余三码设计可逆计数器

电子综合设计第二次设计作业（VHDL语言部分）
（一）以余3码设计一模43的可逆计数器，并将结果以十进制输出。

（设工作频率为20MHz）。

1、程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY f IS
PORT(clk,clr,updn:STD_LOGIC;
bcdn:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY f;
ARCHITECTURE rtl OF f IS
SIGNAL count_7:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL bcd1n:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
bcd1n<=count_7;
B:PROCESS(count_7,clr,clk)IS
BEGIN
IF(clr='1')THEN
count_7<=(OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1')THEN
IF(updn='1'AND count_7=126)THEN
count_7<="0000000";
else
count_7<=count_7+3;
END IF;
IF(updn='0')THEN
count_7<=count_7-3;
END IF;
END IF;
CASE bcd1n IS
WHEN"0000000"=>bcdn<="0000000";
WHEN"0000011"=>bcdn<="0000001";
WHEN"0000110"=>bcdn<="0000010";
WHEN"0001001"=>bcdn<="0000011";
WHEN"0001100"=>bcdn<="0000100";
WHEN"0001111"=>bcdn<="0000101";
WHEN"0010010"=>bcdn<="0000110";
WHEN"0010101"=>bcdn<="0000111";
WHEN"0011000"=>bcdn<="0001000";
WHEN"0011011"=>bcdn<="0001001";
WHEN"0011110"=>bcdn<="0001010";
WHEN"0100001"=>bcdn<="0001011"; WHEN"0100100"=>bcdn<="0001100"; WHEN"0100111"=>bcdn<="0001101"; WHEN"0101010"=>bcdn<="0001110"; WHEN"0101101"=>bcdn<="0001111"; WHEN"0110000"=>bcdn<="0010000"; WHEN"0110011"=>bcdn<="0010001"; WHEN"0110110"=>bcdn<="0010010"; WHEN"0111001"=>bcdn<="0010011"; WHEN"0111100"=>bcdn<="0010100"; WHEN"0111111"=>bcdn<="0010101"; WHEN"1000010"=>bcdn<="0010110"; WHEN"1000101"=>bcdn<="0010111"; WHEN"1001000"=>bcdn<="0011000"; WHEN"1001011"=>bcdn<="0011001"; WHEN"1001110"=>bcdn<="0011010"; WHEN"1010001"=>bcdn<="0011011"; WHEN"1010100"=>bcdn<="0011100"; WHEN"1010111"=>bcdn<="0011101"; WHEN"1011010"=>bcdn<="0011110"; WHEN"1011101"=>bcdn<="0011111"; WHEN"1100000"=>bcdn<="0100000"; WHEN"1100011"=>bcdn<="0100001"; WHEN"1100110"=>bcdn<="0100010"; WHEN"1101001"=>bcdn<="0100011"; WHEN"1101100"=>bcdn<="0100100"; WHEN"1101111"=>bcdn<="0100101"; WHEN"1110010"=>bcdn<="0100110"; WHEN"1110101"=>bcdn<="0100111"; WHEN"1111000"=>bcdn<="0101000"; WHEN"1111011"=>bcdn<="0101001"; WHEN"1111110"=>bcdn<="0101010"; WHEN OTHERS=>bcdn<="XXXXXXX"; END CASE;
END PROCESS;
END ARCHITECTURE rtl;
2、仿真图：
3、设计思想：
定义输入端口，Clk 为时钟脉冲，clr 为清零端，高电平有效，updn 的高低电平分别对应加减计数。

输出为七个端口。

由于采用余三码计数，所以在每个时钟脉冲作用下，对计数值加
3或者减3。

又由于要在端口以十进制输出，则可以用CASE函数，进行枚举。

如0对应输出0，3对应输出1等等。