TLC2543-Q1中文资料

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TLV2543CN;TLV2543CDBR;TLV2543CDW;TLV2543IDB;TLV2543IDW;中文规格书,Datasheet资料

Terminal Functions
TERMINAL NAME AIN0 – AIN10 NO. 1 – 9, 11, 12 15 I/O I DESCRIPTION Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a capacitance of 60 pF. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. Serial data output. This is the 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. Reference +. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF – terminal. Reference –. The lower reference voltage value (nominally ground) is applied to REF –. Positive supply voltage.

TLC2543 芯片资料

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1998, Texas Instruments Incorporated。

TLC2543IDWR;TLC2543CN;TLC2543IN;TLC2543CDB;TLC2543CDW;中文规格书,Datasheet资料

– 55°C to 125°C — — — TLC2543MJ — † Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543IDBR, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or TLC2543IFNR.
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
18 15
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
/
ห้องสมุดไป่ตู้
TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF – AIN10 AIN9
FN PACKAGE (TOP VIEW)
description
The TLC2543C and TLC2543I are 12-bit, switchedcapacitor, successive-approximation, analog-todigital converters. Each device, with three control inputs [chip select (CS), the input-output clock, and the address input (DATA INPUT)], is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.

TLC2543在波导损耗测量系统中的应用

摘要：文介绍了ｌ数模转换芯片ＴＣ５３光波导损耗测试系统中的具体应本２位Ｌ２４在
用。利用８Ｃ１９５单片机、ＴＣ５３Ｒ２２信接口构成的数据采集实时显示系统，Ｌ２４和Ｓ３通在波导损耗测量系统中具有易实现、易编程、精度高等优点，具有良好的推广价值。关键词：波导损耗；ＴＣ５３Ｌ２４；数据采集中图分类号：Ｔ２２文献标识码：ＡＮ５
（ｃｏｌｆｐｏｌｔｎｃｎｏｍａｉ，ＥＴ，ｈｎｄ１０４ＣｉａＳｈｏｏｔ－ｅｒｉＩｆｒｔｎＵＳＣＣｅｇｕ６０５，ｈｎ）Ｏｅｃｏｏ
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TLC2543引脚、功能及时序

TLC2543引脚、功能及时序一、模块采用TI公司的TLC2543 12位串行A/D转换器，使用开关电容逐次逼近技术完成A/D 转换过程。

由于是串行输入结构，能够节省51 系列单片机I/O 资源，且价格适中。

其特点有：(1)12位分辨率A/D转换器；(2)在工作温度范围内10 ys转换时间；( 3) 11 个模拟输入通道；( 4) 3 路内置自测试方式；( 5)采样率为66kbps ；( 6)线性误差+1LSB (max)(7)有转换结束(EOC)输出；( 8)具有单、双极性输出；( 9)可编程的MSB 或LSB 前导；( 10)可编程的输出数据长度。

二、TLC2543 的引脚排列如图所示。

1~9、11、12 —— AIN0〜AIN10为模拟输入端；15 ——CS 为片选端；17——DIN 为串行数据输入端；(控制字输入端，用于选择转换及输出数据格式) 16——DOUT 为A/D 转换结果的三态串行输出端；( A/D 转换结果的输出端。

)19 ——EOC 为转换结束端；18——CLK 为I/O 时钟；(控制输入输出的时钟，由外部输入。

)14 —— REF+为正基准电压端；13 ―― REF-为负基准电压端；20——VCC 为电源；10 ―― GND 为地。

三、TLC2543的使用方法3. 1控制字的格式控制字为从DATAINPUT 端串行输入的8位数据，它规定了 TLC2543要转换的模拟量通道、转换后的输出数据长度、输出数据的格式。

高4位（D7〜D4）决定通道号，对于0通道至10通道，该4位分别为0000〜1010H ,当为1011〜1101时，用于对TLC2543的自检，分别测试（VREF + + VREF— ）/2、VREF ―、VREF + 的值，当为 1110 时，TLC2543 进入休眠状态。

低4位决定输出数据长度及格式，D3、D2决定输出数据长度，01表示输出数据长度为8位，11表示输出数据长度为16位，其他为12位。

TLC2543

摘要：TLC2543是德州仪器公司生产的12位开关电容型逐次逼近模数转换器,它具有三个控制输入端,采用简单的3线SPI串行接口可方便地与微机进行连接,是12位数据采集系统的最佳选择器件之一。

本文介绍了该芯片的功能、时序,并给出了8051单片机的接口电路。

关键词：模数转换器; SPI串行接口; TLC25431. 概述A/D、D/A转换器是过程及仪器仪表、设备等检测与控制装置中应用比较广泛的器件。

随着大规模集成电路技术的发展,各种高精度、低功耗、可编程、低成本的A/D转换器不断推出,使得微机控制系统的电路更加简洁,可靠性更高。

TLC2543与外围电路的连线简单,三个控制输入端为CS(片选)、输入/输出时钟(I/O CLOCK)以及串行数据输入端(DATA INPUT)。

片内的14通道多路器可以选择11个输入中的任何一个或3个内部自测试电压中的一个,采样－保持是自动的,转换结束,EOC输出变高。

TLC2543的主要特性如下：●11个模拟输入通道;●66ksps的采样速率;●最大转换时间为10μs;●SPI串行接口;●线性度误差最大为±1LSB;●低供电电流(1mA典型值);●掉电模式电流为4μA。

2. TLC2543引脚功能与接口时序2.1 TLC2543引脚排列TLC2543的引脚排列如图1所示。

引脚功能说明如下：AIN0～AIN10：模拟输入端,由内部多路器选择。

对4.1MHz的I/O CLOCK,驱动源阻抗必须小于或等于50Ω;CS：片选端,CS由高到低变化将复位内部计数器,并控制和使能DATA OUT、DATA INPUT 和I/O CLOCK。

CS由低到高的变化将在一个设置时间内禁止DATA INPUT和I/O CLOCK;DATA INPUT：串行数据输入端,串行数据以MSB为前导并在I/O CLOCK的前4个上升沿移入4位地址,用来选择下一个要转换的模拟输入信号或测试电压,之后I/O CLOCK将余下的几位依次输入;DATA OUT：A/D转换结果三态输出端,在CS为高时,该引脚处于高阻状态;当CS为低时,该引脚由前一次转换结果的MSB值置成相应的逻辑电平;EOC：转换结束端。

TLC2543 中文资料

TLC2543 中文资料TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2 TLC254 ...TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D 转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2 TLC2543的特点（1）12位分辩率A/D转换器；（2）在工作温度范围内10μs转换时间；（3）11个模拟输入通道；（4）3路内置自测试方式；（5）采样率为66kbps；（6）线性误差±1LSBmax；（7）有转换结束输出EOC；（8）具有单、双极性输出；（9）可编程的MSB或LSB前导；（10）可编程输出数据长度。

3TLC2543的引脚图（管脚图）及说明TLC2543有两种封装形式：DB、DW或N封装以及FN封装，这两种封装的引脚排列如图1，引脚说明见表1。

表1 TLC2543引脚说明引脚号名称I/O 说明1～9,11,12 AIN0～AIN10 I 模拟量输入端。

11路输入信号由内部多路器选通。

对于4.1MHz的I/OCLOCK，驱动源阻抗必须小于或等于50Ω，而且用60pF电容来限制模拟输入电压的斜率15 I 片选端。

在端由高变低时，内部计数器复位。

由低变高时，在设定时间内禁止DATAINPUT和I/O CLOCK17 DATAINPUT I 串行数据输入端。

由4位的串行地址输入来选择模拟量输入通道16 DATA OUT O A/D转换结果的三态串行输出端。

为高时处于高阻抗状态，为低时处于激活状态19 EOC O 转换结束端。

在最后的I/OCLOCK下降沿之后，EOC从高电平变为低电平并保持到转换完成和数据准备传输为止10 GND 地。

关于TLC2543的总结

关于TLC2543的一些问题TLC2543是我调的第四个模块，严格意义上说第三个，因为A/D与D/A是相互配合使用的，在原理上有很多相同的地方。

比如逐次逼近式的A/D转换芯片，内部就存在一个D/A转换器。

总之二者在原理上有相通的地方，下面是我在调试芯片过程中遇到的一些问题：1、下面是它的管脚图以及结构框图：图1、TLC2543NC管脚图图2、2543的结构框图2、它有0~10共11个输入端口，也就是有11个通道，这11个通道是由DA TA IN的高四位决定的，而DA TA IN的低四位决定了是采用8位、12位还是16位数据输出格式，以及输出是单极性输出还是双极性输出，详见表1.需要注意的是这里的DATA IN并不是用于转换的输入数据，而是对输入通道，及一些相关格式的选择数据，相当于命令数据。

DATA OUT是一个串行的输出端，将输入的模拟量转换为数字量后，一位一位输出出来。

转换结束的信号是由EOC决定的，当它为低时表示转换结束，为高时表示正在转换，这里需要注意的是，现在转换的信号，并须在下一次有效输出信号来临时，才被输出；而当前输出的数据世上一次操作转换的结果，所以要输出当前的转换结果，至少要执行两次有效输出，才能得到正确结果。

表1、2543的输入数据功能表3、下面是2543在使用时的两种不同模式，一种是使用~CS端进行控制，一种是不使用。

很显然，第二种，2543时刻都被选通，时刻都在准备进行数据的转换，这样必然会有一定的功耗，所以如果能合理地设计~CS的选通状态，就可以减少电路的功耗。

同样的，还有以8位数据及16位数据格式输出，原理及时序图都与12位的相同，只有输出结果的位数不同，当然，相应的精度也就不同。

可根据具体需要，进行设置。

图3、采用12位输出数据并使用~CS时的序图图4、采用12位输出数据并不使用~CS时的序图。

TL2543

图3.5TLC2543芯片引脚图图3.6内部结构图3.6 TLC2543芯片引脚及内部结构TLC2543是德州仪器公司生产的12位开关电容型逐次逼近模数转换器，最大转换时间10us，11个模拟输入通道，3路内置自测试方式，采样率为66KSPS，线性误差±1LSBmax，有转换结束输出EOC，具有单极、双极性输出，可编程的MSB或LSB前导，可编程输出数据长度。

它具有三个控制输入端，采用简单三线SPI串行接口可方便的与微机进行连接，图3.5和图3.6分别是TLC2543的引脚排列图和内部结构图。

表3.2是TLC2543的引脚功能说明。

3.7 TLC2543的工作方式和输入通道的选择TLC2543是一个多通道和多工作方式的模数转换器件。

图3.5为其芯片引脚图，图3.6是它的内部结构图。

其工作方式和输入通道的选择是通过向TLC2543的控制寄存器写入一个八位的控制字来实现的。

这个八位控制字由四个部分组成：D7D6D5D4选择输入通道，D3D2选择输出数据长度，D1选择输出数据顺序，D0选择转换结果的极性。

八位控制字的各位的含义如表3.3所示。

主机以MSB为前导方式将控制字写入TLC2543的控制寄存器，每个数据位都是在CLOCK序列的上升沿被写入控制器。

表3.2引脚功能说明3.7.1 TLC2543的读写时序当片选信号/CS为高电平时，CLOCK和DATA-IN被禁止、DATA-OUT为高阻状态，以便SPI总线上的其它器件让出总线。

在片选信号/CS的下降沿，A/D转换结果的第一位数据出现在DATA-OUT引脚上，A/D转换结果的其他数据位在时钟信号CLOCK的下降沿被串行输出到DATA-OUT。

在片选信号/CS下降以后，时钟信号CLOCK的前八个上升沿将八位控制字从DATA_IN引脚串行输入到TLC2543的控制寄存器。

在片选信号/CS下降以后，经历8个(12个或16个)时钟信号完成对A/D转换器的一次读写。

TLC2543中文资料_数据手册_参数

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合格的汽车ApplicationsD 12位分辨率A / D ConverterD 10-µs转换时间在OperatingTemperatureD 11模拟输入ChannelsD三内建自测ModesD固有取样保持的FunctionD线性误差。±1 LSB MaxD片上TLC2543系统ClockD转换末尾OutputD单极或双极输出操作(签署二进制对1/2 theApplied参考电压)D可编程MSB和LSB FirstD可编程电源DownD可编程输出数据LengthD CMOS TechnologyD申请报告可用‡ descriptionThe TLC2543 12位,开关电容,逐次逼近,数模转换器。每台设备有三个控制输入(芯片选择(CS)、输入-输出时钟和地址输入(数据输入))，通过串行三态输出与主机处理器或外围设备的串口通信。该设备允许从主机高速传输数据。除了高速转换器和多用途控制能力，该设备还有一个芯片上的14通道多路复用器，可以选择11个输入中的任意一个或3个内部自检电压中的任意一个。这个功能是自动的。在转换结束时，转换结束(EOC)输出变高，表示转换已经完成。TLC2543集成在器件中的转换器具有不同的高阻抗参考输入，便于比值转换、缩放和模拟电路与逻辑和电源噪声隔离。开关电容设计允许在整个工作温度范围内的低误差转换。订货信息工作原理首先，芯片选择(CS)高，I/O时钟和数据输入被禁用，TLC2543数据输出处于高阻抗状态。CS低电平通过启用I/O时钟和数据输入开始转换序列，并从高阻抗状态中删除数据。输入数据为8位数据流，包括4位模拟信道地址(D7−D4)、2位数据纵向选择(D3−D2)、输出MSB或LSB 第一个位(D1)和应用于数据输入的单极或双极输出选择位(D0)。TLC2543应用于I/O时钟终端的I/O时钟序列将此数据传输到输入数据寄存器。在这个传输过程中，I/O时钟序列还将之前的转换结果从输出数据寄存器转移到数据输出。I/O时钟接收8、12或16个时钟周期长的输入序列，这取决于输入数据寄存器中的数据长度选择。TLC2543模拟输入的采样从输入I/O时钟序列的第四个下降沿开始，并在I/O 时钟序列的最后一个下降沿之后进行。I/O时钟序列的最后一个下降沿也将EOC降低并开始转换。转换器的操作转换器的操作被组织成两个不同的周期的序列:1)I/O周期和2)实际的转换周期。I/O周期I/O周期由外部提供的I/O时钟定义，持续8、12或16个时钟周期，取决于所选输出数据的长度。在I/O周期中，同时执行以下两个操作。一个由地址和控制信息组成的8位数据流被提供给数据输入。这些数据被转移到前八个I/O时钟上升边缘的设备中。在12或16个时钟的I/O传输过程中，第一个时钟后的数据输入将被忽略。数据输出(长度为 8、12或16位)是在数据输出时串行提供的。当CS值较低时，第一个输出数据位出现在EOC上升沿。当CS在两次转换之间被否定时，第一个outputdata位出现在CS的下降边缘。该数据是前一个转换周期的结果，在第一个输出数据位之后，每个后续的位都被锁定在每个后续I/O时钟的下降边缘。转换周期转换周期对用户是透明的，它由一个内部时钟同步toI/O时钟控制。在转换期间，该装置对模拟输入电压进行逐次近似转换。EOC输出在转换周期开始时较低，在转换完成并锁定输出数据寄存器时较高。转换周期只有在I/Ocycle完成后才开始，这样可以将外部数字噪声对转换精度的影响降到最低。

我的TLC2543学习笔记——基于msp430g2553单片机

我的TLC2543学习笔记——基于msp430g2553单⽚机还是贴不了图⽚我的TLC2543学习笔记Created on: 2012-9-8Author: zhang bin学习笔记for msp430g2553redesigned by zhang bin2012-09-08versions：12_09_01All Rights ReservedTLC2543具有4线制串⾏接⼝，分别为⽚选端(CS)，串⾏时钟输⼊端(I/O CLOCK)，串⾏数据输⼊端(DATA IN)和串⾏数据输出端(DATA OUT)（转换结束脚EOC可以不接）。

它可以直接与SPI器件进⾏连接，不需要其他外部逻辑。

同时，它还在⾼达4MHz的串⾏速率下与主机进⾏通信。

TLC2543的特点及引脚TLC2543是TI的12 bit串⾏A／D转换器，11个模拟输⼊通道。

使⽤开关电容逐次逼近技术完成，A／D转换过程．由于是串⾏输⼊结构，能够MCU的I／O资源．其特点有：1)12 bit分辨率A／D转换器；2)在⼯作温度范围内10us转换时间；3)11个模拟输⼊通道；4)3路内置⾃测试⽅式；5)采样率为66 kb／s；6)线性误差+1LSB(max)；7)有转换结束(EOC)输出；8)具有单、双极性输出；9)可编程的MSB或LSB前导；10)可编程的输出数据长度．�� 12-Bit-Resolution A/D Converter�� 10-µs Conversion Time Over OperatingTemperature�� 11 Analog Input Channels�� 3 Built-In Self-Test Modes�� Inherent Sample-and-Hold Function�� Linearity Error . . . ±1 LSB Max�� On-Chip System Clock�� End-of-Conversion Output�� Unipolar or Bipolar Output Operation(Signed Binary With Respect to 1/2 theApplied Voltage Reference)�� Programmable MSB or LSB First�� Programmable Power Down�� Programmable Output Data Length�� CMOS Technology�� Application Report Available我⽤的tlc2543是直插的，引脚图如下：各引脚的详细说明如下：引脚号名称I/O说明1～9,11,12AIN0～AIN10I模拟量输⼊端。

TLC2543

TLC2543在仪器仪表中的应用摘要介绍TI公司的TLC2543的特性，与51系列单片机的接口以及在仪器仪表中的应用。

关键词串行A/D应用1引言TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2TLC2543的特点（1）12位分辩率A/D转换器；（2）在工作温度范围内10μs转换时间；（3）11个模拟输入通道；（4）3路内置自测试方式；（5）采样率为66kbps；（6）线性误差±1LSBmax；（7）有转换结束输出EOC；（8）具有单、双极性输出；（9）可编程的MSB或LSB前导；（10）可编程输出数据长度。

3TLC2543的引脚排列及说明TLC2543有两种封装形式：DB、DW或N封装以及FN封装，这两种封装的引脚排列如图1，引脚说明见表1。

图1TLC2543的封装表1TLC2543引脚说明4接口时序可以用四种传输方法使TLC2543得到全12位分辩率，每次转换和数据传递可以使用12或16个时钟周期。

一个片选（）脉冲要插到每次转换的开始处，或是在转换时序的开始处变化一次后保持为低，直到时序结束。

图2显示每次转换和数据传递使用16个时钟周期和在每次传递周期之间插入的时序，图3显示每次转换和数据传递使用16个时钟周期，仅在每次转换序列开始处插入一次时序。

图216时钟传送时序图（使用，MSB在前）图316时钟传送时序图（不使用，MSB在前）5TLC2543在智能仪器仪表中的应用TLC2543是12位分辩率，与MAX186在功能上基本相同，但价格比MAX186低得多，因此TLC2543在便携式数据记录仪、医用仪器、电力检测仪表中具有广泛的应用。

下面主要讲述TLC2543在电力监控显示屏中的应用。

在电厂和变电站中，电网中的电压和电流由于多种原因常常处于波动状态，为了给工作人员提供有效数据，并在超值范围内采取有效措施，监测电网中电压和电流值是非常必要的。

TLC2543QDWREP;TLC2543MDBREP;中文规格书,Datasheet资料

FEATURES(TOP VIEW)DW PACKAGE DESCRIPTION/ORDERING INFORMATION•Controlled Baseline•Programmable Power Down–One Assembly/Test Site,One Fabrication •Programmable Output Data Length Site•CMOS Technology•Extended Temperature Performance of –40°C •Application Report Available (2)to 125°C (TLC2543Q)and –55°C to 125°C (TLC2543M)•Enhanced Diminishing Manufacturing Sources (DMS)Support•Enhanced Product Change Notification •Qualification Pedigree (1)•12-Bit-Resolution Analog-to-Digital Converter (ADC)•10-µs Conversion Time Over Operating Temperature•11Analog Input Channels•Three Built-In Self-Test Modes•Inherent Sample-and-Hold Function •Linearity Error ...±1LSB Max •On-Chip System Clock•End-of-Conversion (EOC)Output•Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2the Applied Voltage Reference)•Programmable Most Significant Bit (MSB)or Least Significant Bit (LSB)First(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over anextended temperature range.This includes,but is not limited to,Highly Accelerated Stress Test (HAST)or biased 85/85,temperature cycle,autoclave or unbiased HAST,electromigration,bond intermetallic life,and mold compound life.Such qualification testing should not be viewed as justifying use of this component beyond specified (2)Microcontroller Based Data Acquisition Using the TLC2543performance and environmental limits.12-bit Serial-Out ADC (SLAA012)The TLC2543is a 12-bit,switched-capacitor,successive-approximation,analog-to-digital converter (ADC).This device,with three control inputs [chip select (CS),input-output clock (I/O CLOCK),and address input (DATA INPUT)],is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output.The device allows high-speed data transfers from the host.In addition to the high-speed converter and versatile control capability,the device has an on-chip 14-channel multiplexer that can select any 1of 11inputs or any 1of 3internal self-test voltages.The sample-and-hold function is automatic.At the end of conversion,the end-of-conversion (EOC)output goes high to indicate that conversion is complete.The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion,scaling,and isolation of analog circuitry from logic and supply noise.A switched-capacitor design allows low-error conversion over the full operating temperature range.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright ©2002–2006,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.DATA OUTDATA INPUT CSEOCAIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9AIN10SGLS125A–JULY 2002–REVISED NOVEMBER 2006ORDERING INFORMATIONT APACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 125°C SOP –DW Tape and reel TLC2543QDWREP TLC2543QEP -55°C to 125°C SSOP -DBTape and ReelTLC2543MDBREPTLC2543MEP(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at /sc/package.FUNCTIONAL BLOCK DIAGRAM2Submit Documentation FeedbackTERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.AIN01AIN12AIN23AIN34AIN45Analog input.These11analog-signal inputs are internally multiplexed.The driving sourceAIN56I impedance should be less than or equal to50Ωfor4.1-MHz I/O CLOCK operation,and be capable AIN67of slewing the analog input voltage into a capacitance of60pF.AIN78AIN89AIN911AIN1012Chip select.A high-to-low transition on CS resets the internal counters and controls and enablesCS15I DATA OUT,DATA INPUT,and I/O CLOCK.A low-to-high transition disables DATA INPUT and I/OCLOCK within a setup time.Serial-data input.A4-bit serial address selects the desired analog input or test voltage to beconverted next.The serial data is presented with the most significant bit(MSB)first and is shifted in DATA INPUT17Ion the first four rising edges of I/O CLOCK.After the four address bits are read into the addressregister,I/O CLOCK clocks the remaining bits in order.The3-state serial output for the A/D conversion result.DATA OUT is in the high-impedance statewhen CS is high and active when CS is low.With a valid CS,DATA OUT is removed from thehigh-impedance state and is driven to the logic level corresponding to the most significant bit/least DATA OUT16Osignificant bit(MSB/LSB)value of the previous conversion result.The next falling edge of I/OCLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB,and the remainingbits are shifted out in order.End of conversion.EOC goes from a high to a low logic level after the falling edge of the last I/O EOC19OCLOCK and remains low until the conversion is complete and the data is ready for transfer.Ground.GND is the ground return terminal for the internal circuitry.Unless otherwise noted,allGND10voltage measurements are with respect to GND.Input/output clock.I/O CLOCK receives the serial input and performs the following four functions:•It clocks the eight input data bits into the input data register on the first eight rising edges of I/OCLOCK with the multiplexer address available after the fourth rising edge.•On the fourth falling edge of I/O CLOCK,the analog input voltage on the selected multiplexer inputbegins charging the capacitor array and continues to do so until the last falling edge of the I/OI/O CLOCK18ICLOCK.•It shifts the11remaining bits of the previous conversion data out on DATA OUT.Data changes onthe falling edge of I/O CLOCK.•It transfers control of the conversion to the internal state controller on the falling edge of the lastI/O CLOCK.Positive reference voltage.The upper reference voltage value(nominally V CC)is applied to REF+. REF+14I The maximum input voltage range is determined by the difference between the voltage applied tothis terminal and the voltage applied to the REF–terminal.Negative reference voltage.The lower reference voltage value(nominally ground)is applied toREF–13IREF–.V CC20Positive supply voltage3Submit Documentation FeedbackAbsolute Maximum Ratings (1)Recommended Operating ConditionsSGLS125A–JULY 2002–REVISED NOVEMBER 2006over operating free-air temperature range (unless otherwise noted)MINMAX UNIT V CC Supply voltage range (2)–0.5 6.5V V CC +V I Input voltage range (any input)–0.3V 0.3V CC +V O Output voltage range –0.3V 0.3V CC +V ref+Positive reference voltage V 0.1V ref–Negative reference voltage –0.1V I I Peak input current (any input)±20mA I I Peak total input current (all inputs)±30mA TLC2543Q –40125T A Operating free-air temperature range °C TLC2543M-55125T stg Storage temperature range–65150°C Lead temperature 1,6mm (1/16in)from the case for 10s260°C(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to the GND terminal with REF–and GND wired together (unless otherwise noted).(1)Analog input voltages greater than that applied to REF+convert as all ones (111111111111),while input voltages less than that applied to REF–convert as all zeros (000000000000).(2)To minimize errors caused by noise at the CS input,the internal circuitry waits for a setup time after CS ↓before responding to control input signals.No attempt should be made to clock in an address until the minimum CS setup time has elapsed.(3)This is the time required for the clock input signal to fall from V IH min to V IL max or to rise from V IL max to V IH min.In the vicinity of normal room temperature,the devices function with input clock transition time as slow as 1µs for remote data acquisition applications where the sensor and the ADC are placed several feet away from the controlling microprocessor.4Submit Documentation FeedbackElectrical Characteristicsover recommended operating free-air temperature range,VCC =Vref+=4.5V to5.5V,f(I/O CLOCK)=4.1MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP(1)MAX UNITV CC=4.5V,I OH=–1.6mA 2.4V OH High-level output voltage VV CC=4.5V to5.5V,I OH=–20µA V CC–0.1V CC=4.5V,I OL=1.6mA0.4V OL Low-level output voltage VV CC=4.5V to5.5V,I OL=20µA0.1V O=V CC,CS at V CC1 2.5 High-impedance off-stateI OZµAoutput current VO=0,CS at V CC1–2.5I IH High-level input current V I=V CC110µAI IL Low-level input current V I=01–10µAI CC Operating supply current CS at0V1 2.5mAFor all digital inputs,I CC(PD)Power-down current425µA0≤V I≤0.5V or V I≥V CC–0.5VSelected channel at V CC,Unselected channel at0V10 Selected channelµA leakage current Selected channel at0V,Unselected channel at VCC–10Maximum static analogV ref+=V CC,V ref–=GND1 2.5µA reference current into REF+Analog inputs3060 InputC i pFcapacitance Control inputs515(1)All typical values are at V CC=5V,T A=25°C.5Submit Documentation FeedbackOperating CharacteristicsSGLS125A–JULY2002–REVISED NOVEMBER2006over recommended operating free-air temperature range,VCC =Vref+=4.5V to5.5V,f(I/O CLOCK)=4.1MHz(1)All typical values are at T A=25°C.(2)Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.(3)Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gainpoint after the offset error has been adjusted to zero.Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point.(4)Analog input voltages greater than that applied to REF+convert as all ones(111111111111),while input voltages less than that appliedto REF–convert as all zeros(000000000000).(5)Total unadjusted error comprises linearity,zero-scale,and full-scale errors.(6)Both the input address and the output codes are expressed in positive logic.(7)I/O CLOCK period=1/(I/O CLOCK frequency)(see Figure7)(8)Any transitions of CS are recognized as valid only is maintained for a setup time.CS must be taken low at≤5µs of thetenth I/O CLOCK falling edge to ensure a conversion is aborted.Between5µs and10µs,the result is uncertain as to whether the conversion is aborted or the conversion results are valid.6Submit Documentation FeedbackPARAMETER MEASUREMENT INFORMATIONC110 µF−15 VVC110 µFLOCATIONU1C1C2C3DESCRIPTIONOP2710-µF 35-V tantalum capacitor0.1-µF ceramic NPO SMD capacitor470-pF porcelain Hi-Q SMD capacitorPART NUMBER——AVX 12105C104KA105 or equivalentJohanson 201S420471JG4L or equivalentEOCC LVR L = 2.18 kΩC LVR L = 2.18 kΩCSDATAOUTtI/O CLOCKFigure1.Analog Input Buffer to Analog Inputs AIN0–AIN10Figure2.Load CircuitsFigure3.DATA OUT to Hi-Z Voltage Waveforms Figure4.DATA INPUT and I/O CLOCKVoltage Waveforms7Submit Documentation FeedbackCSI/O CLOCKI/O CLOCKDATA OUTt t EOCDATA OUTSGLS125A–JULY 2002–REVISED NOVEMBER 2006A.To ensure full conversion accuracy,it is recommended that no input signal change occurs while a conversion is ongoing.Figure 5.CS and I/O CLOCK Voltage WaveformsFigure 6.I/O CLOCK and DATA OUT Voltage WaveformsFigure 7.I/O CLOCK and EOC Voltage WaveformsFigure 8.EOC and DATA OUT Voltage Waveforms8Submit Documentation FeedbackA.To minimize errors caused by noise at CS,the internal circuitry waits for a setup time after CS ↓before responding to control input signals.Therefore,no attempt should be made to clock in an address until the minimum CS setup time has elapsed.Figure 9.Timing for 12-Clock Transfer Using CS With MSB FirstA.To minimize errors caused by noise at CS,the internal circuitry waits for a setup time after CS ↓before responding to control input signals.Therefore,no attempt should be made to clock in an address until the minimum CS setup time has elapsed.Figure 10.Timing for 12-Clock Transfer Not Using CS With MSB First9Submit Documentation FeedbackI/O CLOCKDATA OUT DATA INPUTCSEOCSGLS125A–JULY 2002–REVISED NOVEMBER 2006A.To minimize errors caused by noise at CS,the internal circuitry waits for a setup time after CS ↓before responding to control input signals.Therefore,no attempt should be made to clock in an address until the minimum CS setup time has elapsed.Figure 11.Timing for 8-Clock Transfer Using CS With MSB FirstA.To minimize errors caused by noise at CS,the internal circuitry waits for a setup time after CS ↓before responding to control input signals.Therefore,no attempt should be made to clock in an address until the minimum CS setup time has elapsed.Figure 12.Timing for 8-Clock Transfer Not Using CS With MSB First10Submit Documentation Feedback分销商库存信息:TITLC2543QDWREP TLC2543MDBREP。

TLC2543及其接口电路

TLC2543在仪器仪表中的应用摘要介绍TI公司的TLC2543的特性，与51系列单片机的接口以及在仪器仪表中的应用。

关键词串行A/D应用1引言TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2TLC2543的特点（1）12位分辩率A/D转换器；（2）在工作温度范围内10μs转换时间；（3）11个模拟输入通道；（4）3路内置自测试方式；（5）采样率为66kbps；（6）线性误差±1LSBmax；（7）有转换结束输出EOC；（8）具有单、双极性输出；（9）可编程的MSB或LSB前导；（10）可编程输出数据长度。

3TLC2543的引脚排列及说明TLC2543有两种封装形式：DB、DW或N封装以及FN封装，这两种封装的引脚排列如图1，引脚说明见表1。

图1TLC2543的封装表1TLC2543引脚说明4接口时序可以用四种传输方法使TLC2543得到全12位分辩率，每次转换和数据传递可以使用12或16个时钟周期。

一个片选（）脉冲要插到每次转换的开始处，或是在转换时序的开始处变化一次后保持为低，直到时序结束。

下面主要讲述TLC2543在电力监控显示屏中的应用。

TLC2543中文数据手册

TLC2543使用手册一、简要说明：TLC2543是一款8位、10位、12位为一体的可选输出位数的11通道串行转换芯片。

每一路转换时间为10us。

外部输入信号为：DATA input ；_CS；AD_IO_CLK;Analog input；四种信号；输出为：EOC转换结束信号，DATA output信号。

工作原理为：_CS由高变为低时候，允许DATA input；AD_IO_CLK;Analog input信号输入，DATA out 信号输出；由低到高禁止DATA input；AD_IO_CLK;信号输入。

当忽略ADC转换启动的CS时候，数据的输出是在CS的下降沿，既是将片选的时候，而考虑到CS时候，第一个输出数据发生在EOC变为高的时候的上升沿。

注意：初始化时候，必须将CS由高拉低才能进行数据输出或者是数据输入。

也就是说，当一次转换完成后，进行下一次或者是下一个通道的转换，需要将CS由低拉高，为下一次转换做好准备，当进行下一个转换时候，进行CS 拉低，DATA input输入或者DATA out输出(忽略CS转换作用时候)。

信号解释：DATA input：4位串行地址输入，用来选择模拟输入通道功能或者测试引脚；高位在前，在每一个AD_IO_CLK的上升沿输入ADC的寄存器。

由八位组成：前四位：D7:D4用作选择模拟输入通道，D3:D2用作选择数据长度，D1是选择输出高低位顺序的，D0选择是选择输出极性（单双极性）。

DA TA INPUT的表含义DATA OUT：当_CS为高时DATA out输出为高阻抗，当CS有效时，驱动转换结果，并在AD_IO_CLK的下降沿按位顺序输出。

EOC：ADC的EOC在DATA input输入的最后一个AD_IO_CLK时，由高变为低，并保持到转换结束和数据准备输出结束时候变为高。

AD_IO_CLK:输入和输出时钟，主要完成以下功能：A、在IO_CLK的前八个时钟的上升沿将DATA input的八位数据输入数据寄存器中。

12位TLC2543模数转换总结

Lcd_wcd(1,0x30+bai);
Lcd_wcd(1,0x2e);
Lcd_wcd(1,0x30+shi);
Lcd_wcd(1,0x30+ge);
Lcd_wcd(1,0x30+xiao);
/*for(i=0;i<SUM;i++)
{
temp1+=redad(0x01);//选择通道1，并读取AD转换的数
GND
地。GND是内部电路的地回路端。除另有说明外，所有电压测量都相对GND而言
18
I/O CLOCK
I
输入/输出时钟端。I/OCLOCK接收串行输入信号并完成以下四个功能：（1）在I/O CLOCK的前8个上升沿，8位输入数据存入输入数据寄存器。（2）在I/OCLOCK的第4个下降沿，被选通的模拟输入电压开始向电容器充电，直到I/OCLOCK的最后一个下降沿为止。（3）将前一次转换数据的其余11位输出到DATA OUT端，在I/OCLOCK的下降沿时数据开始变化。（4）I/OCLOCK的最后一个下降沿，将转换的控制信号传送到内部状态控制位
//uchar code dis1[]={"采集电压：000 v"};
/*************延时**************/
void delay(uint z)
{//一毫秒
uint y;
for(;z>0;z--)
for(y=110;y>0;y--) ;
}
void delay_us(uchar n)//微秒
shi=x/1000%10;
ge=x/100%10;
xiao=x/10%10;
}
/****************主函数****************/

TLC2543中文资料

串行A D转换器T L C2543中文资料T L C2543是T I公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2T L C2543的特点（1）12位分辩率A/D转换器；（2）在工作温度范围内10μs转换时间；（3）11个模拟输入通道；（4）3路内置自测试方式；（5）采样率为66k b p s；（6）线性误差±1L S B m a x；（7）有转换结束输出E O C；（8）具有单、双极性输出；（9）可编程的M S B或L S B前导；（10）可编程输出数据长度。

3T L C2543的引脚排列及说明T L C2543有两种封装形式：D B、D W或N封装以及F N封装，这两种封装的引脚排列如图1，引脚说明见表1。

图1T L C2543的封装4接口时序可以用四种传输方法使T L C2543得到全12位分辩率，每次转换和数据传递可以使用12或16个时钟周期。

一个片选（）脉冲要插到每次转换的开始处，或是在转换时序的开始处变化一次后保持为低，直到时序结束。

引脚号名称I/O说明1～9,11,12AIN0～AIN10I模拟量输入端。

11路输入信号由内部多路器选通。

对于4.1MHz的I/OCLOCK，驱动源阻抗必须小于或等于50Ω，而且用60pF电容来限制模拟输入电压的斜率15I片选端。

在端由高变低时，内部计数器复位。

由低变高时，在设定时间内禁止DATAINPUT和I/O CLOCK17DATAINPUT I串行数据输入端。

由4位的串行地址输入来选择模拟量输入通道16DATA OUT O A/D转换结果的三态串行输出端。

TLC2543

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Mailing Address:Texas InstrumentsPost Office Box 655303Dallas, Texas 75265Copyright 2001, Texas Instruments IncorporatedThis datasheet has been download from: Datasheets for electronics components.。

TLC2543中文资料

串行A D转换器T L C2543中文资料TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。

由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。

2TLC2543的特点（1）12位分辩率A/D转换器；（2）在工作温度范围内10μs转换时间；（3）11个模拟输入通道；（4）3路内置自测试方式；（5）采样率为66kbps；（6）线性误差±1LSBmax；（7）有转换结束输出EOC；（8）具有单、双极性输出；（9）可编程的MSB或LSB前导；（10）可编程输出数据长度。

3TLC2543的引脚排列及说明TLC2543有两种封装形式：DB、DW或N封装以及FN封装，这两种封装的引脚排列如图1，引脚说明见表1。

图1T L C2543的封装4接口时序可以用四种传输方法使T L C2543得到全12位分辩率，每次转换和数据传递可以使用12或16个时钟周期。

一个片选（）脉冲要插到每次转换的开始处，或是在转换时序的开始处变化一次后保持为低，直到时序结束。

引脚号名称I/O说明1～9,11,12AIN0～AIN10I模拟量输入端。

11路输入信号由内部多路器选通。

对于的I/OCLOCK，驱动源阻抗必须小于或等于50Ω，而且用60pF电容来限制模拟输入电压的斜率15I片选端。

在端由高变低时，内部计数器复位。

由低变高时，在设定时间内禁止DATAINPUT和I/OCLOCK17DATAINPUT I串行数据输入端。

由4位的串行地址输入来选择模拟量输入通道16DATAOUT O A/D转换结果的三态串行输出端。

为高时处于高阻抗状态，为低时处于激活状态19EOC O转换结束端。

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PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)TLC2543IDBRQ1ACTIVESSOPDB202000Pb-Free (RoHS)CU NIPDAULevel-2-250C-1YEAR/Level-1-235C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -May not be currently available -please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead (Pb-Free).Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean "Pb-Free"and in addition,uses package materials that do not contain halogens,including bromine (Br)or antimony (Sb)above 0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,andthus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM25-Feb-2005Addendum-Page 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。