STATIC AND DYNAMIC BRANCH PREDICTION USING NEURAL NETWORKS
计算机组成与结构第四版(王爱英著)清华大学出版社课后答案(全)

计算机的算术运算
单精度浮点数
1000 1111 1110 1111 1100 0000 0000 0000 S E F S =(-1)1=-1 E =00011111=3110 F’ =110+(110 1111 1100 0000 0000 0000)2
单精度浮点数=S×F’×2E
WANG Wei, Computer Organization and Architecture, Copyright 2004 TJU
若它分别表示如下所示的三种数,那么他们 的含义各是什么?
2的补码表示的整数 无符号整数 单精度浮点数
WANG Wei, Computer Organization and Architecture, Copyright 2004 TJU
计算机的算术运算
分析与解答:
2的补码表示的整数
(1000 1111 1110 1111 1100 0000 0000 0000)补 =(1111 0000 0001 0000 0100 0000 0000 0000)原 =-(111 0000 0001 0000 0100 0000 0000 0000) =-188011315210
WANG Wei, Computer Organization and Architecture, Copyright 2004 TJU
计算机的逻辑部件
+6
WANG Wei, Computer Organization and Architecture, Copyright 2004 TJU
计算机的逻辑部件
0100 0001 0010 1000 0000 0000 0000 0000
WANG Wei, Computer Organization and Architecture, Copyright 2004 TJU
计算机术语与中文解释对照

3C(China Compulsory Certification,中国强制性产品认证制度)3D(Three Dimensional,三维)3DCG(3D computer graphics,三维计算机图形)3DNow!(3D no waiting,无须等待的3D处理)3DPA(3D Positional Audio,3D定位音频)3DS(3D SubSystem,三维子系统)3GIO(Third Generation Input/Output,第三代输入输出技术)AA(Accuview Antialiasing,高精度抗锯齿)AAC(Advanced Audio Compression,高级音频压缩)AAM(AMD Analyst Meeting,AMD分析家会议)AAM(Automatic Acoustic Management,自动机械声学管理)AAS(Automatic Area Segments)AAT(Average access time,平均存取时间)ABB(Advanced Boot Block,高级启动块)ABP(Address Bit Permuting,地址位序列改变)ABP(Advanced Branch Prediction,高级分支预测)ABS(Auto Balance System,自动平衡系统)A-Buffer(Accumulation Buffer,积聚缓冲)AC(Acoustic Edge,声学边缘)AC(Audio Codec,音频多媒体数字信号编解码器)AC-3(Audio Coding 3,第三代音响编码)AC97(Audio Codec 97,多媒体数字信号解编码器1997年标准)ACCP(Applied Computing Platform Providers,应用计算平台提供商)ACG(Aggressive Clock Gating,主动时钟选择)ACIRC(Advanced Cross Interleave Reed - Solomon Code,高级交叉插入里德所罗门代码)ACOPS(Automatic CPU OverHeat Prevention System(CPU过热预防系统)ACPI(Advanced Configuration and Power Interface,先进设置和电源管理)ACR(Advanced Communications Riser,高级通讯升级卡)ACS(Access Control Software,存取控制软件)ACT(Action,动作类游戏)AD(Analog to Digitalg,模拟到数字转换)ADC(Analog to Digital Converter,模数传换器)ADC(Apple Display Connector,苹果专用显示器接口)ADI(Adaptive De-Interlacing,自适应交错化技术)ADIMM(advanced Dual In-line Memory Modules,高级双重内嵌式内存模块)ADIP(Address In Pre-Groove,预凹槽寻址)ADSL(Asymmetric Digital Subscriber Line,不对称数字订阅线路)ADT(Advanced DRAM Technology,高级内存技术)AE(Atmospheric Effects,大气雾化效果)AE(Auto Focus,自动测光)AES-OCB(Advanced Encryption Standard-Operation Cipher Block,高级加密标准-操作密码块)AF(Auto Focus,自动对焦)AFC media(antiferromagnetically coupled media,反铁磁性耦合介质)AFC(Advanced Frame Capture、高级画面捕获)AFC(Amplitude-frequency characteristic,振幅频率特征)AFE(Analog Front End,模拟前置)AFM(Atomic Force Microscope,原子力显微镜)AFR(Alternate Frame Rendering,交替渲染技术)AG(Aperture Grills,栅条式金属板)AGBS(Advance GameBoy development System,高级GameBoy发展系统)AGC(Anti Glare Coatings,防眩光涂层)AGP(Accelerated Graphics Port,图形加速接口)AGPS(Assisted Global Positioning System,援助全球定位系统)AGTL+(Assisted Gunning Transceiver Logic,援助发射接收逻辑电路)AGU(Address Generation Units,地址产成单元)AH(Authentication Header,鉴定文件头)AHA(Accelerated Hub Architecture,加速中心架构)AI(Artificial Intelligence,人工智能)AIMM(AGP Inline Memory Module,AGP板上内存升级模块)AIS(Alternate Instruction Set,交替指令集)AL(Additive Latency,附加反应时间)AL(Artificial Life,人工生命)ALAT(advanced load table,高级载入表)ALDC(Adaptive Lossless Data Compression,适应无损数据压缩)ALU(Arithmetic Logic Unit,算术逻辑单元)Aluminum(铝)AM(Acoustic Management,声音管理)AMC(audio/modem codec,音频/调制解调器多媒体数字信号编解码器)AMR(Audio/Modem Riser,音效/调制解调器主机板附加直立插卡)An isotropic Filtering(各向异性过滤)ANSI(American National Standards Institute,美国国立标准协会)AOI(Automatic Optical Inspection,自动光学检验)AOL(Alert On LAN,局域网警告)APC(Advanced Power Control,高级能源控制)API(Application Programming Interfaces,应用程序接口)APIC(Advanced Programmable Interrupt Controller,高级可编程中断控制器)APM(Advanced Power Management,高级能源管理)APPE(Advanced Packet Parsing Engine,增强形帧解析引擎)APS(Alternate Phase Shifting,交替相位跳转)APS(Audio Production Studio,音频生产工作室)APU(Audio Processing Unit,音频处理单元)APX(All Position eXpansion,全方位扩展)AR(Auto-Resume,自动恢复)ARC(Anti Reflect Coating,防反射涂层)ARF(Asynchronous Receive FIFO,异步接收先入先出)ARP(Address Resolution Protocol,地址解析协议)ARPG(Action Role Play Games,动作角色扮演游戏)ARR(Annual Return Rate,年返修率)ASB(Advanced System Buffering,高级系统缓冲)ASC(Advanced Size Check,高级尺寸检查)ASC(Anti Static Coatings,防静电涂层)ASC(Auto-Sizing and Centering,自动调效屏幕尺寸和中心位置)ASCI(The 10-year Accelerated Strategic Computing Initiative,领先10年战略加速计算机)ASCII(American Standard Code for Information Interchange,美国国家标准信息交换代码)ASD(Auto Stereoscopic Display,自动立体显示)ASF(Advanced Streaming Format,高级数据流格式)ASF(Alert Standards Forum,警告标准讨论)ASIC(Application Specific Integrated Circuit,特殊应用积体电路)ASIO(Audio Streaming Input and Output interface,音频流输入输出接口)ASK IR(Amplitude Shift Keyed Infra-Red,长波形可移动输入红外线)ASMO(Advanced Storage Magneto-Optical,增强形光学存储器)ASP(Active Server Pages,活动服务页)ASP(Application Service Provider,应用服务提供商)ASPI(Advanced SCSI Programming Interface,高级SCSI可编程接口)AST(amorphous-silicon TFT,非晶硅薄膜晶体管)AST(Average Seek time,平均寻道时间)AT(Advanced Technology,先进技术)ATA(Advanced Technology Attachment,高级技术附加装置)ATAPI(AT Attachment Packet Interface,AT扩展包接口)ATC(Access Time from Clock,时钟存取时间)ATC(Advanced Transfer Cache,高级转移缓存)ATD(Assembly Technology Development,装配技术发展)ATL(ActiveX Template Library,ActiveX模板库)ATM(Asynchronous Transfer Mode,异步传输模式)ATM(Automatic Teller Machine,自动提款机)ATOMM(Advanced super Thin-layer and high-Output Metal Media,增强形超薄高速金属媒体)ATP(Active to Precharge,激活到预充电)ATRAC(Adaptive TRansform Acoustic Coding,可适应转换声学译码)ATSC(Advanced Television Systems Committee,高级电视系统委员会)ATX(AT Extend,扩展型AT)AUD_EXT(Audio Extension,音频扩展)AUX(Auxiliary Input,辅助输入接口)AV(Analog Video,模拟视频)AV(Audio & Video,音频和视频)AVG(Adventure Genre,冒险类游戏)AVI(Audio Video Interleave,音频视频插入)B Splines(B样条)B.O.D.E(Body Object Design Envioment,人体/物体/设计/环境渲染自动识别)BAC(Bad Angle Case,边角损坏采样)Back Buffer(后置缓冲)Backface culling(隐面消除)BAD(Best Amiga Dominators)BASIC(Beginner s All-purpose Symbolic Instruction Codec,初学者通用指令代码)Battle for Eyeballs(眼球大战)BBS(BIOS Boot Specification,基本输入/输出系统启动规范)BBUL(Bumpless Build-Up Layer,内建非凹凸层)BCF(Boot Catalog File,启动目录文件)BEDO(Burst Enhanced Data-Out RAM,突发型数据增强输出内存)Benchmarks(基准测试程序数值BGA(Ball Grid Array,球状网阵排列)BHT(branch prediction table,分支预测表)BIF(Boot Image File,启动映像文件)Bilinear Filtering(双线性过滤)BIOS(Basic Input/Output System,基本输入/输出系统)BLA(Bearn Landing Area,电子束落区)BLP(Bottom Leaded Package,底部导向封装)BMC(Black Matrix Screen,超黑矩阵屏幕)BMS(Blue Magic Slot,蓝色魔法槽)BOD(Bandwidth On Demand,弹性带宽运用)BOPS(Billion Operations Per Second,十亿次运算/秒)BP(Brach Prediction,分支预测)BPA(Bit Packing Architecture,位封包架构)BPI(Bit Per Inch,位/英寸)bps(bit per second,位/秒)bps(byte per second,字节/秒)BPU(Branch Processing Unit,分支处理单元)BRC(Beta Release Candidate,测试发布候选版0)BSD(Berkeley Software Distribution,伯克利软件分配代号)BSP(Binary Space Partitioning,二进制空间分区)BSP(Boot Strap Processor,启动捆绑处理器)BSRAM(Burst pipelined synchronous static RAM,突发式管道同步静态存储器)BTAC(Branch Target Address Calculator,分支目标寻址计算器)BTO(Build-To-Order,按序构建)BURN-Proof(Buffer UnderRuN-Proof,防止缓冲区溢出)C.O.P(CPU overheating protection,处理器过热保护)C2C(card-to-card interleaving,卡到卡交错存取CAD(computer-aided design,计算机辅助设计)CAM(Common Access Model,公共存取模型)CAM(Computer-aided manufacturing,计算机辅助制造)CAS(Column Address Strobe,列地址控制器)CAV(Constant Angular Velocity,恒定角速度)CBDS(Continuous Background Defect Scanning,连续后台错误扫描)CBF(Cable Broadband Forum,电缆宽带论坛)CBGA(Ceramic Ball Grid Array,陶瓷球状网阵排列)CBMC(Crossbar based memory controller,内存控制交叉装置)CBR(Committed Burst Rate,约定突发速率)CBR(Constant Bit Rate,固定比特率)CBU(color blending unit,色彩混和单位)CCD(Charge Coupled Device,电荷连接设备)CCIRN(Coordinating Committee for Intercontinental Research Networking,洲际研究网络协调委员会)CCM(Call Control Manager,拨号控制管理)cc-NUMA(cache-coherent non uniform memory access,连贯缓冲非统一内存寻址)CCS(Cross Capacitance Sensing,交叉电容感应)CCS(Cut Change System)CCT(Clock Cycle Time,时钟周期)CD(Compact Disc)cd/m^2(candela/平方米,亮度的单位)CDIP(Ceramic Dual-In-Line,陶瓷双重直线)CDPD(Cellular digital Packet data,细胞数字信息包数据)CDR(CD Recordable,可记录光盘)CDRAM(Cache DRAM,附加缓存型DRAM)CD-ROM/XA(CD-ROM eXtended Architecture,唯读光盘增强形架构)CDRS(Curved Directional Reflection Screen,曲线方向反射屏幕)CDRW(CD-Rewritable,可重复刻录光盘)CDSL(Consumer Digital Subscriber Line(消费者数字订阅线路)CE(Consumer Electronics,消费电子)CEA(Consumer Electronics Association,消费者电子协会)CEA(Critical Edge Angles,临界边角)CEM(cube environment mapping,立方环境映射)CEMA(Consumer Electronics Manufacturing Association(消费者电子制造业协会)Center Processing Unit Utilization,中央处理器占用率CEO(Chief Executive Officer,首席执行官)CF(CompactFlash Card,紧凑型闪存卡)CFM(cubic feet per minute,立方英尺/秒)CG(C for Graphics/GPU,用于图形/GPU的可编程语言)CG(Computer Graphics,计算机动画)CGI(Common Gateway Interface,通用网关接口)CG-Silicon(Continuous Grain Silicon,连续微粒硅)CHRP(Common Hardware Reference Platform,共用硬件平台)CHS(Cylinders、Heads、Sectors,柱面、磁头、扇区)CIEA(Commercial Internet Exchange Association,商业因特网交易协会)CIR(Committed Information Rate,约定信息速率)CIS(Contact Image Sensors,接触图像传感器)CISC(Complex Instruction Set Computing,复杂指令集计算机)CL(CAS Latency,CAS反应时间)Clipping(剪贴纹理)CLK(Clock Cycle,时钟周期)Clock Synthesizer,时钟合成器CLV(Constant Linear Velocity,恒定线速度)CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)CMOV(conditional move 包含uction,条件移动指令)CMP(on-chip multiprocessor,片内多重处理)CMR(Colossal Magneto Resistive,巨磁阻抗)CMS(Code Morphing Software,代码变形软件)CMSS(Creative Multi Speaker Surround,创新多音箱环绕)CMT(course-grained multithreading,过程消除多线程)CNPS(Computer Noise Prevention System,计算机噪音预防系统)CNR(Communication and Networking Riser,通讯和网络升级卡)CNT(carbon nano-tube,碳微管)COAST(Cache-on-a-stick,条状缓存)COB(Cache on board,板上集成缓存)co-CPU(cooperative CPU,协处理器)COD(Cache on Die,芯片内核集成缓存)COM(Component Object Model,组件对象模式)COMDEX(Computer Distribution Exposition,计算机代理分销业展览会)compressed textures(压缩纹理)Concurrent Command Engine,协作命令引擎COO(Chief Organizer Officer,首席管理官)Copper(铜)CP(command processor,指令处理器)CPA(Close Page Auto recharge,接近页自动预充电)CPE(Customer Premise Equipment,用户预定设备)CPGA(Ceramic Pin Grid Array,陶瓷针型栅格阵列)CPI(count per inch,每英寸计数)CPI(cycles per 包含uction,周期/指令)CPLD(Complex Programmable Logic Device,复杂可程序化逻辑组件)CPRM(Content Protection for record able media,记录媒体内容保护)CPS(Certification Practice Statement,使用证明书)CPU(Center Processing Unit,中央处理器)CRC(Cyclical Redundancy Check,循环冗余检查)CRM(Customer Relationship Management,顾客关系管理)CRT(Cathode Ray Tube,阴极射线管)CRT(Cooperative Redundant Threads,协同多余线程)CS(Channel Separation,声道分离)CSA(Canadian Standards Association,加拿大标准协会)CSA(Communication Streaming Architecture,通讯流架构)CSC(Colorspace Conversion,色彩空间转换)CSD(Circuit Switched Data,电路切换数据通话)CSE(Configuration Space Enable,可分配空间)CSG(constructive solid geometry,建设立体几何)CSP(Chip Scale Package,芯片比例封装)CSP(Chip Size Package,芯片尺寸封装)CSS(Cascading Style Sheets,层叠格式表)CSS(Common Command Set,通用指令集)CSS(Content Scrambling System,内容不规则加密)CTI(Computer Telephone Integration,计算机电话综合技术)CTO(Chief Technology Officer,首席技术官)CTR(CAS to RAS,列地址到行地址延迟时间)CTS(Carpal Tunnel Syndrome,计算机腕管综合症)CTS(Clear to Send,清除发送)CVS(Compute Visual Syndrome,计算机视觉综合症)CXT(Chooper eXTend,增强形K6-2内核)DA(Digital to Analog,数字到模拟转换)DAB(digital audio broadcast,数字音频广播)DAC(Digital to Analog Converter,数模传换器)DAC(Dual Address Cycle,双重地址周期)DAE(digital Audio Extraction,数据音频抓取)DAN(Dance,跳舞类游戏)DAO(Disc At Once,整盘刻录)DAO-RAW(Disc At Once Read after Write,整盘刻录-写后读)DASP(Dynamic Adaptive Speculative Pre-Processor,动态适应预测预处理器)Data Forwarding(数据前送)dB(decibel,分贝)DB(Deep Buffer,深度缓冲)DB(Device Bay,设备插架)DBBS(Dynamic Bass Boost System,动态低音增强系统)DBI(dynamic bus inversion,动态总线倒置)DBS(Direct Broadcast Satellite,直接卫星广播)DBS-PC(Direct Broadcast Satellite PC,人造卫星直接广播式PC)DC(Digital Camera,数码相机)DC(Dreamcast,世嘉64位游戏机)DCA(Defense Communication Agency,国防部通信局)DCC(Digital Compact Cassette,数字盒式磁带)DCC(Digital Content Creation,数字内容创造)DCD(Directional Corelational De-interlacing,方向关联解交错)DCD(Document Content De脚本ion for XML,XML文件内容描述)DCE(Data Circuit Terminal Equipment,数据通信设备)DCLK(Dot Clock,点时钟)DCOM(Distributing Component Object Model,构造物体模块)DCT(Display Compression Technology,显示压缩技术)DCT(DRAM Controller,DRAM控制器)DD(Double Side,双面内存)DDBGA(Die Dimension Ball Grid Array,内核密度球状矩阵排列)DDC(Display Data Channel,显示数据通道)DDC(Dynamic Depth Cueing,动态深度暗示)图像DDE(dynamic data exchange,动态数据交换)DDMA(Distributed DMA,分布式DMA)DDP(Digital Display Port,数字输出端口)DDR SDRAM(Double Date Rate,上下行双数据率SDRAM)DDR(Double Date Rate,上下行双数据率)DDS(Direct Draw Surface,直接绘画表面)DDSS II(Double Dynamic Suspension System II,第二代双层动力悬吊系统)DDSS(Dolby Digital Surround Sound,杜比数字环绕声)DDSS(Double Dynamic Suspension System,双悬浮动态减震系统)DDT(Dynamic Deferred Transaction,动态延期处理)DDWG(Digital Display Working Group,数字化显示工作组)DEC(Direct Etching Coatings,表面蚀刻涂层)Decal(印花法)Decode(指令解码)Deflection Coil(偏转线圈)DES(ata Encryption Standard,数据加密标准)DFL(Dynamic Focus Lens,动态聚焦)DFP(Digital Flat Panel,数字平面显示标准)DFPG(Digital Flat Panel Group,数字平面显示标准工作组)DFS(Digital Flex Scan,数字伸缩扫描)DFS(Dynamic Flat Shading,动态平面描影)DHCP(Dynamic Host Configuration Protocol,动态主机分配协议)DHHF(Dual Head - High Fidelity,高精度第四代双头)DHT(Dolby Headphone Technology,杜比耳机技术)DIB(Dual Independent Bus,双重独立总线)DIC(Digital Image Control,数字图像控制)DID(Device ID,设备ID)Digital Multiscan II(数字式智能多频追踪)DIL(dual-in-line)DIMM(Dual In-line Memory Modules,双重内嵌式内存模块)Directional Light(方向性光源)DiscWizard(磁盘控制软件)DIT(Disk Inspection Test,磁盘检查测试)Dithering(抖动)DIVA(Data IntensiVe Architecture,数据加强架构)DIY(Do it Yourself,自己装机)DLL(Delay-Locked Loop,延时锁定循环电路)dll(dynamic link library,动态链接库)DLP(digital Light Processing,数字光处理)DLS(Downloadable Sounds Level,可下载音色)DLS-2(Downloadable Sounds Level 2,第二代可下载音色)DM(Displacement mapping,位移贴图)DMA(Direct Memory Access,直接内存存取)DMAC(Direct Memory Access Controller,直接内存存取控制器)DME(Direct Memory Execute,直接内存执行)DMF(Distribution Media Format)DMI(Desktop Management Interface,桌面管理接口)DMT(Discreet Monitor Timing,智能型显示器调速)DMT(Discrete Multi - Tone,不连续多基频模式)DMT(Dynamic Multithreading Architecture,动态多线程结构)DNA(Distributed Internet Application,分布式因特网应用程序)DNS(Domain Name System,域名解析系统)DOA2 HC(Deal or Live 2 hardcore,生与死2完整版)DOC(Disk On Chip,芯片磁盘)DOCSIS(Data Over Cable Service Interface Specifications,线缆服务接口数据规格)DOF(Depth of Field,多重境深)DOJ(Department of Justice,反不正当竞争部门)DOM(Document Object Model,文档目标模型)DoS(Denial of Service,拒绝服务)DOS(Disk Operating System,磁盘操作系统)DOSD(Digital On Screen Display,同屏数字化显示)Dot Pitch(点距)dot texture blending(点型纹理混和)DOT(Dynamic Overcooking Technology,动态超频技术)DOT3(Dot product 3 bump mapping,点乘积凹凸映射)Double Buffering(双缓冲区)DP(Dual Processor,双处理器)DPBM(Dot Product Bump Mapping,点乘积凹凸映射)DPC(Desktop PC,桌面PC)dpi(dot per inch,每英寸的打印像素)DPMS(Display Power Management Signaling,显示能源管理信号)DPP(Direct print Protocol,直接打印协议DQL(Dynamic Quadra pole Lens,动态四极镜)DQS(Bidirectional data strobe,双向数据滤波)DQUICK(DVD Qualification and Integration Kit,DVD资格和综合工具包)DRA(deferred rendering architecture,延迟渲染架构)DRAM(Dynamic Random Access Memory,动态随机存储器)DRCG(Direct Rambus Clock Generator,直接Rambus时钟发生器)DRDRAM(Direct RAMBUS DRAM,直接内存总线DRAM)DRF(Digital radio frequency,数字无线电频率)DRI(Direct Rendering Infrastructure,基层直接渲染)DRM(Digital rights management,数字版权保护)DRM(Digital Rights Management,数字适当管理)DRSL(Differential Rambus Signaling Level,微分RAMBUS信号级)DRSL(Direct Rambus Signaling Level,直接RAMBUS信号级)DS3D(DirectSound 3D Streams)DSD(Direct Stream Digital,直接数字信号流)DSL(Data Strobe Link,数据选通连接DSL(Down Loadable Sample,可下载的取样音色)DSM(Dedicated Stack Manager,专门堆栈管理)DSM(Distributed shared memory,分布式共享内存)DSMT(Dynamic Simultaneous Multithreading,动态同步多线程)DSO(Dynamic Sound-stage Organizer,动态声音层组建)DSP(Delivery Service Partner,交付服务合伙人)DSP(Digital Signal Processing,数字信号处理)DSP(Digital Sound Field Processing,数字音场处理)DSP(Dual Streams Processor,双重流处理器)DST(Depleted Substrate Transistor,衰竭型底层晶体管)DST(Drive Self Test,磁盘自检程序)DSTN(Double layers Super Twisted Nematic,双层超扭曲向列,无源矩阵LCD)DSVD(Digital Simultaneous Voice and Data)DTD(Document Type Definition,文件类型定义)DTE(Data Terminal Equipment,数据终端设备)DTL(Developer Tool,发展工具包)DTR(Disk Transfer Rate,磁盘传输率)DTS(Digital Theater System,数字剧院系统)DTT(DeskTop Theater,桌面剧院)DTV(Digital TV,数字电视)DTV(Dual Threshold Voltage,双重极限电压)DTXS(Decryption Transform for XML Signature,XML签名解密转换)DUN(Dial-Up Networking,拨号网络)DUV(Deep Ultra-Violet,纵深紫外光)DV(Digital Vidicon,数码摄录机)DVB(Digital Video Broadcasting,数字视频广播DVC(Digital Vibrance Control,数字振动控制)DVD(Digital Video/Versatile Disk,数字视频/万能光盘)DVD-R(DVD Recordable,可记录DVD盘)DVD-RAM(Digital Video/Versatile Disk - Random Access Memory,随机存储数字视频/万能光盘)DVD-RW(DVD Rewritable,可重复刻录DVD盘)DVFM(Dynamic Voltage and Frequency Management,动态电压和频率管理)DVI(Digital Video Interface,数字视频接口)DVI(Digital Visual Interface,数字化视像接口)DVMT(Dynamic Video Memory Technology,动态视频内存技术)DVMT(Dynamic Video Memory Technology,动态视频内存技术)DWDM(Dense WaveLength Division Multiplex,波长密集型复用技术)DxR(DynamicXTended Resolution,动态可扩展分辨率)DXTC(Direct X Texture Compress,DirectX纹理压缩)Dynamic Z-buffering(动态Z轴缓冲区)E(Economy,经济,或Entry-level,入门级)E3(Electronic Entertainment Expo,电子娱乐展览会)EAP(Extensible Authentication Protocol,扩展证明协议)EAX(Environmental Audio Extensions,环境音效扩展技术)EB(Expansion Bus,扩展总线)EBGA(Enhanced Ball Grid Array,增强形球状网阵排列)EBL(electron beam lithography,电子束平版印刷)EBR(Excess Burst Rate,超额突发速率)EC(Early Childhood,学龄前儿童)EC(Embedded Controller,嵌入式控制器)ECC(Elliptic Curve Crypto,椭圆曲线加密)ECC(Error Checking and Correction,错误检查修正)ECD(Electro Chromic Display,电铬显示器)ECP(Extended Capabilities Port,延长能力端口)ED(Execution driven,执行驱动)EDA(Electronic Design Automatic,电子设计自动化)E-DDC(Enhanced Display Data Channel,增强形视频数据通道协议)EDEC(Early Decode,早期解码)Edge Anti-aliasing(边缘抗锯齿失真)EDO(Enhanced Data-Out RAM,数据增强输出内存)EE(Emotion Engine,情感引擎)E-EDID(Enhanced Extended Identification Data,增强形扩充身份辨识数据)EEPROM(Electrically Erasable Programmable ROM,电擦写可编程只读存储器)eFB(embedded Frame Buffer,嵌入式帧缓冲)EFEAL(Extended Field Elliptical Aperture Lens,可扩展扫描椭圆孔镜头)EFF(Electronic Frontier Foundation(电子前线基金会)EFI(Extensible Firmware Interface,扩展固件接口)EFM(Eight to Fourteen Modulation,8位信号转换为14位信号)EFU(Elemntary Functional Unit,增强功能单元)EHCI(Enhanced Host Controller Interface,加强型主机端控制接口)EHSDRAM(Enhanced High Speed DRAM,增强型超高速内存)EIDE(enhanced Integrated Drive Electronics,增强形电子集成驱动器)EISA(Enhanced Industry Standard Architecture,增强形工业标准架构)EL DDR(Enhanced Latency DDR,增强反应周期DDR内存)Embedded Chips(嵌入式)EMBM(environment mapped bump mapping,环境凹凸映射)Embosing(浮雕)EMC(Electron Magnetic Compatibility,电磁兼容)EMF(Electron Magnetic Field,电磁场)EMI(Electromagnetic Interference,电磁干扰)EMP(Emergency Management Port,紧急事件管理端口)EMS(Enhanced Memory System,增强内存系统)EMS(Enhanced Message Service,扩展型信息服务)EMS(Expanded Memory Specification,扩充内存规格)EOL(End of Life,最终完成产品)EOS(eBookMan Operating System,电子书操作系统)EPA(edge pin array,边缘针脚阵列)EPA(Environmental Protection Agency,美国环境保护局)EPF(Embedded Processor Forum,嵌入式处理器论坛)EPIC(explicitly parallel 包含uction code,并行指令代码)EPL(electron projection lithography,电子发射平版印刷)EPM(Enhanced Power Management,增强形能源管理)EPM(enterprise project manage)EPOC(Electronic Piece of Cheese,小型电子块)EPOC(Elevated Package Over CSP,CSP架空封装)EPP(Enhanced Parallel Port,增强形平行接口)EPROM(erasable,programmable ROM,可擦写可编程ROM)EPV(Extended Voltage Protection,扩展电压保护)ERD(Emergency Repair Disk,应急修理磁盘)ERP(Enterprise Requirement Planning,企业需求计划)ERP(Enterprise Resource Planning,企业资源计划)ERP(estimated retail price,估计零售价)ES(Energy Star,能源之星)ES(Engineering Sample,工程样品)eSATA(External Serial ATA,扩展型串行ATA)ESCD(Extended System Configuration Data,可扩展系统配置数据)ESD(electro-static discharge,静电释放)ESDJ(Easy Setting Dual Jumper,简化CPU双重跳线法)ESDRAM(Enhanced SDRAM,增强型SDRAM)ESER(EAC Secure Extract Ripping,EAC安全抓取复制)ESP(Electronic-Shock Protection,电子抗震系统)ESP(Embedded System Platform,嵌入式系统平台)ESP(Encapsulating Security Payload,压缩安全有效载荷)ESR(Equivalent Series Resistance,等价系列电阻)ESRAM(Enhanced SRAM,增强型SRAM)ETC(etc,其它类游戏,包括模拟飞行)eTM(embedded Texture Buffer,嵌入式纹理缓冲)ETRI(Electronics and Telecommunications Research Institute,电子和电信研究协会)EULA(End-User License Agreement,最终用户释放协议)EUV(Extreme Ultra Violet,紫外光)EUV(extreme ultraviolet lithography,极端紫外平版印刷)EVF(Electronic Viewfinder,电子取景窗)E-WDM(Enhanced Windows Driver Model,增强型视窗驱动程序模块)Execute Buffers(执行缓冲区)Extended Burst Transactions(增强式突发处理)Extended Stereo(扩展式立体声)Factor Alpha Blending(因子阿尔法混合)FADD(Floationg Point Addition,浮点加)FAQ(Frequently Asked Questions,常见问题回答)Fast Z-clear(快速Z缓冲清除)FAT(File Al本地 Tables,文件分配表)FB(fragment buffer,片段缓冲)FBC(Frame Buffer Cache,帧缓冲缓存)FBGA(Fine-Pitch Ball Grid Array,精细倾斜球状网阵排列)FBGA(flipchip BGA,轻型芯片BGA)F-Buffer(Fragment Stream FIFO Buffer,片段流先入先出缓冲区)FC(Famicom,任天堂8位游戏机)FC(Fibre Channel,光纤通道)FC-BGA(Flip-Chip Ball Grid Array,反转芯片球形栅格阵列)FCC(Federal Communications Commission,联邦通信委员会)FC-PGA(Flip-Chip Pin Grid Array,反转芯片针脚栅格阵列)FCRAM(Fast Cycle RAM,快周期随机存储器)FDB(Fluid Dynamic Bearing,非固定动态轴承)FDB(fluid-dynamic bearings,动态轴承)FDBM(Fluid dynamic bearing motors,液态轴承马达)FDC(Floppy Disk Controller,软盘驱动器控制装置)FDD(Floppy Disk Driver,软盘驱动器)FDIV(Floationg Point Divide,浮点除)FDM(Frequency Division Multi,频率分离)FED(Field Emission Displays,电场显示器)FEMMA(Foldable Electronic Memory Module Assembly,折叠电子内存模块装配)FEMMS(Fast Entry/Exit Multimedia State,快速进入/退出多媒体状态FFB(Force Feed Back,力反馈)FFJ(Force Feedback Joystick,力量反馈式操纵杆)FFT(fast Fourier transform,快速热欧姆转换)FGM(Fine-Grained Multithreading,高级多线程)FID(FID(Frequency identify,频率鉴别号码)FIFO(First Input First Output,先入先出队列)FIR(finite impulse response,有限推进响应)FireWire(火线,即IEEE1394标准)FISC(Fast Instruction Set Computer,快速指令集计算机)FL(fragment list,片段列表)FL(Function Lookup,功能查找)Flat(平面描影)FlexATX(Flexibility ATX,可扩展性ATX)flip double buffered(反转双缓存)flip-chip(芯片反转)FLIR(Forward Looking Infra-Red,前视红外)FLOPs(Floating Point Operations Per Second,浮点操作/秒)Flow-control(流控制)FLS(Front Light Screen,前发光屏幕)Flyback Transformer(回转变压器)FM(Flash Memory,快闪存储器)FM(Frequency Modulation,频率调制)FMA(full-motion animated backdrops)FMAC(Floating-Point Multiply-Accumulators,浮点累积乘单元)FMC(Frictionless Memory Control,无阻内存控制)FMD ROM(Fluorescent Material Read Only Memory,荧光质只读存储器)FMT(fine-grained multithreading,纯消除多线程)FMUL(Floationg Point Multiplication,浮点乘)Fog table quality(雾化表画质)Fog(雾化效果)FPD(flat panel display,平面显示器)FPM(Fast Page Mode,快页模式内存)FPRs(floating-point registers,浮点寄存器)FPS(First Person Shooters,第一人称射击游戏)FPS(FourPointSurround,创新的四点环绕扬声器系统)fps(frames per second,帧/秒)FPU(Float Point Unit,浮点运算单元)FR(Frames Rate,游戏运行帧数)FR(Frequence Response,频率响应)Frames rate is King(帧数为王)FRC(Frame Rate Control(帧比率控制)FRC(Frame Rate Control,帧率控制)FRICC(Federal Research Internet Coordinating Committee,联邦调查因特网协调委员会)FRJS(Fully Random Jittered Super-Sampling,完全随机移动式超级采样)Front Buffer(前置缓冲)FSAA(Full Scene/Screen Anti-aliasing,全景/屏幕抗锯齿)FSB(Front Side Bus,前端总线)FSE(Frequency Shifter Effect,频率转换效果)FSR(force sensor resistance,动力感应电阻)FSTN(Film compensated Super Twisted liquid crystal,带补偿膜超扭曲相列)FSUB(Floationg Point Subtraction,浮点减)FTC(Federal Trade Commission,联邦商业委员会)FTG(Fighting Game,格斗类游戏)FTP(File Transfer Protocol,文件传输协议)Fur(软毛效果)FW(Fast Write,快写,AGP总线的特殊功能)FWH(Firmware Hub,固件中心)GART(Graphic Address Remappng Table,图形地址重绘表)GB(Game Boy,任天堂4位手提游戏机)GB(Garibaldi架构,Garibaldi基于ATX架构,但是也能够使用WTX构架的机箱)GBA(Game Boy Advanced,任天堂增强型手提游戏机)GBC(Game Boy Color,任天堂手提16色游戏机)GBL(GameBoy Light,GB夜光型)GBP(GameBoy Pocket,GB口袋型)GDC(Game Developer Conference,游戏发展商会议)GDI(Graphics Device Interface,图形设备接口)GFD(Gold finger Device,金手指超频设备)GG(Game Gear,世嘉彩色手提游戏机)GHC(Global History Counter,通用历史计数器)Ghost((General Hardware Oriented System Transfer,全面硬件导向系统转移)GI(Global Illumination,球形光照)GIC(Gold Immersion Coating,化金涂布技术)GIF(Graphics Interchange Format,图像交换格式)GIF(Graphics Interface unit,图形接口单元)GLV(grating-light-valve,光栅亮度阀)GM(General Midi,普通MIDI)GM(Glass Mould,玻璃铸制)GMCH(Graphics & Memory Controller Hub,图形和内存控制中心)GMR(giant magnetoresistive,巨型磁阻)Gouraud Shading,高洛德描影,也称为内插法均匀涂色GPA(Graphics Performance Accelerator,图形性能加速卡)GPF(General protect fault,一般保护性错误)GPIs(General Purpose Inputs,普通操作输入)GPL(GNU Public License,GNU公众授权)GPRS(General Packet Raice,整合封包无线服务)GPRs(General Purpose Registers,通用寄存器)GPS(Global Positioning System,全球定位系统)GPT(Graphics Performance Toolkit,图形性能工具包)GPU(Graphics Processing Unit,图形处理器)GS(Graphic Synthesizer,图形合成器)GS(Graphics Synthesizer,图形合成器)GSM(Galvanization Superconductive Material,电镀锌超导材料)GTF(General Timing Formula,普通调速方程式)GTL(Gunning Transceiver Logic,发射接收逻辑电路)GTS(Giga Textel Sharder,十亿像素填充率)Guard Band Support(支持保护带)GUI(Graphics User Interface,图形用户界面)GVPP(Generic Visual Perception Processor,常规视觉处理器)GWS(graphics workstations,图形工作站)HAL(Hardware Abstraction Layer,硬件抽像化层)HCF(Host Controller,主体控制处理)HCI(Host Controller Interface,主机控制接口HCL(Hardware Compatibility List,硬件兼容性列表)HCRP(Hardcopy Cable Replacement Profile,硬复制电缆复位协议子集)HCT(Hardware Compatibility Test,硬件兼容性测试HDA(Head Disk Assembly,头盘组件)HDA(high-efficiency Audax High Definition Aerogel,高效高清楚气动)HDIT(High Bandwidth Differential Interconnect Technology,高带宽微分互连技术)HDMI(High Definition Multimedia Interface,高精度多媒体接口)HDR(High Dynamic Range,高级动态范围)HDRL(high dynamic-range lighting,高动态范围光线)HDSL(High bit rate DSL,高比特率数字订阅线路)HDSS(Holographic Data Storage System,全息数据存储系统)HDTV(high definition television,高清晰度电视)HDVP(High-Definition Video Processor,高精度视频处理器)HE(Home Edition,家庭版)HEL(Hardware Emulation Layer(硬件模拟层)HID(Human Interface Device,人机对话接口设备)Hierarchical Z(Z分级)HiFD(high-capacity floppy disk,高容量软盘)Hi-fi(high fidelity,高精度设备)high triangle count(复杂三角形计数)HLL(high level language,高级语言)HLLCA(High-Level Language Computing Architecture,高级语言计算架构)HL-PBGA(表面黏著,高耐热、轻薄型塑胶球状网阵封装HLSL(High Level Shading Language,高级描影语言)HMC(hardware motion compensation,硬件运动补偿)HMC(holographic media card,全息媒体卡)HMD(holographic media disk,全息媒体磁盘)Home PNA(Home Private Network Adapter,家庭私人网络适配器)HOS(Higher-Order Surfaces,高次序表面)HPC(Hand held PC,手持电脑设备)HPDR(High-Precision Dynamic-Range,高精度动态范围)HPF(High-Pass Filter,高通滤波器)HPNA(home phoneline networking,家庭电话线网络)HPS(High Performance Server,高性能服务器)HPTC(high performance technical computing,高性能技术运算)HPW(High Performance Workstation,高性能工作站)HRAA(High Resolution Anti-aliasing,高分辨率抗锯齿)HRTF(Head Related Transfer Function,头部关联传输功能)HSCSD(High-Speed Circuit-Switched Data,高速巡回开关数据)HSDRAM(High Speed DRAM,超高速内存)HSF(Host Signal,主体信号处理)HSI(High Speed Interconnect,高速内连)HSLB(High Speed Link Bus,高速链路总线)HSP(Host Signal Processing,主体信号处理)HSR(Hidden Surface Removal,隐藏表面移除)HT(Hyper Transport,超级传输)HTA(Hypertext Application,超文本应用程序)。
3CPU-6典型CPU简介

二、 Intel 80X86微处理器举例
1 . 8086微处理器
Intel公司1978年研制成功 时钟频率:4.7MHz-10MHz 2.9万个晶体管、91种指令 由EU执行单元和BIU总线接口单元组成 20位地址总线,寻址能力 220 = 1048576 = 1( MB ) 16位数据总线 4个16位通用寄存器:AX,BX,CX,DX, 5个16位地址指针寄存器:IP,BP,SP,SI,DI 4个16位段界寄存器:CS,DS,SS,ES
4) 8086、8088微处理器的工作方式与引脚号
10
2.
80286微处理器
Intel公司1982年推出 13.4万个晶体管,时钟频率6MHz~20MHz 向下兼容8086,具有8086的基本结构,但增强了 存储管理和保护虚地址结构,可支持多用户系统 具有8086的全部指令,并新增加25种指令 16位数据线,24根地址线,寻址能力达到16MB 有实地址和16MB保护虚地址两种工作模式,通过 指 令实现转换。实地址模式下完全兼容 8086 CPU 并能 运行8086软件,兼容目标代码;保护虚地址模 式下, 可管理内存达16MB,并且对使用者来说存储 器的分 配方式与寻址方式没有改变。
ห้องสมุดไป่ตู้
Pentium的超标量流水线 0 1 2 3 4 5 6 7 8 时间 i1 U PF D1 D2 EX WB i2 V PF D1 D2 EX WB i3 U i4 V i5 U i6 V PF D1 D2 EX WB
PF D1 D2 EX WB PF D1 D2 EX WB
PF D1 D2 EX WB PF D1 D2 EX WB PF D1 D2 EX WB
2012计算机系统结构核心概念

5. RISC:精简指令集计算机
6. Multicore microprocessor(多处理器核)处理器核和其他应用相关的硬件整合,构建一个单一的芯片。
7. Operating system(操作系统):计算机资源管理程序。为运行在该计算机上的应用程序服务。
39. Spatial locality:时间局部性,如果某个数据项被引用,那么可能很快再次被引用。
40. Temporal locality:空间局部性,如果某个数据项被引用,那么与它地址相近的数据项可能很快会被引用。
41. hit rate:命中率,在高速缓存中找到目标数据的存储访问的比例。
35. VIEW:
36. Superscalar:超标量,一种高级流水线技术,可以使每个周期处理器能执行的指令数多于一条。
37. out-of-order execution:乱序执行,在基于流水线的执行过程中,一条由于某种原因阻塞的指令不会造成后面的指令等待的过程。
第五章
38. Memory hierarchy:存储器层次结构,一种使用多层存储器的结构(存储器离CPU越远,容量越大而访问时间就越长)。
42. miss rate:缺失率,层次结构存储器中不在某层出现的存储访问比例。
43. hit time:命中时间,访问存储器某层所需要时间,包括判断访问是否命中所需要的时间。
44. miss penalty:缺失损失,从底层将块取入该层所需要的时间,包括访问块,向上逐层传输块直至将数据块放入发生缺失的那一层所需要的时间。
58. Compulsory miss:强制缺失,也称冷启动缺失,对从没在高速缓存中出现过的块第一次进行访问引起的缺失。
动态调度(Cont),推断执行和ILP

Local predictor :两级预测器
• Top level :1024个10-bit 项构成,每个10-bit项对应最近10次分支 的转移方向 • Next level :由Top level所选项中的10-bit索引找到1K 项中的对应 项,每项由3-bit saturating counter 作为局部预测器
计算机体系结构 Chapter4_3.4
进行循环重叠执行需要尽快解决分支问题!
在循环展开的例子中,我们假设整数部件可以快速解决分 支问题,以便进行循环重叠执行! Loop: LD MULTD SD SUBI BNEZ F0 F4 F4 R1 R1 0 F0 0 R1 Loop R1 F2 R1 #8
计算机体系结构
Chapter4_3.14
Correlating Branch Predicator
例如: if (aa==2) aa=0; if (bb==2) bb=0; if (aa!=bb) { 翻译为DLX SUBI R3,R1,#2 BNEZ R3,L1 ADDI R1,R0,R0 L1: SUBI R3,R2,#2 BNEZ R3,L2 ADDI R2,R0,R0 L2: SUBI R3,R1,R2 BEQZ R3,L3
2-bit recent global branch history (01 = not taken then taken)
计算机体系结构 Chapter4_3.21
计算机体系结构
Chapter4_3.22
Tournament Predictors
Tournament predictors:
动态调度 (Cont), 推断执行 和ILP
计算机体系结构 Chapter4_3.1
常用计算机词汇英文缩写

常用计算机词汇缩写1、CPU3DNow!(3D no waiting)ALU(Arithmetic Logic Unit,算术逻辑单元)AGU(Address Generation Units,地址产成单元)BGA(Ball Grid Array,球状矩阵排列)BHT(branch prediction table,分支预测表)BPU(Branch Processing Unit,分支处理单元)Brach Pediction(分支预测)CMOS: (Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)CISC(Complex Instruction Set Computing,复杂指令集计算机)CLK(Clock Cycle,时钟周期)COB(Cache on board,板上集成缓存)COD(Cache on Die,芯片内集成缓存)CPGA(Ceramic Pin Grid Array,陶瓷针型栅格阵列)CPU(Center Processing Unit,中央处理器)Data Forwarding(数据前送)Decode(指令解码)DIB(Dual Independent Bus,双独立总线)EC(Embedded Controller,嵌入式控制器)Embedded Chips(嵌入式)EPIC(explicitly parallel instruction code,并行指令代码)FADD(Floationg Point Addition,浮点加)FCPGA(Flip Chip Pin Grid Array,反转芯片针脚栅格阵列)FDIV(Floationg Point Divide,浮点除)FEMMS:(Fast Entry/Exit Multimedia State,快速进入/退出多媒体状态)FFT(fast Fourier transform,快速热欧姆转换)FID(FID:Frequency identify,频率鉴别号码)FIFO(First Input First Output,先入先出队列)flip-chip(芯片反转)FLOP(Floating Point Operations Per Second,浮点操作/秒)FMUL(Floationg Point Multiplication,浮点乘)FPU(Float Point Unit,浮点运算单元)FSUB(Floationg Point Subtraction,浮点减)GVPP(Generic Visual Perception Processor,常规视觉处理器)HL-PBGA: 表面黏著,高耐热、轻薄型塑胶球状矩阵封装IA(Intel Architecture,英特尔架构)ICU(Instruction Control Unit,指令控制单元)ID:(identify,鉴别号码)IDF(Intel Developer Forum,英特尔开发者论坛)IEU(Integer Execution Units,整数执行单元)IMM:( Intel Mobile Module, 英特尔移动模块)Instructions Cache,指令缓存Instruction Coloring(指令分类)IPC(Instructions Per Clock Cycle,指令/时钟周期)ISA(instruction set architecture,指令集架构)KNI(Katmai New Instructions,Katmai新指令集,即SSE)Latency(潜伏期)LDT(Lightning Data Transport,闪电数据传输总线)Local Interconnect(局域互连)MESI(Modified, Exclusive, Shared, Invalid:修改、排除、共享、废弃)MMX(MultiMedia Extensions,多媒体扩展指令集)MMU(Multimedia Unit,多媒体单元)MFLOPS(Million Floationg Point/Second,每秒百万个浮点操作)MHz(Million Hertz,兆赫兹)MP(Multi-Processing,多重处理器架构)MPS(MultiProcessor Specification,多重处理器规范)MSRs(Model-Specific Registers,特别模块寄存器)NAOC(no-account OverClock,无效超频)NI:(Non-Intel,非英特尔)OLGA(Organic Land Grid Array,基板栅格阵列)OoO(Out of order,乱序执行)PGA: Pin-Grid Array(引脚网格阵列),耗电大Post-RISCPR(Performance Rate,性能比率)PSN(Processor Serial numbers,处理器序列号)PIB(Processor In a Box,盒装处理器)PPGA(Plastic Pin Grid Array,塑胶针状矩阵封装)PQFP(Plastic Quad Flat Package,塑料方块平面封装)RAW(Read after Write,写后读)Register Contention(抢占寄存器)Register Pressure(寄存器不足)Register Renaming(寄存器重命名)Remark(芯片频率重标识)Resource contention(资源冲突)Retirement(指令引退)RISC(Reduced Instruction Set Computing,精简指令集计算机)SEC:( Single Edge Connector,单边连接器)Shallow-trench isolation(浅槽隔离)SIMD(Single Instruction Multiple Data,单指令多数据流)SiO2F(Fluorided Silicon Oxide,二氧氟化硅)SMI(System Management Interrupt,系统管理中断)SMM(System Management Mode,系统管理模式)SMP(Symmetric Multi-Processing,对称式多重处理架构)SOI: (Silicon-on-insulator,绝缘体硅片)SONC(System on a chip,系统集成芯片)SPEC(System Performance Evaluation Corporation,系统性能评估测试)SQRT(Square Root Calculations,平方根计算)SSE(Streaming SIMD Extensions,单一指令多数据流扩展)Superscalar(超标量体系结构)TCP: Tape Carrier Package(薄膜封装),发热小Throughput(吞吐量)TLB(Translate Look side Buffers,翻译旁视缓冲器)USWC(Uncacheabled Speculative Write Combination,无缓冲随机联合写操作)VALU(Vector Arithmetic Logic Unit,向量算术逻辑单元)VLIW(Very Long Instruction Word,超长指令字)VPU(Vector Permutate Unit,向量排列单元)VPU(vector processing units,向量处理单元,即处理MMX、SSE等SIMD指令的地方)2、主板ADIMM(advanced Dual In-line Memory Modules,高级双重内嵌式内存模块)AMR(Audio/Modem Riser;音效/调制解调器主机板附加直立插卡)AHA(Accelerated Hub Architecture,加速中心架构)ASK IR(Amplitude Shift Keyed Infra-Red,长波形可移动输入红外线)ATX: AT Extend(扩展型AT)BIOS(Basic Input/Output System,基本输入/输出系统)CSE(Configuration Space Enable,可分配空间)DB:(Device Bay,设备插架)DMI(Desktop Management Interface,桌面管理接口)EB(Expansion Bus,扩展总线)EISA(Enhanced Industry Standard Architecture,增强形工业标准架构)EMI(Electromagnetic Interference,电磁干扰)ESCD(Extended System Configuration Data,可扩展系统配置数据)FBC(Frame Buffer Cache,帧缓冲缓存)FireWire(火线,即IEEE1394标准)FSB: (Front Side Bus,前置总线,即外部总线)FWH( Firmware Hub,固件中心)GMCH(Graphics & Memory Controller Hub,图形和内存控制中心)GPIs(General Purpose Inputs,普通操作输入)ICH(Input/Output Controller Hub,输入/输出控制中心)IR(infrared ray,红外线)IrDA(infrared ray,红外线通信接口可进行局域网存取和文件共享)ISA:(Industry Standard Architecture,工业标准架构)ISA(instruction set architecture,工业设置架构)MDC(Mobile Daughter Card,移动式子卡)MRH-R(Memory Repeater Hub,内存数据处理中心)MRH-S(SDRAM Repeater Hub,SDRAM数据处理中心)MTH(Memory Transfer Hub,内存转换中心)NGIO(Next Generation Input/Output,新一代输入/输出标准)P64H(64-bit PCI Controller Hub,64位PCI控制中心)PCB(printed circuit board,印刷电路板)PCBA(Printed Circuit Board Assembly,印刷电路板装配)PCI:(Peripheral Component Interconnect,互连外围设备)PCI SIG(Peripheral Component Interconnect Special Interest Group,互连外围设备专业组)POST(Power On Self Test,加电自测试)RNG(Random number Generator,随机数字发生器)RTC: (Real Time Clock 实时时钟)KBC(KeyBroad Control,键盘控制器)SAP(Sideband Address Port,边带寻址端口)SBA(Side Band Addressing,边带寻址)SMA: (Share Memory Architecture,共享内存结构)STD(Suspend To Disk,磁盘唤醒)STR(Suspend To RAM,内存唤醒)SVR: (Switching Voltage Regulator 交换式电压调节)USB(Universal Serial Bus,通用串行总线)USDM(Unified System Diagnostic Manager,统一系统监测管理器)VID(Voltage Identification Definition,电压识别认证)VRM (Voltage Regulator Module,电压调整模块)ZIF: (Zero Insertion Force, 零插力)主板技术GigabyteACOPS:(Automatic CPU OverHeat Prevention SystemCPU 过热预防系统)SIV: (System Information Viewer系统信息观察)磐英ESDJ(Easy Setting Dual Jumper,简化CPU双重跳线法)浩鑫UPT(USB、PANEL、LINK、TV-OUT四重接口)芯片组ACPI(Advanced Configuration and Power Interface,先进设置和电源管理)AGP(Accelerated Graphics Port,图形加速接口)I/O(Input/Output,输入/输出)MIOC: (Memory and I/O Bridge Controller,内存和I/O桥控制器)NBC: (North Bridge Chip北桥芯片)PIIX: (PCI ISA/IDE Accelerator加速器)PSE36: (Page Size Extension 36-bit,36位页面尺寸扩展模式)PXB:(PCI Expander Bridge,PCI增强桥)RCG: (RAS/CAS Generator,RAS/CAS发生器)SBC: (South Bridge Chip南桥芯片)SMB: (System Management Bus全系统管理总线)SPD(Serial Presence Detect,内存内部序号检测装置)SSB: (Super South Bridge,超级南桥芯片)TDP:(Triton Data Path数据路径)TSC: (Triton System Controller系统控制器)QPA: (Quad Port Acceleration四接口加速)3、显示设备ASIC: (Application Specific Integrated Circuit特殊应用积体电路)ASC(Auto-Sizing and Centering,自动调效屏幕尺寸和中心位置)ASC(Anti Static Coatings,防静电涂层)AGAS(Anti Glare Anti Static Coatings,防强光、防静电涂层)BLA: (Bearn Landing Area电子束落区)BMC(Black Matrix Screen,超黑矩阵屏幕)CRC: (Cyclical Redundancy Check循环冗余检查)CRT(Cathode Ray Tube,阴极射线管)DDC:(Display Data Channel,显示数据通道)DEC(Direct Etching Coatings,表面蚀刻涂层)DFL(Dynamic Focus Lens,动态聚焦)DFS(Digital Flex Scan,数字伸缩扫描)DIC: (Digital Image Control数字图像控制)Digital Multiscan II(数字式智能多频追踪)DLP(digital Light Processing,数字光处理)DOSD:(Digital On Screen Display同屏数字化显示)DPMS(Display Power Management Signalling,显示能源管理信号)Dot Pitch(点距)DQL(Dynamic Quadrapole Lens,动态四极镜)DSP(Digital Signal Processing,数字信号处理)EFEAL(Extended Field Elliptical Aperture Lens,可扩展扫描椭圆孔镜头)FRC:(Frame Rate Control帧比率控制)HVD(High Voltage Differential,高分差动)LCD(liquid crystal display,液晶显示屏)LCOS: (Liquid Crystal On Silicon硅上液晶)LED(light emitting diode,光学二级管)L-SAGIC(Low Power-Small Aperture G1 wiht Impregnated Cathode,低电压光圈阴极管)LVD(Low Voltage Differential,低分差动)LVDS:(Low Voltage Differential Signal低电压差动信号)MALS(Multi Astigmatism Lens System,多重散光聚焦系统)MDA(Monochrome Adapter,单色设备)MS: (Magnetic Sensors磁场感应器)Porous Tungsten(活性钨)RSDS: (Reduced Swing Differential Signal小幅度摆动差动信号)SC(Screen Coatings,屏幕涂层)Single Ended(单终结)Shadow Mask(阴罩式)TDT(Timeing Detection T able,数据测定表)TICRG: (Tungsten Impregnated Cathode Ray Gun钨传输阴级射线枪)TFT(thin film transistor,薄膜晶体管)UCC(Ultra Clear Coatings,超清晰涂层)VAGP:( Variable Aperature Grille Pitch可变间距光栅)VBI:( Vertical Blanking Interval垂直空白间隙)VDT(Video Display Terminals,视频显示终端)VRR: (Vertical Refresh Rate垂直扫描频率)4、视频3D:(Three Dimensional,三维)3DS(3D SubSystem,三维子系统)AE(Atmospheric Effects,雾化效果)AFR(Alternate Frame Rendering,交替渲染技术)Anisotropic Filtering(各向异性过滤)APPE(Advanced Packet Parsing Engine,增强形帧解析引擎)AV(Analog Video,模拟视频)Back Buffer,后置缓冲Backface culling(隐面消除)Battle for Eyeballs(眼球大战,各3D图形芯片公司为了争夺用户而作的竞争)Bilinear Filtering(双线性过滤)CEM(cube environment mapping,立方环境映射)CG(Computer Graphics,计算机生成图像)Clipping(剪贴纹理)Clock Synthesizer,时钟合成器compressed textures(压缩纹理)Concurrent Command Engine,协作命令引擎Center Processing Unit Utilization,中央处理器占用率DAC(Digital to Analog Converter,数模传换器)Decal(印花法,用于生成一些半透明效果,如:鲜血飞溅的场面)DFP(Digital Flat Panel,数字式平面显示器)DFS:( Dynamic Flat Shading动态平面描影,可用作加速Dithering抖动)Directional Light,方向性光源DME:( Direct Memory Execute直接内存执行)DOF(Depth of Field,多重境深)dot texture blending(点型纹理混和)Double Buffering(双缓冲区)DIR(Direct Rendering Infrastructure,基层直接渲染)DVI(Digital Video Interface,数字视频接口)DxR:( DynamicXTended Resolution动态可扩展分辨率)DXTC(Direct X Texture Compress,DirectX纹理压缩,以S3TC为基础)Dynamic Z-buffering(动态Z轴缓冲区),显示物体远近,可用作远景E-DDC(Enhanced Display Data Channel,增强形视频数据通道协议,定义了显示输出与主系统之间的通讯通道,能提高显示输出的画面质量)Edge Anti-aliasing,边缘抗锯齿失真E-EDID(Enhanced Extended Identification Data,增强形扩充身份辨识数据,定义了电脑通讯视频主系统的数据格式)Execute Buffers,执行缓冲区environment mapped bump mapping(环境凹凸映射)Extended Burst Transactions,增强式突发处理Front Buffer,前置缓冲Flat(平面描影)Frames rate is King(帧数为王)FSAA(Full Scene Anti-aliasing,全景抗锯齿)Fog(雾化效果)flip double buffered(反转双缓存)fog table quality(雾化表画质)GART(Graphic Address Remappng Table,图形地址重绘表)Gouraud Shading,高洛德描影,也称为内插法均匀涂色GPU(Graphics Processing Unit,图形处理器)GTF(Generalized Timing Formula,一般程序时间,定义了产生画面所需要的时间,包括了诸如画面刷新率等)HAL(Hardware Abstraction Layer,硬件抽像化层)hardware motion compensation(硬件运动补偿)HDTV(high definition television,高清晰度电视)HEL: Hardware Emulation Layer(硬件模拟层)high triangle count(复杂三角形计数)ICD(Installable Client Driver,可安装客户端驱动程序)IDCT(Inverse Discrete Cosine Transform,非连续反余弦变换,GeForce的DVD硬件强化技术)Immediate Mode,直接模式IPPR: (Image Processing and Pattern Recognition图像处理和模式识别)large textures(大型纹理)LF(Linear Filtering,线性过滤,即双线性过滤)lighting(光源)lightmap(光线映射)Local Peripheral Bus(局域边缘总线)mipmapping(MIP映射)Modulate(调制混合)Motion Compensation,动态补偿motion blur(模糊移动)MPPS:(Million Pixels Per Second,百万个像素/秒)Multi-Resolution Mesh,多重分辨率组合Multi Threaded Bus Master,多重主控Multitexture(多重纹理)nerest Mipmap(邻近MIP映射,又叫点采样技术)Overdraw(透支,全景渲染造成的浪费)partial texture downloads(并行纹理传输)Parallel Processing Perspective Engine(平行透视处理器)PC(Perspective Correction,透视纠正)PGC(Parallel Graphics Configuration,并行图像设置)pixel(Picture element,图像元素,又称P像素,屏幕上的像素点)point light(一般点光源)point sampling(点采样技术,又叫邻近MIP映射)Precise Pixel Interpolation,精确像素插值Procedural textures(可编程纹理)RAMDAC(Random Access Memory Digital to Analog Converter,随机存储器数/模转换器)Reflection mapping(反射贴图)ender(着色或渲染)S端子(Seperate)S3(Sight、Sound、Speed,视频、音频、速度)S3TC(S3 Texture Compress,S3纹理压缩,仅支持S3显卡)S3TL(S3 Transformation & Lighting,S3多边形转换和光源处理)Screen Buffer(屏幕缓冲)SDTV(Standard Definition Television,标准清晰度电视)SEM(spherical environment mapping,球形环境映射)Shading,描影Single Pass Multi-Texturing,单通道多纹理SLI(Scanline Interleave,扫描线间插,3Dfx的双Voodoo 2配合技术)Smart Filter(智能过滤)soft shadows(柔和阴影)soft reflections(柔和反射)spot light(小型点光源)SRA(Symmetric Rendering Architecture,对称渲染架构)Stencil Buffers(模板缓冲)Stream Processor(流线处理)SuperScaler Rendering,超标量渲染TBFB(Tile Based Frame Buffer,碎片纹理帧缓存)texel(T像素,纹理上的像素点)Texture Fidelity(纹理真实性)texture swapping(纹理交换)T&L(Transform and Lighting,多边形转换与光源处理)T-Buffer(T缓冲,3dfx Voodoo4的特效,包括全景反锯齿Full-scene Anti-Aliasing、动态模糊Motion Blur、焦点模糊Depth of Field Blur、柔和阴影Soft Shadows、柔和反射Soft Reflections)TCA(Twin Cache Architecture,双缓存结构)Transparency(透明状效果)Transformation(三角形转换)Trilinear Filtering(三线性过滤)Texture Modes,材质模式TMIPM: (Trilinear MIP Mapping三次线性MIP材质贴图)UMA(Unified Memory Architecture,统一内存架构)Visualize Geometry Engine,可视化几何引擎Vertex Lighting(顶点光源)Vertical Interpolation(垂直调变)VIP(Video Interface Port,视频接口)ViRGE: (Video and Rendering Graphics Engine视频描写图形引擎)Voxel(Volume pixels,立体像素,Novalogic的技术)VQTC(Vector-Quantization Texture Compression,向量纹理压缩)VSIS(Video Signal Standard,视频信号标准)v-sync(同步刷新)Z Buffer(Z缓存)5、音频3DPA(3D Positional Audio,3D定位音频)AC(Audio Codec,音频多媒体数字信号编解码器)Auxiliary Input(辅助输入接口)CS(Channel Separation,声道分离)DS3D(DirectSound 3D Streams)DSD(Direct Stream Digital,直接数字信号流)DSL(Down Loadable Sample,可下载的取样音色)DLS-2(Downloadable Sounds Level 2,第二代可下载音色)EAX(Environmental Audio Extensions,环境音效扩展技术)Extended Stereo(扩展式立体声)FM(Frequency Modulation,频率调制)FIR(finite impulse response,有限推进响应)FR(Frequence Response,频率响应)FSE(Frequency Shifter Effect,频率转换效果)HRTF(Head Related Transfer Function,头部关联传输功能)IID(Interaural Intensity Difference,两侧声音强度差别)IIR(infinite impulse response,无限推进响应)Interactive Around-Sound(交互式环绕声)Interactive 3D Audio(交互式3D音效)ITD(Interaural Time Difference,两侧声音时间延迟差别)MIDI:( Musical Instrument Digital Interface乐器数字接口)NDA:( non-DWORD-aligned ,非DWORD排列)Raw PCM:( Raw Pulse Code Modulated元脉码调制)RMA:( RealMedia Architecture实媒体架构)RTSP: (Real Time Streaming Protocol实时流协议)SACD(Super Audio CD,超级音乐CD)SNR(Signal to Noise Ratio,信噪比)S/PDIF(Sony/Phillips Digital Interface,索尼/飞利普数字接口)SRS: (Sound Retrieval System声音修复系统)Surround Sound(环绕立体声)Super Intelligent Sound ASIC(超级智能音频集成电路)THD+N(Total Harmonic Distortion plus Noise,总谐波失真加噪音)QEM(Qsound Environmental Modeling,Qsound环境建模扬声器组)WG(Wave Guide,波导合成)WT(Wave T able,波表合成)6、RAM & ROMABP: (Address Bit Permuting,地址位序列改变)ATC(Access Time from Clock,时钟存取时间)BSRAM(Burst pipelined synchronous static RAM,突发式管道同步静态存储器)CAS(Column Address Strobe,列地址控制器)CCT(Clock Cycle Time,时钟周期)DB: (Deep Buffer深度缓冲)DDR SDRAM(Double Date Rate,双数据率SDRAM)DIL(dual-in-line)DIMM(Dual In-line Memory Modules,双重内嵌式内存模块)DRAM(Dynamic Random Access Memory,动态随机存储器)DRDRAM(Direct RAMbus DRAM,直接RAMbus内存)ECC(Error Checking and Correction,错误检查修正)EEPROM(Electrically Erasable Programmable ROM,电擦写可编程只读存储器)FM: (Flash Memory快闪存储器)FMD ROM (Fluorescent Material Read Only Memory,荧光质只读存储器)PIROM:(Processor Information ROM,处理器信息ROM)PLEDM: Phase-state Low Electron(hole)-number Drive MemoryQBM(Quad Band Memory,四倍边带内存)RAC(Rambus Asic Cell,Rambus集成电路单元)RAS(Row Address Strobe,行地址控制器)RDRAM(Rambus Direct RAM,直接型RambusRAM)RIMM(RAMBUS In-line Memory Modules,RAMBUS内嵌式内存模块)SDR SDRAM(Single Date Rate,单数据率SDRAM)SGRAM(synchronous graphics RAM,同步图形随机储存器)SO-DIMM(Small Outline Dual In-line Memory Modules,小型双重内嵌式内存模块)SPD(Serial Presence Detect,串行存在检查)SRAM(Static Random Access Memory,静态随机存储器)SSTL-2(Stub Series Terminated Logic-2)TSOPs(thin small outline packages,超小型封装)USWV(Uncacheable, Speculative, Write-Combining非缓冲随机混合写入)VCMA(Virtual Channel Memory architecture,虚拟通道内存结构)7、磁盘AAT(Average access time,平均存取时间)ABS(Auto Balance System,自动平衡系统)ASMO(Advanced Storage Magneto-Optical,增强形光学存储器)AST(Average Seek time,平均寻道时间)ATA(AT Attachment,AT扩展型)ATOMM(Advanced super Thin-layer and high-Output Metal Media,增强形超薄高速金属媒体)bps(bit per second,位/秒)CAM(Common Access Model,公共存取模型)CSS(Common Command Set,通用指令集)DMA(Direct Memory Access,直接内存存取)DVD(Digital Video Disk,数字视频光盘)EIDE(enhanced Integrated Drive Electronics,增强形电子集成驱动器)FAT(File Allocation T ables,文件分配表)FDBM(Fluid dynamic bearing motors,液态轴承马达)FDC(Floppy Disk Controller,软盘驱动器控制装置)FDD(Floppy Disk Driver,软盘驱动器)GMR(giant magnetoresistive,巨型磁阻)HDA(head disk assembly,磁头集合)HiFD(high-capacity floppy disk,高容量软盘)IDE(Integrated Drive Electronics,电子集成驱动器)LBA(Logical Block Addressing,逻辑块寻址)MBR(Master Boot Record,主引导记录)MTBF(Mean Time Before Failure,平均故障时间)PIO(Programmed Input Output,可编程输入输出模式)PRML(Partial Response Maximum Likelihood,最大可能部分反应,用于提高磁盘读写传输率)RPM(Rotation Per Minute,转/分)RSD:(Removable Storage Device移动式存储设备)SCSI(Small Computer System Interface,小型计算机系统接口)SCMA:(SCSI Configured Auto Magically,SCSI自动配置)S.M.A.R.T.(Self-Monitoring, Analysis and Reporting Technology,自动监测、分析和报告技术)SPS(Shock Protection System,抗震保护系统)STA(SCSI Trade Association,SCSI同业公会)Ultra DMA(Ultra Direct Memory Access,超高速直接内存存取)LVD(Low Voltage Differential)Seagate硬盘技术DiscWizard(磁盘控制软件)DST(Drive Self Test,磁盘自检程序)SeaShield(防静电防撞击外壳)8、光驱ATAPI(AT Attachment Packet Interface)BCF(Boot Catalog File,启动目录文件)BIF(Boot Image File,启动映像文件)CDR(CD Recordable,可记录光盘)CD-ROM/XA(CD-ROM eXtended Architecture,唯读光盘增强形架构)CDRW(CD-Rewritable,可重复刻录光盘)CLV(Constant Linear Velocity,恒定线速度)DAE(digital Audio Extraction,数据音频抓取)DDSS(Double Dynamic Suspension System,双悬浮动态减震系统)DDSS II(Double Dynamic Suspension System II,第二代双层动力悬吊系统)PCAV(Part Constant Angular Velocity,部分恒定角速度)VCD(Video CD,视频CD)9、打印机AAS(Automatic Area Seagment?)dpi(dot per inch,每英寸的打印像素)ECP(Extended Capabilities Port,延长能力端口)EPP(Enhanced Parallel Port,增强形平行接口)IPP(Internet Printing Protocol,因特网打印协议)ppm(paper per minute,页/分)SPP(Standard Parallel Port,标准并行口)TET(Text Enhanced Technology,文本增强技术)USBDCDPD(Universal Serial Bus Device Class Definition for Printing Devices,打印设备的通用串行总线级标准)VD(Variable Dot,变点式列印)10、扫描仪TWAIN(Toolkit Without An Interesting Name)协议11、计算机公司Ali: Acer Lab(宏棋实验室)ASF: Applied Science FictionAMD: Advanced Micro Device(超微半导体)AMI: American Megatrends IncorporatedEAR(Extreme Audio Reality)HP: Hewlett-Packard,美国惠普公司IBM: International Business Machine,国际商业机器IDG(International Data Group,国际数据集团)IMS: International Meta SystemMLE:Microsoft Learning and Entertainment,微软教学与娱乐公司MS(Microsoft,微软)NAI: Network Associates Incorporation,前身为McAfee。
气象科学英语

气象科学英语Meteorology is a fascinating field of study that delves into the complex and dynamic processes of the Earth's atmosphere. As a branch of the atmospheric sciences, meteorology encompasses the observation, analysis, and prediction of weather phenomena, from the smallest local events to the most massive global patterns.At the heart of meteorology lies the study of the physical and chemical properties of the atmosphere, including its composition, temperature, pressure, and moisture content. By understanding these fundamental elements, meteorologists can develop models and simulations to forecast weather patterns with increasing accuracy and reliability.One of the primary goals of meteorology is to provide timely and accurate weather information to a wide range of stakeholders, from individuals and communities to industries and government agencies. This information can be crucial for decision-making, planning, and risk management, as weather events can have significant impacts on various aspects of human life and economic activities.Meteorologists employ a variety of tools and technologies to gatherand analyze data, including weather balloons, satellites, radar systems, and computer models. These tools allow them to monitor the atmosphere, track the movement of air masses, and detect the formation of weather systems such as storms, hurricanes, and fronts.One of the most challenging aspects of meteorology is the inherent complexity and unpredictability of the atmosphere. Weather patterns are influenced by a multitude of factors, including global climate patterns, local geography, and the interactions between different atmospheric layers. As a result, meteorologists must constantly refine their models and techniques to improve the accuracy of their forecasts.Despite these challenges, the field of meteorology has made significant advancements in recent decades, thanks to the development of more sophisticated observational and computational tools, as well as a deeper understanding of the underlying atmospheric processes. Today, meteorologists can provide detailed and reliable forecasts that help people and organizations prepare for and respond to a wide range of weather events, from severe storms and droughts to heat waves and cold snaps.Beyond weather forecasting, meteorology also plays a crucial role in studying the long-term trends and patterns of the Earth's climate. Meteorologists work closely with climatologists to analyze historicalweather data and develop models to predict future climate change scenarios. This information is essential for informing policy decisions, mitigating the impacts of climate change, and developing sustainable strategies for the future.In conclusion, the field of meteorology is a dynamic and multifaceted discipline that continues to evolve and expand our understanding of the Earth's atmosphere. From providing critical weather information to advancing our knowledge of global climate patterns, meteorologists play a vital role in shaping our understanding of the world around us and helping us navigate the challenges posed by an ever-changing environment.。
计算机系统结构

Computer Architecture, Spring 2008
2
Two approaches to exploit parallelism
Dynamic techniques largely depend on hardware to locate the parallelism Static techniques relay on software
Instruction i produces a result used by instruction j, or Instruction j is data dependent on instruction k, and instruction k is data dependent on instruction i
5
Computer Architecture, Spring 2008
Definition: Data Dependencies
Data dependence: instruction j is data dependent on instruction i if either of the following holds
Simplest and most common way to increase amount of parallelism among instruction is to exploit parallelism among iterations of a loop => Loop Level Parallelism for(i=1; i<=1000; i++) x[i]=x[i] + s; Vector Processing
Computer Architecture, Spring 2008
英语与电脑的关系

英语与电脑的关系世界上第一台电子计算机——埃尼亚克(ENIAC)于1946年诞生于美国宾夕法尼亚州,这就决定了计算机从发明之日起就使用英语作为人机交流的桥梁。
因此,我们可以说英语和电脑是“天生的一对,地配的一双”,两者相辅相成,密不可分。
电脑中的第一条命令、第一个语句乃至每一个符号以及用各种电脑高级程序设计语言编写的程序都是用英语单词或英语单词的缩写形式写成。
只要打开电脑,首先出现在屏幕上的各种信息都是用英语表达的,在DOS下操作电脑要键入的各种命令,也是一些英文单词或英文单词的缩写。
例如,COPY(拷贝文件命令)是英语单词,意为“复制、抄写”,DIR(显示目录命令)是英语单词Directory 缩略而来,REN(改变文件名命令)来自英语单词Rename。
世界上最大的电脑公司(IBM、Compaq、Apple),最大的CPU公司(Intel、AMD、Cyrix)、最大的软件公司(Mirosoft、Oracle)等都是美国的。
这些美国大公司的最新产品的包装、使用说明、软件的操作等最初使用的都是英语。
由此看来,电脑不但诞生在一个说英语的环境中,而且一开始就与英语密不可分,有着千丝万缕的联系。
使用和操作电脑的过程是人机对话的过程,电脑发展至今已出现了十分友好的界面,如Microsoft的Windows3.x、Windows95等,电脑从启动到运行都能够将工作状态及时地向用户提供准确的信息,这些信息通常由英文表达。
诚然,自从发明了汉字编码以来,根据我国的需要,业已开发出大量的汉化软件。
如北京希望电脑公司的UCDOS7.0,美国微软公司的中文Windows3.2、中文Windows95,很多信息包括一些计算机命令都可用汉语表达。
但是,由于我国电脑技术基础薄弱,起步较晚,吸收和汉化国外不断涌现的先进软件常常需要时日,而且由于计算机自身的特点,即使是汉化软件,许多信息也只能用英文表达。
要想充分利用国外先进软件,如果等到汉化后才去使用,也许当拿到汉化版本后,该软件早已过时。
Static and Dynamic Stress Analysis(静态和动态应力分析)

Chapter 5Static and Dynamic Stress Analysis第五章静态和动态应力分析5-1. Stress Analysis5-1.应力分析a. General.(1) A stress analysis of gravity dams is performed to determine the magnitude and distribution of stresses throughout the structure for static and dynamic load conditions and to investigate the structural adequacy of the substructance and foundation. Load conditions usually investigated are outlined in Chapter 4.(2) Gravity dam stresses are analyzed by either approximate simplified methods or the finite element method depending on the refinement required for the particular level of design and the type and configuration of the dam. For preliminary designs, simplified methods using cantilever beam models for two-dimensional analysis or the trial load twist method for three-dimensional analysis are appropriate as described in the US Bureau of Reclamation (USBR), “Design of Gravity Dams” (1976).The finite element method is ordinarily used for the feature and final design stages if a more exact stress investigation is required.a.普通方法(1)重力坝的应力分析是用以确定在静态和动态荷载作用下结构的应力分布和大小情况以及验证下部和基础的结构强度,荷载条件通常在第四章作了概述。
PowerPC 440中文资料

The PowerPC® 440 Core A high-performance, superscalar processor core for embedded applicationsIBM Microelectronics DivisionResearch Triangle Park, NC09/21/1999OverviewThe PowerPC 440 CPU core is the latest addition to IBM’s family of 32-bit RISC PowerPC embedded processor cores. The PPC440’s high-speed, superscalar design and Book E Enhanced PowerPC Architecture™ put it at the leading edge for high performance system-on-a-chip (SOC) designs. The PPC440 core marries the performance and features of standalone microprocessors with the flexibility, low power, and modularity of embedded CPU cores.Target ApplicationsThe PPC440 Core is primarily designed for applications in which maximum performance and extensive peripheral integration are the critical selection criteria.Target market segments for the PPC440 core include:•Consumer applications including digital cameras, video games, set-top boxes, and internet appliances •Office automation products such as laser printers, thin-client systems, and sub-notebooks •Storage and networking products such as RAID controllers, routers, ATM switches, cellular basestations, and network cardsFeatures•2-way superscalar design•Out-of-order issue, execution, and completion•Dynamic branch prediction•Single-cycle branch latency•Three execution pipelines•Single-cycle throughput on 32x32 multiply•24 DSP operations (16x16+32->32, MAC with single-cycle throughput)•Real-time non-invasive instruction traceTypical ApplicationA typical system on a chip design with the PPC440 Core uses the CoreConnect TM bus structure for system level communication. High bandwidth peripherals and the PPC440 core communicate with one another over the processor local bus (PLB). Less demanding peripherals share the on-chip peripheral bus (OPB) and communicate to the PLB through the OPB Bridge. The PLB and OPB provide common interfaces for peripherals and enable quick turnaround, custom solutions for high volume applications.F igure 1 shows an example PPC440 Core-based system on a chip, illustrating the two-level bus structure and modular core-based design.Figure 1. Example PPC440 Core + ASIC SpecificationsPerformance (Dhrystone 2.1)1000 MIPS @ 555MHz (est.), Nominal silicon, 1.8V, 55°C 720 MIPS @ 400MHz (est.), Slow silicon, 1.65V, 85°CFrequency0 – 400MHz , Slow silicon, 1.65V, 85°C555MHz nominalPower Dissipation 2.5mW / MHz @ 1.8V (est.), hard core with 32KI / 32KD cachesArchitecture32-bit PowerPC Book E compliant, application code compatible withall PowerPC processorsDie Size 4.0 mm2 for CPU only (est.)Caches0-64KB, 32-way to 128-way associativeTechnology0.18 µm CMOS copper technology0.12 µm L eff , 4 levels of metalPower Supply 1.8 VoltsTransistors 5.5M, hard core with 32KI / 32KD cachesOperating Range-40°C to 125°C, 1.6V to 1.9VData Bandwidth Up to 6.4 GB/sec via three 128-bit, 200MHz CoreConnect businterfacesTable 1- 440 CPU Core SpecificationsEmbedded Design SupportThe PPC440 Core, as a member of the PowerPC 400 Family, is supported by the IBM PowerPC Embedded Tools TM program, in which over 80 third party vendors have combined with IBM to provide a complete tools solution. Development tools for the PPC440 include C/C++ compilers, debuggers, bus functional models, hardware/software co-simulation environments, and real-time operating systems. As part of the tools program, IBM maintains a complete set of development tools by offering the High C/C++ Compiler, RISCWatch TM debugger with RISCTrace TM trace interface, VHDL and Verilog simulation models and a PPC440 Core Superstructure development kit.PPC440 CPU Core OrganizationPPC440 CPUThe PPC440 CPU operates on instructions in a dual issue, seven stage pipeline, capable of dispatching two instructions per clock to multiple execution units and to optional Auxiliary Processor Units (APUs). The PPC440 core is shown in Figure 2.Figure 2 - PPC440 Core Block DiagramThe pipeline contains the following stages, as shown in Figure 3:1.IFTH – Fetch instructions from instruction cache2.PDCD – Pre-decode; partial instruction decode3.DISS – Decode/Issue; final decode and issue to units4.RACC – Register Access; read from multi-ported General Purpose Register (GPR) file5.EXE1/AGEN – Execute stage 1; complete simple arithmetics, generate load/store address6.EXE2/CRD – Execute stage 2; multiplex in results from units in preparation for writing into GPRfile, Data Cache access7.WB – Writeback; write results into GPR file from integer operation or load operationFigure 3 - PPC440 CPU PipelineInstruction Fetch and Pre-decodeDuring the Instruction Fetch stage (IFTH), an entire cache line (eight words) is read into the instruction cache line read buffer. From there, the next two instructions in the pre-decode buffers PDCD0 and PDCD1 during the PDCD stage. The instruction cache is virtually indexed and tagged, and translation is performed in parallel with the cache access.Branch UnitThe PPC440 uses a Branch History Table (BHT) to maintain dynamic branch prediction of conditional branches. To perform dynamic branch prediction, a 2-bit counter in the BHT is used to decide whether prediction should agree or disagree with the normal PowerPC static branch prediction. The counter counts up if branch determination agrees, and down if it disagrees. Once the counter saturates, it can only count away from saturation. Therefore, four valid states exist: “Strongly agree”, “Agree”, “Disagree”, and “Strongly disagree”. By agreeing or disagreeing with static branch prediction, different branches can use the same counter in the BHT and have opposite static predictions, without the machine necessarily mispredicting a branch.The Branch Target Address Cache (BTAC) is used to predict branches and deliver their target addresses before the instruction cache can deliver the same data. It is accessed during IFTH, whereas normal branch prediction would not occur until PDCD, and therefore avoids a one cycle penalty. The BTAC is made up of an odd and even BTAC containing eight entries each. Only unconditional branches and bdnzinstructions are stored, which gives a significant performance boost while keeping the design straightforward.Decode and IssueThe four-entry decode queue accepts up to two instructions per clock submitted from the pre-decode buffers. Instructions always enter the lowest empty or emptying queue position, behind any instructions already in the queue. Therefore, the queue fills from the bottom up, instructions stay in order, and no bubbles exist in the queue. A significant portion of decode is performed in the lowest two positions (DISS0 and DISS1). Up to two instructions exit the queue based on the instructions’ decode and pipeline availability, and are issued to the RACC stage. DISS1 can issue out of order with respect to DISS0. Register AccessConceptually, the GPR file consists of thirty-two, 32-bit general purpose registers. It is implemented as two 6-port arrays, (one array for LRACC, one for IRACC) each with thirty-two, 32-bit registers containing three write ports and three read ports. On all GPR updating instructions, the appropriate GPR write ports will be written in order to keep the contents of the files the same. On GPR reads, however, the GPR read ports are dedicated to instructions that are dispatched to a RACC’s associated pipe(s). Execution PipelinesThe PPC440 contains three execution pipes: a load/store pipe (“L-pipe”), a simple integer pipe (“J-pipe”), and a complex integer pipe (“I-pipe”). The L-pipe and J-pipe instructions are dispatched from the LRACC; I-pipe instructions are dispatched from IRACC. The three pipes together perform all 32-bit PowerPC integer instructions in hardware compliant with the PowerPC Book E specification. Table 2 lists the rules for dispatching to each of the three execution pipes.L-pipe only Loads/stores1, cache instructions, mbar, msyncI-pipe or J-pipe2Add, addi, addis, and, andc, cntlzw, eqv, extsb, extsh, nand, neg, nor, or, orc, ori, oris, xori, xoris, rlwimi, rlwinm, rlwnm, slw, srw, subfI-pipe only Branches, multiplies, divides, move to/from DCR/SPR, indirect XER updates,indirect LR/CTR updates, indirect CR updates, CR-logicals, MAC instructions,mcrf, mcrxr, mtcrf, mfcr, compares, dlmzb, isync, rfi, rfci, sc, wrtee, wrteei,mtmsr, mfmsr, trapsTable 2 – Rules for Instruction IssueThe MAC unit is an auxiliary processor unit (APU) which adds 24 operations to the PPC440 instruction set. MAC instructions operate on either signed or unsigned 16 bit operands and accumulate the results in a 32-bit GPR. All MAC unit instructions have single cycle throughput. The MAC unit is contained within the I-pipe.1 The stwcx. instruction goes down both the L-pipe as well as the I-pipe, in order to update the CR.2 Instructions which update the CR or XER are not issued to the J-pipe.Instruction and Data CachesProcessor Local Bus (PLB) Memory AccessThe PPC440 has three independent 128-bit Processor Local Bus (PLB) master interfaces, one for instruction fetches, one for data reads, and a third for data writes. Memory accesses are performed through the PLB interfaces to/from the instruction cache (I-Cache) or data cache (D-Cache) units. Having three independent bus interfaces for the cache units provides maximum flexibility for designs to optimize system throughput. Memory accesses (loads/stores) which hit in the cache achieve single-cycle throughput.Cache ConfigurationThe PPC440 has separate instruction and data caches with 8 word (32 byte) cache lines. Instruction and data cache sizes are factory-configurable to any combination of 0KB, 8KB, 16KB, 32KB, or 64KB cache sizes. Configurable cache sizes provide designers with a parameter for optimizing the PPC440 to a desired price-performance for a particular application. The caches are highly associative, with associativity varying with cache size as shown in Table 3. High associativity enables advanced cache functions such as locking and transient memory regions (see “Cache Partitioning” below).Cache Size Ways8 KB3216KB6432KB6464KB128Table 3 – Number of Ways for Different PPC440 Cache SizesThe cache arrays are non-blocking. Non-blocking caches allow the PPC440 to overlap execution ofload/store instructions while instruction fetches take place over the PLB. The caches, therefore, continue supplying data and instructions without interruption to the pipeline. The PPC440 replaces cache lines according to a round-robin replacement policy.The initial PPC440A4 core offering will include a 32KB instruction cache and 32KB data cache. These caches are physically constructed using two, 16KB CAMRAM macros, each consisting of 8, 2KB sub-banks (or “sets”). This organization facilities low-power operation and fast hit/miss determination. Cache PartitioningThe PPC440 caches have the ability to be separated into “normal”, “transient”, and “locked” regions. Normal regions are what is traditionally thought of regarding cache replacement. Transient regions are used for data that is used temporarily and then not needed again, such as the data in a particular JPEG image. A separate transient region avoids castouts of more commonly accessed code in the normal region. The locked region is for code that is not to be cast out of the cache, and is the resulting region not included in the normal and transient regions. The regions are set via “victim” ceiling and floor pointers, as shown in Figure 4. Figure 4 shows two examples of cache partitioning, the left side shows separate transient and normal regions, and the right side shows part of the normal region overlapping with the transient region. The normal ceiling is defined as the top of the cache.Figure 4 – Two Examples of Cache PartitioningI-Cache Speculative Pre-fetchingThe I-Cache utilizes a programmable speculative pre-fetch mechanism to enhance performance. Software can enable up to three additional lines to be speculatively pre-fetched, using a burst protocol, upon any instruction cache miss. When this mode is enabled, the I-Cache controller will automatically inspect the I-Cache on a miss to see if any of up to the next three lines are also misses. If so, the hardware will present a burst request to the PLB immediately after the original line fill request. This speculative burst request takes advantage of the throughput capability of standard memory architectures such as SDRAM and brings in anticipated subsequent instructions after a miss. Furthermore, if the instruction stream branches away from the lines which are being speculatively filled, the burst request which is filling the speculative lines can be abandoned in the middle, and a new fill request at the branch target location immediately initiated. There is a programmable "threshold" to determine when to abandon a speculative line fill that may have been in progress at the time of a branch redirection. This threshold designates how many doublewords of the speculative cache line must be received to not abandon a current line fill. In this fashion, the speculative pre-fetch mechanism can be carefully tailored to provide optimum performance for specific applications and memory subsystems.D-Cache Line FillsThe D-Cache contains three line fill buffers and can queue up to four load misses to three separate cache lines. The PPC440 will then execute past these load misses, until the queue is full or the pipes are held waiting for a load value. The D-Cache controller places the target word on the bypass path as the fill buffer captures data words off the PLB. Additional requests of the cache line held in the fill buffer are also forwarded directly to the operand registers in the execute unit.D-Cache Non-cacheable Store GatheringThe D-Cache “gathers” up to 16 bytes for non-cacheable, write-through, and w/o allocate stores, and will burst the quadword to the PLB for fast writes to non-cacheable memory.D-Cache Write-Back and Write-Through ModesThe D-Cache supports write-back or write-through mode. In write-back mode, store hits are written to the cache and not to main memory. Main memory is later modified if and when the line is flushed from the cache. In write-through mode, the data cache controller writes main memory for store misses as well asstore hits; every store operation generates a PLB write request. (Although write-through requests to non-cacheable memory can be gathered as previously mentioned).D-Cache Store AllocationThe D-Cache can be programmed whether or not to allocate a line on a D-Cache store miss. Write-on-allocate is enabled by default. In this mode, a store miss to cacheable memory forces the data cache controller to allocate a line in the data cache and generate a line fill. In contrast, when “without allocate”is enabled, a store miss to cacheable memory will not allocate a line data cache and will simply write the data to memory.Big Endian and Little Endian SupportThe PPC440 supports big endian or little endian byte ordering for instructions and data stored in external memory. The PowerPC Book E architecture is endian neutral; each page in memory can be configured for big or little endian byte ordering via a storage attribute contained in the TLB entry for that region. Strapping signals on the PPC440 core initialize the beginning TLB entry’s endian attribute, so thePPC440 can boot from little or big endian memory.Memory Management Unit (MMU)The MMU supports multiple page sizes as well as a variety of storage protection attributes and access control options. Multiple page sizes improve TLB efficiency and minimize the number of TLB misses. The PPC440 gives programmers the flexibility to have any combination of the following eight possible page sizes in the translation look-aside buffer (TLB) simultaneously: 1KB, 4KB, 16KB, 64KB, 256KB,1MB, 16MB and 256MB. Having an extremely large page size allows users to define system memory with a minimal number of TLB entries, thereby simplifying TLB allocation and replacement. Small page sizes prevent the wasting of memory when allocating small areas of data.Each page of memory is accompanied by a set of storage attributes. These attributes include cacheability, write through/write back mode, big/little endian, guarded and four user-defined attributes. The user-defined attributes can be used to mark a memory page with an application-specific meaning. The guarded attribute controls speculative accesses. The big/little endian attribute marks a memory page as having big or little endian byte ordering. Write through/write back specifies whether memory is updated in addition to the cache during store operations.Two of the user-defined storage attributes can be programmed for special functions inside the core. One can be enabled to designate normal or transient cache regions. Another can be enabled to control whether or not store misses allocate a line in the D-Cache.Access control bits in the TLB entries enable system software to control read, write, and execute access for programs in both user and supervisor states.The MMU includes a 64-entry fully-associative unified TLB to reduce the overhead of address translation. Contention for the main TLB between data address and instruction address translation is minimized through the use of a four-entry instruction shadow TLB (ITLB) and an eight-entry data shadow TLB (DTLB). The ITLB and DTLB shadow the most recently used entries in the unified TLB. The MMU manages the replacement strategy of the ITLB and DTLB leaving the unified TLB to software control. Real-time operating systems are free to implement their own replacement algorithm for the unified TLB.Interrupt Handling LogicThe PPC440 services exceptions generated by error conditions, the internal timer facilities, debug events, and the external interrupt controller (EIC) interface. Altogether, there are sixteen different interrupt types supported.Interrupts are divided into two classes, critical and non-critical. Each class of interrupt has its own pair of save/restore registers for holding the program counter and machine state. Separate save/restore registers allow the PPC440 to quickly handle critical interrupts even within a non-critical interrupt handler. When an interrupt is taken, the PPC440 automatically writes the program counter and machine state to save/restore register SRR0 and SRR1 respectively for non-critical interrupts, or CSRR0 and CSRR1 respectively for critical interrupts. The machine status and program counter are automatically restored at the end of an exception handler when the return from interrupt (rfi) or return from critical interrupt (rfci) instruction is executed.TimersThe PPC440 contains a 64-bit time base and three timers: the Decrementer (DEC), the Fixed Interval Timer (FIT), and the WatchDog Timer (WDT). The time base counter increments synchronously with the CPU clock or an external clock source. The three timers are synchronous with the time base.The DEC is a 32-bit register that decrements at the time base increment rate. The user loads the DEC register with a value to create the desired delay. When the register reaches zero, the timer stops decrementing and generates a decrementer interrupt. Optionally, the DEC can be programmed to auto-reload the value last written to the DEC auto-reload register, after which the DEC continues to decrement.The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the selected bit changes from 0 to 1, the PPC440 generates a FIT exception.The watchdog timer provides a periodic critical-class interrupt based on a selected bit in the time base. This interrupt can be used for system error recovery in the event of software or system lockups. Users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset unless an exception handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals.Debug LogicAll architected resources on the PPC440 can be accessed through the debug logic. Upon a debug event, the PPC440 provides debug information to an external debug tool. Three different types of tools are supported depending on the debug mode: ROM Monitors, JTAG debuggers and instruction trace tools. Internal Debug ModeIn internal debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take over the PPC440 and communicate with a debug tool. Exception-handling software has read-write access to all registers and can set hardware or software breakpoints. ROM monitors typically use the internal debug mode.External Debug ModeIn external debug mode, the PPC440 enters stop state (i.e., stops instruction execution) when a debug event occurs. This mode offers a debug tool non-invasive read-write access to all registers in the PPC440 via the JTAG interface. Once the PPC440 is in stop state, the debug tool can start the PPC440, step an instruction, freeze the timers or set hardware or software break points. In addition to PPC440 control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring up.Debug Wait ModeDebug wait mode offers the same functionality as external debug mode with one difference; in debug wait mode, the PPC440 will respond to interrupts and temporarily leave stop state to service them before returning to debug wait mode. In external debug mode, by contrast, interrupts are disabled while in stop state. Debug wait mode is particularly useful when debugging real-time control systems.Real-Time Trace Debug ModeIn real-time trace debug mode, instruction trace information is continuously broadcast to the trace port. When a debug event occurs, an external debug tool saves instruction trace information before and after the event. The number of traced instructions depends only on the memory buffer depth of the trace tool. Debug EventsDebug events signal the debug logic to either stop the PPC440, put the PPC440 in debug wait state, cause a debug exception, or save instruction trace information, depending on the debug mode. Table 4 on the following page lists the possible debug events and their description.Debug Event DescriptionBranch Taken A Branch Taken debug event occurs prior to the execution ofa taken branch instruction.Instruction Completion The Instruction Completion debug event occurs after thecompletion of any instruction.Return from Interrupt The Return From Interrupt debug event occurs after thecompletion of an rfi or rfci instruction.Interrupt The Interrupt debug event occurs after an interrupt is taken. Trap The Trap debug event occurs prior to the execution of a trapinstruction, where the trap condition is met.Instruction Address Compare (IAC)The IAC debug event occurs prior to the execution of aninstruction at an address that matches the contents of one offour IAC registers (IAC1, IAC2, IAC3, and IAC4).Alternatively, the registers can be combined to cause an IACdebug event prior to the execution of an instruction at anaddress contained in one of the following ranges as specifiedby the four IAC registers:IAC1 <= range < IAC2 (inclusive),IAC3 <= range < IAC4 (inclusive),range low < IAC1 < IAC2 <= range high (exclusive), orrange low < IAC3 < IAC4 <= range high (exclusive).Data Address Compare (DAC)The DAC debug event occurs prior to the execution of aninstruction that accesses a data address matching the contentsof one of the two DAC registers (DAC1 and DAC2).Alternatively, the registers can be combined to cause a DACdebug event occurs prior to the execution of an instructionthat accesses a data address within one of the followingranges specified by the two DAC registers:DAC1 <= range < DAC2 (inclusive), orrange low < DAC1 < DAC2 <= range high (exclusive). Data Value Compare (DVC)The Data Value Compare debug event occurs prior to theexecution of an instruction that accesses a data addressmatching one of the two DAC registers (or within a DACrange) and containing a particular data value as specified byone of the two DVC registers. The DVC debug event mayoccur when a selected data byte, half-word or word matchesthe corresponding element in DVC1 or DVC2. Unconditional Event An unconditional debug event is set by a debug tool throughthe JTAG port or by ASIC logic external to the PPC440.Table 4 - Debug EventsPower ManagementThe PPC440 core, in keeping with the IBM PowerPC 400 family tradition, utilizes aggressive power management techniques for minimizing power. The PPC440 utilizes three key techniques: redundant operand registers, half-cycle latch stabilization, and dynamic clock gating.Redundant Operand RegistersRedundant operand registers are used at various pipeline stages for feeding operands to each of the execution units. This saves power by preventing unused units from seeing the operand values being used by other units and improves performance by reducing loading and wire length in critical stages.Half-Cycle Latch StabilizationHalf-cycle stabilization latches minimize the propagation of glitches to downstream logic. This is easily employed since the PPC440 core contains a master/slave latch arrangement for scan-test purposes. Therefore, a master-only latch is simply needed in the logic path that is switching in the first half of a cycle. For example, if the select lines for a mux are being determined in the first half of a cycle, then by putting a master-only latch on these select lines before delivering them to the mux, the mux outputs are prevented from glitching while the select lines are being determined. Conversely, if the data lines are unstable in the first half of a cycle, a stabilization latch may be used on the data inputs, while leaving the select lines alone.Dynamic Clock GatingThe most important feature of the PPC440’s dynamic power management is the extensive use of clock gating. Given the PPC440’s master/slave latch organization, there are two possible gates that can be used. The relationship between them, and their relative affect on the clock splitter and hence power are shown in Figure 5.Figure 5 - PPC440 Clock GatingIn this figure, the early gate blocks the phase 1 clock and prevents the master latch from loading, while the late gate blocks the phase 2 clock and prevents the slave latch from loading. As illustrated in the simplified block diagram of the clock splitter, the early gate must arrive by mid-cycle -- which is when the system clock falls. If the gate is activated by this point, then the net effect is that internal to the clock splitter the fall on the system clock is never observed, and both the phase 1 and the phase 2 clock splitteroutputs remain stable, preventing any downstream master latches from loading, and hence their associated slave latches will not change either. This affords the maximum power savings, with the downstream logic dissipating no power other than leakage, and the clock splitter itself using almost zero power.In the event that the gate for a given latch cannot be determined by mid-cycle, the late gate can be used, which does not prevent the system clock fall and consequent phase 1 clock rise, but does prevent the corresponding next phase 2 clock rise. This does not save as much power, but the timing is much more relaxed and the power savings are still considerable.。
分支预测器(Branch Predictor) 汇总介绍

当包含流水线技术的处理器处理分支指令时就会遇到一个问题,根据判定条件的真/假的不同,有可能会产生转跳,而这会打断流水线中指令的处理,因为处理器无法确定该指令的下一条指令,直到分支执行完毕。
流水线越长,处理器等待的时间便越长,因为它必须等待分支指令处理完毕,才能确定下一条进入流水线的指令。
分支预测技术便是为解决这一问题而出现的。
分支预测技术包含编译时进行的静态分支预测和硬件在执行时进行的动态分支预测。
静态分支预测: 最简单的静态分支预测方法就是任选一条分支。
1)认为branch一定会token;2)认为branch一定不会token;这样平均命中率为50%。
更精确的办法是根据原先运行的结果进行统计从而尝试预测分支是否会跳转。
任何一种分支预测策略的效果都取决于该策略本身的精确度和条件分支的频率。
SPARC与MIPS的最早实现(作为第一代商用RISC体系结构处理器)使用单方向静态分支预测:总是预测条件跳转不发生,因此总是顺序取下一条指令投机执行。
仅当条件跳转指令被求值确实发生了跳转,则非顺序的代码地址被加载执行。
两种CPU都是在解码阶段评价分支指令,取指令占用1个周期。
因此分支目标需要两个周期(即经过了去指令、解码两个周期)才能确定。
两种处理器都会在分支指令进入流水线的执行阶段时,插入一个分支延迟间隙。
分支指令完成流水线的执行阶段,就已经能确定是否跳转,这时就可以决定是后续的顺序出现的指令被继续执行还是跳转到的新指令进入流水。
更复杂的静态预测假定向后分支将会发生,向前的分支不会发生。
向后分支,是指跳转到的新地址比当前地址要低。
这有助于配合经常出现的程序的循环控制结构。
一些处理器允许分支预测提示出现在代码中。
Intel Pentium 4就是如此。
但这一特征在Intel此后的处理器中不再支持。
静态预测也用于某些处理器分支动态预测没有任何可用信息时的一个最后的办法。
Motorola MPC7450 动态分支预测:动态分支预测是近来的处理器已经尝试采用的的技术。
09-英汉句法比较-Static Vs Dynamic

禁止通行 禁止停车 禁止超车 禁止掉头 闲人免进 不准在此设摊兜售 包您满意,否则退款 保证三个月内免费维修 立正! 齐步走! 稍息! 未满十八岁者勿进 未经许可,车辆不得入
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No Thoroughfare No Parking No Passing No U-turn No Admittance Except on Business No Hawker Satisfaction or your money back. Full three months unconditiona的替代
1) be+表知觉、愿望、情感等心理活动的形容词=对动词的替代 ① Premier Wen Jiabao is very concerned about the high-speed train crash in Wenzhou City. 温家宝总理非常关心发生在温州市的高铁事故。 ② The American veterans are guilty of what they have done in Vietnam. 美国越战退伍军人为自己在越南所做的一切感到愧疚。 ③ I am optimistic about the future development of Sino-Japanese relations. 对中日关系的未来我持乐观的态度。 ④ I always think of my childhood these days. Maybe I’m a little bit nostalgic. 最近我总想起童年的事情,也许是有些怀旧吧。 ⑤ The girl is very sensitive and observant of the messages sent by others. 这个小女孩很敏感,他很善意观察别人的心思。
简述动态分支预测技术。

简述动态分支预测技术。
动态分支预测技术(DynamicBranchPrediction,DBP)是一种指令流水线技术,它可以极大地提高计算机在分支指令处理时的指令执行效率。
它也可以防止硬件资源的浪费和重复。
动态分支预测技术的原理很简单,它是在分支指令处预测出下一条指令是何种指令。
它可以有效地提高指令序列的执行速度,因为分支指令的处理需要花费更多的时间和资源。
当动态分支预测技术的原理运用到软件和硬件中时,能够有效地控制分支指令的执行和资源的利用。
动态分支预测技术的原理基于概率的预测技术。
它的基本方法是使用不同的指令序列来检测一个节点的指令将去哪个节点。
它使用分支指令的历史记录和概率来推断下一条指令可能会去哪个节点。
例如,当一个指令序列中出现了分支指令时,就会按照历史记录生成这个节点的概率,随后按照概率来预测下一条指令去哪个节点。
如果该节点概率较高,就可以预测出该节点是下一条指令要去的地方。
按照这种原理,动态分支预测技术可以把分支指令指向正确的目标和分支节点,从而提高指令执行的效率。
动态分支预测技术也可以用来防止硬件神经元被重复利用。
当一个指令序列被重复使用时,就可以使用动态分支预测技术来避免重复使用神经元,从而有效地节省硬件资源。
目前,随着硬件技术的发展,动态分支预测技术越来越得到普及和应用。
它不仅可以节省硬件资源,而且可以提高指令的执行速度。
例如, GCC,一款非常流行的计算机编程语言,在内部使用动态分支预测技术,它使用动态分支预测技术来优化程序的执行,从而提高程序运行的效率。
总而言之,动态分支预测技术是一种有效和有益的技术,它不仅可以节省硬件资源,而且可以提高指令的执行速度,从而提高程序处理的效率。
另外,它还可以有效地防止硬件资源的浪费和重复。
分支预测的名词解释

分支预测的名词解释分支预测(Branch Prediction)是计算机系统中的一个重要概念,它在程序中遇到分支指令时,根据历史运行数据和预测算法,预测分支指令的分支方向,以提高程序执行效率。
一、分支指令的概念及作用在计算机程序中,分支指令用于实现程序的选择性执行。
当程序需要根据某个条件决定执行哪条分支时,就会使用分支指令来实现这个功能。
例如,if条件语句和循环语句等都是用分支指令来实现的。
分支指令的正确预测对于程序性能的提高至关重要。
二、分支预测的背景与挑战随着计算机系统的发展,处理器的运行速度越来越快,而内存访问的速度却没有相应提高。
因此,处理器在执行指令过程中,可能会出现等待数据的情况。
而分支指令的执行是需要等待条件判断的结果的,这会导致处理器停下来等待条件判断结果,从而浪费了处理器的执行能力。
为了解决这个问题,分支预测应运而生。
三、分支预测的原理分支预测通过使用历史运行数据和预测算法来预测分支指令的分支方向。
其中,历史运行数据是指前一次或多次运行时,分支指令的实际执行结果。
预测算法则是根据历史运行数据,预测下一次分支指令的执行结果。
常见的预测算法包括:1.静态预测:静态预测是最简单的分支预测算法。
它假设每次分支指令都只会按照同一种方向执行,无论前一次的执行结果如何。
静态预测不依赖于历史运行数据,而只根据当前的指令信息进行预测。
尽管静态预测简单,但由于无法适应实际的程序特征,预测准确率较低。
2.动态预测:动态预测是目前主流的分支预测算法。
它使用历史运行数据和一系列的预测器来实现预测。
其中,预测器是用于记录以往运行中的分支指令的分支方向信息,以便下一次预测时使用。
常见的动态预测算法包括两位预测器、局部预测器和全局预测器。
四、分支预测的影响因素分支预测的准确度受多个因素影响。
以下是几个主要因素:1.分支指令的类型:不同类型的分支指令对预测算法的准确度有不同的要求。
例如,无条件分支指令很容易预测,而条件分支指令则需要更复杂的预测算法。
电子与计算机英语词组缩写

电子与计算机英语词组缩写简写All-In-On〔单一主板结构设计〕VGA〔Video Grephics Array〕视频图形阵列CRT〔Cathode Rey Tude〕阴极射线管LVDS〔Low V oltage Differential Signal〕低压差分信号LCD〔Liquid Crystal Display〕液晶显示器CPU〔Central Process Unit〕中央处理器DIY〔Do It Yourself〕自己动手做TFT〔Thin Film Tramsistor〕薄膜晶体管HDD〔Hard Disk Drive〕硬盘驱动器IDE〔Integrated Drive Electronics〕集成开发环境、电子集成驱动器SA TA〔Serial ATA〕串行ATAODD〔Optical Disk Drive〕光盘驱动器1×〔ODD中的一倍速〕150KB/SRAM〔Random Access Memory〕随机存取储备器Inverter〔高压板〕反向器XGA〔Extended Graphics Array〕延伸绘图陈设SVGA〔Super VGA〕UXGA〔Ultra XGA〕调整VGAWLAN〔Wireless Local Area Net〕无线局域网CCK〔Complementary Code Keying)补码键控调制OFDM〔Orthogonal Frequency Division Multiplexing〕正交频分多路复用技术FSB〔Front Side Bus〕前端总线SDRAM〔Synchronous Dynamic RAM〕同步动态RAMDDR〔Double Data Rate〕双倍数据传输率Stick Point〔指点杆〕Touth Pad〔触控板〕OEM〔Original Equipment Manufacturer〕电脑原始设备制造商ODM〔Original Design Manufacturer〕设计制造商R&D〔Research&Development〕研发PCB〔Print Circuit Board〕印制电路板EMI〔Electro Magnetic Interference 〕电磁干扰EMC〔Electro Magnetic Compatibility〕电磁兼容Blind Via(盲孔)Buried Via(埋孔)Through Via(通孔)PAD(焊点)VIA(导通孔)SMT(Surface Mount Technology) 表面安装技术ME(Mechabical engineer)机构工程师BOM(Bill Of Material)物料单DIP(Dual Inline Package)双列直插式组装QFP(Qual Flat Package)方型扁平封装PGA(Pin Grid Array)BGA(Ball Grid Array Package) 球栅阵列阵列CSP〔Ship Size Package〕芯片尺寸封装MCM〔Multi Chip Model〕多芯片模块OOBA (Out Of Box Audit)开箱检查Electric Screw Diver〔电动起子〕Fixture〔治具〕Barcode Scanner(条形码扫描仪)IPQC(In Process Quality Control) 制程中的质量检测人员OQC(Output Quality Control) 最终出货质量治理人员IQC(Incoming Quality Comtrol ) 进料质量治理人员OQA(Output Quality Assurance) 出货质量保证人员FAI(First Article Inspection) 新品首件检查FAA(First Article Assurance) 首件确认P/N(Part Number)料号L/N(Lot Number)批号PDCA(Plan Do Check Action) 打算、执行、检查、总结ECN(Engineering Change Notes) 工程变更通知〔供货商〕ECO(Engineering Change Order) 工程改动要求〔客户〕PCN(Process Change Notice) 工序改动通知PMP(Product Management Plan) 生产管制打算SOP(Standard Operation Procedure)制造作业规范IS(Inspection Specification)成品检验规范PS〔Package Specification〕包装规范SPEC〔Specification〕规格ES〔Engineering Standardization〕工程标准PO〔Purchasing Order〕采购订单MO〔Manufacture Orde〕生产单D/C〔Date Code〕生产日期码ID/C〔Identification Code〕〔供货商〕识别码ESD〔Electro Static Discharge〕静电排放ASS’Y〔Assembly〕组装MAT’S〔Material〕材料LED〔Light-Emitting Diode〕发光二极管COA〔Certification Of Authentication〕微软之授权条码EOL〔End Of Life〕产品生产周期SCSI〔Small Computer System Interface〕小型运算机接口系统BIOS〔Basic Input/Output System〕差不多输入输出系统SFIS〔Shop Floor Information System〕现场信息整合系统IC〔Integrated Circuit〕集成电路SPC〔Statistical Process Control〕统计制程管制SQC〔Statistical Quality Control〕统计品质管制DIM〔Dimension 〕尺寸DIA〔Diameter〕直径SIP〔Standard Inspection Procedure〕制程检验标准程序IS〔Inspection Specification〕成品检验规范MC〔Material Control〕物料操纵PCC〔Production Plan Control〕生产打算操纵N/A〔Not Applicable〕不适用NG〔Not Good〕不良AC(alternating current) 交流(电)A/D(analog to digital) 模拟/数字转换ADC(analog to digital convertor) 模拟/数字转换器ADM(adaptive delta modulation) 自适应增量调制ADPCM(adaptive differential pulse code modulation) 自适应差分脉冲编码调制ALU(arithmetic logic unit) 算术逻辑单ASCII(American standard code for informationinterchange) 美国信息交换标准码A V(audio visual) 声视,视听BCD(binary coded decimal) 二进制编码的十进制数BCR(bi-directional controlled rectifier)双向晶闸管BCR(buffer courtier reset) 缓冲计数器BZ(buzzer) 蜂鸣器,蜂音器C(capacitance,capacitor) 电容量,电容器CATV(cable television) 电缆电视CCD(charge-coupled device) 电荷耦合器件CCTV(closed-circuit television) 闭路电视CMOS(complementary) 互补MOSCPU(central processing unit)**处理单元CS(control signal) 操纵信号D(diode) 二极管DAST(direct analog store technology) 直截了当模拟储备技术DC(direct current) 直流DIP(dual in-line package) 双列直插封装DP(dial pulse) 拨号脉冲DRAM(dynamic random access memory) 动态随机储备器DTL(diode-transistor logic) 二极管晶体管逻辑DUT(device under test) 被测器件DVM(digital voltmeter) 数字电压表ECG(electrocardiograph) 心电图ECL(emitter coupled logic) 射极耦合逻辑EDI(electronic data interchange) 电子数据交换EIA(Electronic Industries Association) 电子工业联合会EOC(end of conversion) 转换终止EPROM(erasable programmable read only memory) 可擦可编程只读储备器EEPROM(electrically EPROM) 电可擦可编程只读储备器ESD(electro-static discharge) 静电放电FET(field-effect transistor) 场效应晶体管FS(full scale) 满量程F/V(frequency to voltage convertor) 频率/电压转换FM(frequency modulation) 调频FSK(frequency shift keying) 频移键控FSM(field strength meter) 场强计FST(fast switching shyster) 快速晶闸管FU(fuse unit) 保险丝装置FWD(forward) 正向的GAL(generic array logic) 通用阵列逻辑GND(ground) 接地,地线GTO(Sate turn off thruster) 门极可关断晶体管HART(highway addressable remote transducer) 可寻址远程传感器数据公路HCMOS(high density COMS) 高密度互补金属氧化物半导体(器件)HF(high frequency) 高频HTL(high threshold logic) 高阈值逻辑电路HTS(heat temperature sensor) 热温度传感器IC(integrated circuit) 集成电路ID(international data) 国际数据IGBT(insulated gate bipolar transistor) 绝缘栅双极型晶体管IGFET(insulated gate field effect transistor) 绝缘栅场效应晶体管I/O(input/output) 输入/输出I/V(current to voltage convertor) 电流-电压变换器IPM(incidental phase modulation) 附带的相位调制IPM(intelligent power module) 智能功率模块IR(infrared radiation) 红外辐射IRQ(interrupt request) 中断要求JFET(junction field effect transistor) 结型场效应晶体管LAS(light activated switch)光敏开关LASCS(light activated silicon controlled switch) 光控可控硅开关LCD(liquid crystal display) 液晶显示器LDR(light dependent resistor) 光敏电阻LED(light emitting diode) 发光二极管LRC(longitudinal redundancy check) 纵向冗余(码)校验LSB(least significant bit) 最低有效位LSI(1arge scale integration) 大规模集成电路M(motor) 电动机MCT(MOS controlled gyrator) 场控晶闸管MIC(microphone) 话筒,微音器,麦克风min(minute) 分MOS(metal oxide semiconductor)金属氧化物半导体MOSFET(metal oxide semiconductor FET) 金属氧化物半导体场效应晶体管[ N(negative) 负NMOS(N-channel metal oxide semiconductor FET) N沟道MOSFETNTC(negative temperature coefficient) 负温度系数OC(over current) 过电流OCB(overload circuit breaker) 过载断路器OCS(optical communication system) 光通讯系统}OR(type of logic circuit) 或逻辑电路OV(over voltage) 过电压P(pressure) 压力FAM(pulse amplitude modulation) 脉冲幅度调制PC(pulse code) 脉冲码PCM(pulse code modulation) 脉冲编码调制PDM(pulse duration modulation) 脉冲宽度调制PF(power factor) 功率因数PFM(pulse frequency modulation) 脉冲频率调制PG(pulse generator) 脉冲发生器PGM(programmable) 编程信号PI(proportional-integral(controller)) 比例积分(操纵器)PID(proportional-integral-differential(controller))比例积分微分(操纵器)PIN(positive intrinsic-negative) 光电二极管PIO(parallel input output) 并行输入输出PLD(phase-locked detector) 同相检波PLD(phase-locked discriminator) 锁相解调器PLL(phase-locked loop) 锁相环路PMOS(P-channel metal oxide semiconductor FET) P沟道MOSFET PPM(pulse phase modulation) 脉冲相位洲制PRD(piezoelectric radiation detector) 热电辐射控测器PROM(programmable read only memory) 可编只读程储备器PRT(platinum resistance thermometer) 铂电阻温度计PRT(pulse recurrent time) 脉冲周期时刻PUT(programmable unijunction transistor) 可编程单结晶体管PWM(pulse width modulation) 脉宽调制R(resistance,resistor) 电阻,电阻器RCT(reverse conducting thyristor) 逆导晶闸管REF(reference) 参考,基准REV(reverse) 反转R/F(radio frequency) 射频RGB(red/green/blue) 红绿蓝ROM(read only memory) 只读储备器RP(resistance potentiometer) 电位器RT(resistor with inherent variability dependent) 热敏电阻RTD(resistance temperature detector) 电阻温度传感器RTL(resistor transistor logic) 电阻晶体管逻辑(电路)RV(resistor with inherent variability dependent on thevoltage) 压敏电阻器SA(switching assembly) 开关组件SBS(silicon bi-directional switch) 硅双向开关,双向硅开关SCR(silicon controlled rectifier) 可控硅整流器SCS(safety control switch) 安全操纵开关SCS(silicon controlled switch) 可控硅开关SCS(speed control system) 速度操纵系统SCS(supply control system) 电源操纵系统SG(spark gap) 放电器SIT(static induction transformer) 静电感应晶体管SITH(static induction thyristor) 静电感应晶闸管SP(shift pulse) 移位脉冲kwSnT]]SPI(serial peripheral interface) 串行外围接口SR(sample realy,saturable reactor) 取样继电器,饱和电抗器SR(silicon rectifier) 硅整流器SRAM(static random access memory) 静态随机储备器SSR(solid-state relay) 固体继电器SSR(switching select repeater) 中断器开关选择器SSS(silicon symmetrical switch) 硅对称开关,双向可控硅SSW(synchro-switch) 同步开关ST(start) 启动ST(starter) 启动器STB(strobe) 闸门,选通脉冲T(transistor) 晶体管,晶闸管TACH(tachometer) 转速计,转速表TP(temperature probe) 温度传感器TRIAC(triodes AC switch) 三极管交流开关TTL(transistor-transistor logic) 晶体管一晶体管逻辑TV(television) 电视UART(universal asynchronous receiver transmitter) 通用异步收发器VCO(voltage controlled oscillator) 压控振荡器VD(video decoders) 视频译码器VDR(voltage dependent resistor) 压敏电阻VF(video frequency) 视频V/F(voltage-to-frequency) 电压/频率转换V/I(voltage to current convertor) 电压-电流变换器VM(voltmeter) 电压表VS(vacuum switch) 电子开关VT(visual telephone) 电视VT(video terminal) 视频终端1、CPU3DNow!〔3D no waiting〕ALU〔Arithmetic Logic Unit,算术逻辑单元〕AGU〔Address Generation Units,地址产成单元〕BGA〔Ball Grid Array,球状矩阵排列〕BHT〔branch prediction table,分支推测表〕BPU〔Branch Processing Unit,分支处理单元〕Brach Pediction〔分支推测〕CMOS: 〔Complementary Metal Oxide Semiconductor,互补金属氧化物半导体〕CISC〔Complex Instruction Set Computing,复杂指令集运算机〕CLK〔Clock Cycle,时钟周期〕COB〔Cache on board,板上集成缓存〕COD〔Cache on Die,芯片内集成缓存〕CPGA〔Ceramic Pin Grid Array,陶瓷针型栅格阵列〕CPU〔Center Processing Unit,中央处理器〕Data Forwarding〔数据前送〕Decode〔指令解码〕DIB〔Dual Independent Bus,双独立总线〕EC〔Embedded Controller,嵌入式操纵器〕Embedded Chips〔嵌入式〕EPIC〔explicitly parallel instruction code,并行指令代码〕FADD〔Floationg Point Addition,浮点加〕FCPGA〔Flip Chip Pin Grid Array,反转芯片针脚栅格阵列〕FDIV〔Floationg Point Divide,浮点除〕FEMMS:〔Fast Entry/Exit Multimedia State,快速进入/退出多媒体状态〕FFT〔fast Fourier transform,快速热欧姆转换〕FID〔FID:Frequency identify,频率鉴别号码〕FIFO〔First Input First Output,先入先出队列〕flip-chip〔芯片反转〕FLOP〔Floating Point Operations Per Second,浮点操作/秒〕FMUL〔Floationg Point Multiplication,浮点乘〕FPU〔Float Point Unit,浮点运算单元〕FSUB〔Floationg Point Subtraction,浮点减〕GVPP〔Generic Visual Perception Processor,常规视觉处理器〕HL-PBGA: 表面黏著,高耐热、轻薄型塑胶球状矩阵封装IA〔Intel Architecture,英特尔架构〕ICU〔Instruction Control Unit,指令操纵单元〕ID:〔identify,鉴别号码〕IDF〔Intel Developer Forum,英特尔开发者论坛〕IEU〔Integer Execution Units,整数执行单元〕IMM:〔Intel Mobile Module, 英特尔移动模块〕Instructions Cache,指令缓存Instruction Coloring〔指令分类〕IPC〔Instructions Per Clock Cycle,指令/时钟周期〕ISA〔instruction set architecture,指令集架构〕KNI〔Katmai New Instructions,Katmai新指令集,即SSE〕Latency〔埋伏期〕LDT〔Lightning Data Transport,闪电数据传输总线〕Local Interconnect〔局域互连〕MESI〔Modified, Exclusive, Shared, Invalid:修改、排除、共享、废弃〕MMX〔MultiMedia Extensions,多媒体扩展指令集〕MMU〔Multimedia Unit,多媒体单元〕MFLOPS〔Million Floationg Point/Second,每秒百万个浮点操作〕MHz〔Million Hertz,兆赫兹〕MP〔Multi-Processing,多重处理器架构〕MPS〔MultiProcessor Specification,多重处理器规范〕MSRs〔Model-Specific Registers,专门模块寄存器〕NAOC〔no-account OverClock,无效超频〕NI:〔Non-Intel,非英特尔〕OLGA〔Organic Land Grid Array,基板栅格阵列〕OoO〔Out of Order,乱序执行〕PGA: Pin-Grid Array〔引脚网格阵列〕,耗电大Post-RISCPR〔Performance Rate,性能比率〕PSN〔Processor Serial numbers,处理器序列号〕PIB〔Processor In a Box,盒装处理器〕PPGA〔Plastic Pin Grid Array,塑胶针状矩阵封装〕PQFP〔Plastic Quad Flat Package,塑料方块平面封装〕RAW〔Read after Write,写后读〕Register Contention〔抢占寄存器〕Register Pressure〔寄存器不足〕Register Renaming〔寄存重视命名〕Remark〔芯片频率重标识〕Resource contention〔资源冲突〕Retirement〔指令引退〕RISC〔Reduced Instruction Set Computing,精简指令集运算机〕SEC:〔Single Edge Connector,单边连接器〕Shallow-trench isolation〔浅槽隔离〕SIMD〔Single Instruction Multiple Data,单指令多数据流〕SiO2F〔Fluorided Silicon Oxide,二氧氟化硅〕SMI〔System Management Interrupt,系统治理中断〕SMM〔System Management Mode,系统治理模式〕SMP〔Symmetric Multi-Processing,对称式多重处理架构〕SOI: 〔Silicon-on-insulator,绝缘体硅片〕SONC〔System on a chip,系统集成芯片〕SPEC〔System Performance Evaluation Corporation,系统性能评估测试〕SQRT〔Square Root Calculations,平方根运算〕SSE〔Streaming SIMD Extensions,单一指令多数据流扩展〕Superscalar〔超标量体系结构〕TCP: Tape Carrier Package〔薄膜封装〕,发热小Throughput〔吞吐量〕TLB〔Translate Look side Buffers,翻译旁视缓冲器〕USWC〔Uncacheabled Speculative Write Combination,无缓冲随机联合写操作〕VALU〔Vector Arithmetic Logic Unit,向量算术逻辑单元〕VLIW〔Very Long Instruction Word,超长指令字〕VPU〔Vector Permutate Unit,向量排列单元〕VPU〔vector processing units,向量处理单元,即处理MMX、SSE等SIMD指令的地点〕2、主板ADIMM〔advanced Dual In-line Memory Modules,高级双重内嵌式内存模块〕AMR〔Audio/Modem Riser;音效/调制解调器主机板附加直立插卡〕AHA〔Accelerated Hub Architecture,加速中心架构〕ASK IR〔Amplitude Shift Keyed Infra-Red,长波形可移动输入红外线〕ATX: AT Extend〔扩展型AT〕BIOS〔Basic Input/Output System,差不多输入/输出系统〕CSE〔Configuration Space Enable,可分配空间〕DB:〔Device Bay,设备插架〕DMI〔Desktop Management Interface,桌面治理接口〕EB〔Expansion Bus,扩展总线〕EISA〔Enhanced Industry Standard Architecture,增强形工业标准架构〕EMI〔Electromagnetic Interference,电磁干扰〕ESCD〔Extended System Configuration Data,可扩展系统配置数据〕FBC〔Frame Buffer Cache,帧缓冲缓存〕FireWire〔火线,即IEEE1394标准〕FSB: 〔Front Side Bus,前置总线,即外部总线〕FWH〔Firmware Hub,固件中心〕GMCH〔Graphics & Memory Controller Hub,图形和内存操纵中心〕GPIs〔General Purpose Inputs,一般操作输入〕ICH〔Input/Output Controller Hub,输入/输出操纵中心〕IR〔infrared ray,红外线〕IrDA〔infrared ray,红外线通信接口可进行局域网存取和文件共享〕ISA:〔Industry Standard Architecture,工业标准架构〕ISA〔instruction set architecture,工业设置架构〕MDC〔Mobile Daughter Card,移动式子卡〕MRH-R〔Memory Repeater Hub,内存数据处理中心〕MRH-S〔SDRAM Repeater Hub,SDRAM数据处理中心〕MTH〔Memory Transfer Hub,内存转换中心〕NGIO〔Next Generation Input/Output,新一代输入/输出标准〕P64H〔64-bit PCI Controller Hub,64位PCI操纵中心〕PCB〔printed circuit board,印刷电路板〕PCBA〔Printed Circuit Board Assembly,印刷电路板装配〕PCI:〔Peripheral Component Interconnect,互连外围设备〕PCI SIG〔Peripheral Component Interconnect Special Interest Group,互连外围设备专业组〕POST〔Power On Self Test,加电自测试〕RNG〔Random number Generator,随机数字发生器〕RTC: 〔Real Time Clock 实时时钟〕KBC〔KeyBroad Control,键盘操纵器〕SAP〔Sideband Address Port,边带寻址端口〕SBA〔Side Band Addressing,边带寻址〕SMA: 〔Share Memory Architecture,共享内存结构〕STD〔Suspend To Disk,磁盘唤醒〕STR〔Suspend To RAM,内存唤醒〕SVR: 〔Switching V oltage Regulator 交换式电压调剂〕USB〔Universal Serial Bus,通用串行总线〕USDM〔Unified System Diagnostic Manager,统一系统监测治理器〕VID〔V oltage Identification Definition,电压识别认证〕VRM 〔V oltage Regulator Module,电压调整模块〕ZIF: 〔Zero Insertion Force, 零插力〕ACOPS:〔Automatic CPU OverHeat Prevention SystemCPU 过热预防系统〕SIV: 〔System Information Viewer系统信息观看〕ESDJ〔Easy Setting Dual Jumper,简化CPU双重跳线法〕浩鑫UPT〔USB、PANEL、LINK、TV-OUT四重接口〕芯片组ACPI〔Advanced Configuration and Power Interface,先进设置和电源治理〕AGP〔Accelerated Graphics Port,图形加速接口〕I/O〔Input/Output,输入/输出〕MIOC: 〔Memory and I/O Bridge Controller,内存和I/O桥操纵器〕NBC: 〔North Bridge Chip北桥芯片〕PIIX: 〔PCI ISA/IDE Accelerator加速器〕PSE36: 〔Page Size Extension 36-bit,36位页面尺寸扩展模式〕PXB:〔PCI Expander Bridge,PCI增强桥〕RCG: 〔RAS/CAS Generator,RAS/CAS发生器〕SBC: 〔South Bridge Chip南桥芯片〕SMB: 〔System Management Bus全系统治理总线〕SPD〔Serial Presence Detect,内存内部序号检测装置〕SSB: 〔Super South Bridge,超级南桥芯片〕TDP:〔Triton Data Path数据路径〕TSC: 〔Triton System Controller系统操纵器〕QPA: 〔Quad Port Acceleration四接口加速〕3、显示设备ASIC: 〔Application Specific Integrated Circuit专门应用积体电路〕ASC〔Auto-Sizing and Centering,自动调效屏幕尺寸和中心位置〕ASC〔Anti Static Coatings,防静电涂层〕AGAS〔Anti Glare Anti Static Coatings,防强光、防静电涂层〕BLA: 〔Bearn Landing Area电子束落区〕BMC〔Black Matrix Screen,超黑矩阵屏幕〕CRC: 〔Cyclical Redundancy Check循环冗余检查〕CRT〔Cathode Ray Tube,阴极射线管〕DDC:〔Display Data Channel,显示数据通道〕DEC〔Direct Etching Coatings,表面蚀刻涂层〕DFL〔Dynamic Focus Lens,动态聚焦〕DFS〔Digital Flex Scan,数字伸缩扫描〕DIC: 〔Digital Image Control数字图像操纵〕Digital Multiscan II〔数字式智能多频追踪〕DLP〔digital Light Processing,数字光处理〕DOSD:〔Digital On Screen Display同屏数字化显示〕DPMS〔Display Power Management Signalling,显示能源治理信号〕Dot Pitch〔点距〕DQL〔Dynamic Quadrapole Lens,动态四极镜〕DSP〔Digital Signal Processing,数字信号处理〕EFEAL〔Extended Field Elliptical Aperture Lens,可扩展扫描椭圆孔镜头〕FRC:〔Frame Rate Control帧比率操纵〕HVD〔High V oltage Differential,高分差动〕LCD〔liquid crystal display,液晶显示屏〕LCOS: 〔Liquid Crystal On Silicon硅上液晶〕LED〔light emitting diode,光学二级管〕L-SAGIC〔Low Power-Small Aperture G1 wiht Impregnated Cathode,低电压光圈阴极管〕LVD〔Low V oltage Differential,低分差动〕LVDS:〔Low V oltage Differential Signal低电压差动信号〕MALS〔Multi Astigmatism Lens System,多重散光聚焦系统〕MDA〔Monochrome Adapter,单色设备〕MS: 〔Magnetic Sensors磁场感应器〕Porous Tungsten〔活性钨〕RSDS: 〔Reduced Swing Differential Signal小幅度摆动差动信号〕SC〔Screen Coatings,屏幕涂层〕Single Ended〔单终结〕Shadow Mask〔阴罩式〕TDT〔Timeing Detection Table,数据测定表〕TICRG: 〔Tungsten Impregnated Cathode Ray Gun钨传输阴级射线枪〕TFT〔thin film transistor,薄膜晶体管〕UCC〔Ultra Clear Coatings,超清晰涂层〕VAGP:〔Variable Aperature Grille Pitch可变间距光栅〕VBI:〔Vertical Blanking Interval垂直空白间隙〕VDT〔Video Display Terminals,视频显示终端〕VRR: 〔Vertical Refresh Rate垂直扫描频率〕4、视频3D:〔Three Dimensional,三维〕3DS〔3D SubSystem,三维子系统〕AE〔Atmospheric Effects,雾化成效〕AFR〔Alternate Frame Rendering,交替渲染技术〕Anisotropic Filtering〔各向异性过滤〕APPE〔Advanced Packet Parsing Engine,增强形帧解析引擎〕A V〔Analog Video,模拟视频〕Back Buffer,后置缓冲Backface culling〔隐面排除〕Battle for Eyeballs〔眼球大战,各3D图形芯片公司为了争夺用户而作的竞争〕Bilinear Filtering〔双线性过滤〕CEM〔cube environment mapping,立方环境映射〕CG〔Computer Graphics,运算机生成图像〕Clipping〔剪贴纹理〕Clock Synthesizer,时钟合成器compressed textures〔压缩纹理〕Concurrent Command Engine,协作命令引擎Center Processing Unit Utilization,中央处理器占用率DAC〔Digital to Analog Converter,数模传换器〕Decal〔印花法,用于生成一些半透亮成效,如:鲜血飞溅的场面〕DFP〔Digital Flat Panel,数字式平面显示器〕DFS:〔Dynamic Flat Shading动态平面描影,可用作加速Dithering抖动〕Directional Light,方向性光源DME:〔Direct Memory Execute直截了当内存执行〕DOF〔Depth of Field,多重境深〕dot texture blending〔点型纹理混和〕Double Buffering〔双缓冲区〕DIR〔Direct Rendering Infrastructure,基层直截了当渲染〕DVI〔Digital Video Interface,数字视频接口〕DxR:〔DynamicXTended Resolution动态可扩展辨论率〕DXTC〔Direct X Texture Compress,DirectX纹理压缩,以S3TC为基础〕Dynamic Z-buffering〔动态Z轴缓冲区〕,显示物体远近,可用作远景E-DDC〔Enhanced Display Data Channel,增强形视频数据通道协议,定义了显示输出与主系统之间的通讯通道,能提高显示输出的画面质量〕Edge Anti-aliasing,边缘抗锯齿失真E-EDID〔Enhanced Extended Identification Data,增强形扩充身份辨识数据,定义了电脑通讯视频主系统的数据格式〕Execute Buffers,执行缓冲区environment mapped bump mapping〔环境凹凸映射〕Extended Burst Transactions,增强式突发处理Front Buffer,前置缓冲Flat〔平面描影〕Frames rate is King〔帧数为王〕FSAA〔Full Scene Anti-aliasing,全景抗锯齿〕Fog〔雾化成效〕flip double buffered〔反转双缓存〕fog table quality〔雾化表画质〕GART〔Graphic Address Remappng Table,图形地址重绘表〕Gouraud Shading,高洛德描影,也称为内插法平均涂色GPU〔Graphics Processing Unit,图形处理器〕GTF〔Generalized Timing Formula,一样程序时刻,定义了产生画面所需要的时刻,包括了诸如画面刷新率等〕HAL〔Hardware Abstraction Layer,硬件抽像化层〕hardware motion compensation〔硬件运动补偿〕HDTV〔high definition television,高清晰度电视〕HEL: Hardware Emulation Layer〔硬件模拟层〕high triangle count〔复杂三角形计数〕ICD〔Installable Client Driver,可安装客户端驱动程序〕IDCT〔Inverse Discrete Cosine Transform,非连续反余弦变换,GeForce的DVD硬件强化技术〕Immediate Mode,直截了当模式IPPR: 〔Image Processing and Pattern Recognition图像处理和模式识别〕large textures〔大型纹理〕LF〔Linear Filtering,线性过滤,即双线性过滤〕lighting〔光源〕lightmap〔光线映射〕Local Peripheral Bus〔局域边缘总线〕mipmapping〔MIP映射〕Modulate〔调制混合〕Motion Compensation,动态补偿motion blur〔模糊移动〕MPPS:〔Million Pixels Per Second,百万个像素/秒〕Multi-Resolution Mesh,多重辨论率组合Multi Threaded Bus Master,多重主控Multitexture〔多重纹理〕nerest Mipmap〔邻近MIP映射,又叫点采样技术〕Overdraw〔透支,全景渲染造成的白费〕partial texture downloads〔并行纹理传输〕Parallel Processing Perspective Engine〔平行透视处理器〕PC〔Perspective Correction,透视纠正〕PGC〔Parallel Graphics Configuration,并行图像设置〕pixel〔Picture element,图像元素,又称P像素,屏幕上的像素点〕point light〔一样点光源〕point sampling〔点采样技术,又叫邻近MIP映射〕Precise Pixel Interpolation,精确像素插值Procedural textures〔可编程纹理〕RAMDAC〔Random Access Memory Digital to Analog Converter,随机储备器数/模转换器〕Reflection mapping〔反射贴图〕ender〔着色或渲染〕S端子〔Seperate〕S3〔Sight、Sound、Speed,视频、音频、速度〕S3TC〔S3 Texture Compress,S3纹理压缩,仅支持S3显卡〕S3TL〔S3 Transformation & Lighting,S3多边形转换和光源处理〕Screen Buffer〔屏幕缓冲〕SDTV〔Standard Definition Television,标准清晰度电视〕SEM〔spherical environment mapping,球形环境映射〕Shading,描影Single Pass Multi-Texturing,单通道多纹理SLI〔Scanline Interleave,扫描线间插,3Dfx的双V oodoo 2配合技术〕Smart Filter〔智能过滤〕soft shadows〔柔和阴影〕soft reflections〔柔和反射〕spot light〔小型点光源〕SRA〔Symmetric Rendering Architecture,对称渲染架构〕Stencil Buffers〔模板缓冲〕Stream Processor〔流线处理〕SuperScaler Rendering,超标量渲染TBFB〔Tile Based Frame Buffer,碎片纹理帧缓存〕texel〔T像素,纹理上的像素点〕Texture Fidelity〔纹理真实性〕texture swapping〔纹理交换〕T&L〔Transform and Lighting,多边形转换与光源处理〕T-Buffer〔T缓冲,3dfx V oodoo4的特效,包括全景反锯齿Full-scene Anti-Aliasing、动态模糊Motion Blur、焦点模糊Depth of Field Blur、柔和阴影Soft Shadows、柔和反射Soft Reflections〕TCA〔Twin Cache Architecture,双缓存结构〕Transparency〔透亮状成效〕Transformation〔三角形转换〕Trilinear Filtering〔三线性过滤〕Texture Modes,材质模式TMIPM: 〔Trilinear MIP Mapping三次线性MIP材质贴图〕UMA〔Unified Memory Architecture,统一内存架构〕Visualize Geometry Engine,可视化几何引擎Vertex Lighting〔顶点光源〕Vertical Interpolation〔垂直调变〕VIP〔Video Interface Port,视频接口〕ViRGE: 〔Video and Rendering Graphics Engine视频描写图形引擎〕V oxel〔V olume pixels,立体像素,Novalogic的技术〕VQTC〔Vector-Quantization Texture Compression,向量纹理压缩〕VSIS〔Video Signal Standard,视频信号标准〕v-sync〔同步刷新〕Z Buffer〔Z缓存〕5、音频3DPA〔3D Positional Audio,3D定位音频〕AC〔Audio Codec,音频多媒体数字信号编解码器〕Auxiliary Input〔辅助输入接口〕CS〔Channel Separation,声道分离〕DS3D〔DirectSound 3D Streams〕DSD〔Direct Stream Digital,直截了当数字信号流〕DSL〔Down Loadable Sample,可下载的取样音色〕DLS-2〔Downloadable Sounds Level 2,第二代可下载音色〕EAX〔Environmental Audio Extensions,环境音效扩展技术〕Extended Stereo〔扩展式立体声〕FM〔Frequency Modulation,频率调制〕FIR〔finite impulse response,有限推进响应〕FR〔Frequence Response,频率响应〕FSE〔Frequency Shifter Effect,频率转换成效〕HRTF〔Head Related Transfer Function,头部关联传输功能〕IID〔Interaural Intensity Difference,两侧声音强度差别〕IIR〔infinite impulse response,无限推进响应〕Interactive Around-Sound〔交互式围绕声〕Interactive 3D Audio〔交互式3D音效〕ITD〔Interaural Time Difference,两侧声音时刻延迟差别〕MIDI:〔Musical Instrument Digital Interface乐器数字接口〕NDA:〔non-DWORD-aligned ,非DWORD排列〕Raw PCM:〔Raw Pulse Code Modulated元脉码调制〕RMA:〔RealMedia Architecture实媒体架构〕RTSP: 〔Real Time Streaming Protocol实时流协议〕SACD〔Super Audio CD,超级音乐CD〕SNR〔Signal to Noise Ratio,信噪比〕S/PDIF〔Sony/Phillips Digital Interface,索尼/飞利普数字接口〕SRS: 〔Sound Retrieval System声音修复系统〕Surround Sound〔围绕立体声〕Super Intelligent Sound ASIC〔超级智能音频集成电路〕THD+N〔Total Harmonic Distortion plus Noise,总谐波失真加噪音〕QEM〔Qsound Environmental Modeling,Qsound环境建模扬声器组〕WG〔Wave Guide,波导合成〕WT〔Wave Table,波表合成〕6、RAM & ROMABP: 〔Address Bit Permuting,地址位序列改变〕ATC〔Access Time from Clock,时钟存取时刻〕BSRAM〔Burst pipelined synchronous static RAM,突发式管道同步静态储备器〕CAS〔Column Address Strobe,列地址操纵器〕CCT〔Clock Cycle Time,时钟周期〕DB: 〔Deep Buffer深度缓冲〕DDR SDRAM〔Double Date Rate,双数据率SDRAM〕DIL〔dual-in-line〕DIMM〔Dual In-line Memory Modules,双重内嵌式内存模块〕DRAM〔Dynamic Random Access Memory,动态随机储备器〕DRDRAM〔Direct RAMbus DRAM,直截了当RAMbus内存〕ECC〔Error Checking and Correction,错误检查修正〕EEPROM〔Electrically Erasable Programmable ROM,电擦写可编程只读储备器〕FM: 〔Flash Memory快闪储备器〕FMD ROM 〔Fluorescent Material Read Only Memory,荧光质只读储备器〕PIROM:〔Processor Information ROM,处理器信息ROM〕PLEDM: Phase-state Low Electron〔hole〕-number Drive MemoryQBM〔Quad Band Memory,四倍边带内存〕RAC〔Rambus Asic Cell,Rambus集成电路单元〕RAS〔Row Address Strobe,行地址操纵器〕RDRAM〔Rambus Direct RAM,直截了当型RambusRAM〕RIMM〔RAMBUS In-line Memory Modules,RAMBUS内嵌式内存模块〕SDR SDRAM〔Single Date Rate,单数据率SDRAM〕SGRAM〔synchronous graphics RAM,同步图形随机储存器〕SO-DIMM〔Small Outline Dual In-line Memory Modules,小型双重内嵌式内存模块〕SPD〔Serial Presence Detect,串行存在检查〕SRAM〔Static Random Access Memory,静态随机储备器〕SSTL-2〔Stub Series Terminated Logic-2〕TSOPs〔thin small outline packages,超小型封装〕USWV〔Uncacheable, Speculative, Write-Combining非缓冲随机混合写入〕VCMA〔Virtual Channel Memory architecture,虚拟通道内存结构〕7、磁盘AAT〔Average access time,平均存取时刻〕ABS〔Auto Balance System,自动平稳系统〕ASMO〔Advanced Storage Magneto-Optical,增强形光学储备器〕AST〔Average Seek time,平均寻道时刻〕ATA〔AT Attachment,AT扩展型〕ATOMM〔Advanced super Thin-layer and high-Output Metal Media,增强形超薄高速金属媒体〕bps〔bit per second,位/秒〕CAM〔Common Access Model,公共存取模型〕CSS〔Common Command Set,通用指令集〕DMA〔Direct Memory Access,直截了当内存存取〕DVD〔Digital Video Disk,数字视频光盘〕EIDE〔enhanced Integrated Drive Electronics,增强形电子集成驱动器〕FAT〔File Allocation Tables,文件分配表〕FDBM〔Fluid dynamic bearing motors,液态轴承马达〕FDC〔Floppy Disk Controller,软盘驱动器操纵装置〕FDD〔Floppy Disk Driver,软盘驱动器〕GMR〔giant magnetoresistive,巨型磁阻〕HDA〔head disk assembly,磁头集合〕HiFD〔high-capacity floppy disk,高容量软盘〕IDE〔Integrated Drive Electronics,电子集成驱动器〕LBA〔Logical Block Addressing,逻辑块寻址〕MBR〔Master Boot Record,主引导记录〕MTBF〔Mean Time Before Failure,平均故障时刻〕PIO〔Programmed Input Output,可编程输入输出模式〕PRML〔Partial Response Maximum Likelihood,最大可能部分反应,用于提高磁盘读写传输率〕RPM〔Rotation Per Minute,转/分〕RSD:〔Removable Storage Device移动式储备设备〕SCSI〔Small Computer System Interface,小型运算机系统接口〕SCMA:〔SCSI Configured Auto Magically,SCSI自动配置〕S.M.A.R.T.〔Self-Monitoring, Analysis and Reporting Technology,自动监测、分析和报告技术〕SPS〔Shock Protection System,抗震爱护系统〕STA〔SCSI Trade Association,SCSI同业公会〕Ultra DMA〔Ultra Direct Memory Access,超高速直截了当内存存取〕LVD〔Low V oltage Differential〕Seagate硬盘技术DiscWizard〔磁盘操纵软件〕DST〔Drive Self Test,磁盘自检程序〕SeaShield〔防静电防撞击外壳〕8、光驱ATAPI〔AT Attachment Packet Interface〕BCF〔Boot Catalog File,启动名目文件〕BIF〔Boot Image File,启动映像文件〕CDR〔CD Recordable,可记录光盘〕CD-ROM/XA〔CD-ROM eXtended Architecture,唯读光盘增强形架构〕CDRW〔CD-Rewritable,可重复刻录光盘〕CLV〔Constant Linear Velocity,恒定线速度〕DAE〔digital Audio Extraction,数据音频抓取〕DDSS〔Double Dynamic Suspension System,双悬浮动态减震系统〕DDSS II〔Double Dynamic Suspension System II,第二代双层动力悬吊系统〕PCA V〔Part Constant Angular Velocity,部分恒定角速度〕VCD〔Video CD,视频CD〕9、打印机AAS〔Automatic Area Seagment?〕dpi〔dot per inch,每英寸的打印像素〕ECP〔Extended Capabilities Port,延长能力端口〕EPP〔Enhanced Parallel Port,增强形平行接口〕IPP〔Internet Printing Protocol,因特网打印协议〕ppm〔paper per minute,页/分〕SPP〔Standard Parallel Port,标准并行口〕TET〔Text Enhanced Technology,文本增强技术〕USBDCDPD〔Universal Serial Bus Device Class Definition for Printing Devices,打印设备的通用串行总线级标准〕VD〔Variable Dot,变点式列印〕10、扫描仪TWAIN〔Toolkit Without An Interesting Name〕协议11、运算机公司Ali: Acer Lab〔宏棋实验室〕ASF: Applied Science FictionAMD: Advanced Micro Device〔超微半导体〕AMI: American Megatrends IncorporatedEAR〔Extreme Audio Reality〕HP: Hewlett-Packard,美国惠普公司IBM: International Business Machine,国际商业机器IDG〔International Data Group,国际数据集团〕IMS: International Meta SystemMLE:Microsoft Learning and Entertainment,微软教学与娱乐公司MS〔Microsoft,微软〕NAI: Network Associates Incorporation,前身为McAfee。
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STATIC AND DYNAMIC BRANCH PREDICTION USING NEURALNETWORKSMarius SBERA*, Lucian N. VINTAN**, Adrian FLOREA*** “S.C. Consultens Informationstechnik S.R.L.” Sibiu, ROMANIA, E-mail: sbmarius@** “Lucian Blaga” University of Sibiu, Computer Science Department, Sibiu, ROMANIAE-mail: vintan@jupiter.sibiu.ro, aflorea@vectra.sibiu.roAbstract: In this short paper we investigated a new static branch prediction technique. The main idea of this technique is to use a large body of different programs (benchmarks) to identify and infer common C program behaviour. Then, this knowledge is used to predict new “unseen” branches belonging to new programs. The common behaviour is represented as a set of static features of branches that are mapped using a neural network to the probability that the branch will be taken. In this way the predictor does not predict a program behaviour based on previous execution of the same program or based on some program profiles but uses the knowledge gathered from other programs (knowledge experience). Also we combined static and a dynamic neural branch predictor in order to investigate how much influences the static predictor the dynamic one.Key words: Architectures, Multiple Instruction Issue, Pipelining, Neural Branch Prediction, Neural Networks, Modeling and Simulation, Performance Evaluations1. IntroductionBranch prediction represents the process of correctly predicting the branch’s direction and target address before it is actually executed. High accuracy branch prediction is increasingly important in today’s wide-issue superscalar and/or deep pipeline processor architecture. Wide-issue computer architectures rely on predictable control flow and failure; to correctly predict a branch involves delays in evacuating the instructions from the wrong path of execution entered into the pipeline structures [7,8]. Statistically was proven that conditional branches are executed about every 7-8 instructions at average. Current wide-issue architectures can execute four or more independent instructions per cycle so a branch instruction is likely to be executed every two cycles or less. This means that branch prediction is crucial for processor performance. So in the example of the Alpha 21164 processor, about 12 instructions may have to be flushed on a misprediction. This translates to a severe performance penalty. Many approaches have been proposed to branch prediction, some of which mainly involve hardware (dynamic branch prediction) while others involve software (static branch prediction). Software methods usually cooperate with hardware methods. For example, some architecture have a “likely” bit into the instruction opcode that can be set by the compiler if a branch is determined to be likely taken. Recently there is a big interest in hybrid branch prediction where it is exploited the synergism between some different branch prediction schemes. Hence, a combination of basic schemes might – at the same cost –involve serious advantages. As an example, the recent microprocessor Alpha 21264 uses a large hybrid predictor [3]. This paper investigates neural static branch prediction as proposed in [1] but it goes further and links it with a dynamic neural branch prediction as stated in [5,8].2. Static Branch PredictionGood static branch predictions are invaluable information for compiler optimisation or performance estimation. Typically there are two general approaches for static branch prediction: profile-based predictions and program-based predictions [8]. Profile-based predictions use program profiles to determine the certain path executed frequency. This can be extremely successful in reducing the number of instructions executed between mispredicted branches but additional work is required on the part of the programmer togenerate the program profiles. Program-based branch prediction methods attempt to rely only on a program’s structure and to avoid programmer supplementary work. Some of these techniques use heuristics based on local knowledge that can be encoded in the architecture. Other techniques rely on applying heuristics based on less program structure in an effort to predict branch behavior. The method described in this paper does not rely on such heuristics. Rather than using heuristics it uses a large body of different programs to identify and infer common behavior. Then, this knowledge is used to predict some new “unseen” programs. The common behavior is represented in this work as static features of branches that are mapped using a neural network to the probability that the branch will be taken. In this way the predictor does not predict a program behavior based on previous execution of the same program but uses the knowledge gathered from other programs.3. Useful Information for Program-based Branch PredictionOne of the first and most simple methods for branch prediction is called “backward-taken/forward-not-taken”(BTFNT). This technique relies on the statistical facts that backward branches are usually loop branches, and as such are likely to be taken. While simple, BTFNT is also quite successful. Using this technique we obtained in our experiments a static prediction accuracy rate of 57,83%. Applying other simple program-based heuristics information (branch opcode, operands, and characteristics of the branch successor blocks, knowledge about common programming idioms) can significantly improve the branch prediction accuracy over the simple BTFNT technique.The work presented in this paper does not use any of the heuristics stated above. Instead, a body of programs is used to extract common branch behavior that can be used to predict other branches. Every branch of those programs is processed and some static information is automatically extracted. The programs are then executed and the corresponding dynamic behavior is associated with each static element. Now we have accumulated a body of knowledge about the relation between the static program elements and it’s dynamic behavior. This body of knowledge can then be used at a later time to predict the behavior of instructions with similar static features from programs not yet “seen” (i.e. processed). However the prediction process is yet not complete. The static prediction is not linked with real time execution unless there is no connection with dynamic prediction (likely bits). Of course, compilers or integrated schedulers may still use static prediction alone in order to schedule the static program [9]. So we further generate such bits and use them as inputs into a dynamic predictor.The only program elements that we are interested in are the conditional branches. Other kinds of branches are quite trivial from the direction prediction point of view. However, there are some branches that remain very interesting from the target prediction challenge. For each conditional branch in the program a set of static useful features are recorded (Table 1). Some of these features are properties of the branch instruction itself (the branch opcode, branch direction, etc.), others are properties of the previous branch, while others are properties of the basic blocks that follow on the two program paths after the current branch. We mention that characteristics no. 5, 11 and 12 belonging to Table 1, are new useful characteristics proposed by the authors of this work, completely different by those stated in [1]. Of course, finding new relevant prediction features might be a very important open problem in our opinion.Table 1. The Static Features SetIndex Feature Name Feature Description1Branch opcode The opcode of the branch instruction2Branch direction The branch direction (forward or backward)3Loop header The basic block is a loop header4RB type RB is a register or an immediate constant5RB register index or constant The RB register index or the LSB bits from the immediate constant Features of the taken successor of the branch6Succ. Type The branch type from the successor basic block7Succ. Loopheader The successor basic block is a loop header8Succ. Backedge The edge getting to the successor is a back edge9Succ. Exitedge The edge getting to the successor is a loop exit edge10Suc. Call The successor basic block contains a procedure call11Succ. Store The successor basic block contains at least one store instruction 12Succ. Load The successor basic block contains at least one load instruction Features of the not taken successor of the branch13-19As features 6 to 124. The Statically Neural PredictorOur goal into this work is to predict the branch probability for a particular branch from its associated static features. The prediction rate obtained is then used as input into a dynamic branch predictor besides other inputs. Also the static prediction will be used as an important information in the static scheduler (as an example, for the well-known trace scheduling optimization technique).The static features of a branch are mapped to a probability that the branch will be taken. A simple way to do this is using a feed-forward neural network. The neural network uses as input a numerical vector and maps it to a probability. Here, the numerical input vector is binary coded and consists of the feature values belonging to the static set (Table 1) and the output is a scalar indicating the branch’s probability.Similarly, the same type of feed-forward neural network, but another input vector, is used to predict into the dynamic predictor. This time the input vector consists of binary representation of the branch address concatenated with the transformed prediction obtained from the static predictor (the static prediction obtained may be a binary value taken/not taken or a “percentage value”), and, possible other useful dynamic information [6]. The output is represented by one bit value (‘1’for taken and ‘0’for not taken). Figure 1. A general picture of the two neural predictors working togetherBefore this ensemble of predictors (static and dynamic) starting to will work we have to record a body of knowledge into the static predictor’s neural network. So, a set of programs (benchmarks) is used to train the static neural network. The static features – automatically extracted - for every conditional branch belonging to these programs are mapped using the neural network to the probability that the branch will be taken. The output probability itself is obtained after running those programs and recording statistical information about each branch’s dynamical behavior. The process is reiterated until the difference between the output of the network and the statistical information gathered drops under a certain value. After the process ends we may say that we have recorded into the neural network weights a body of knowledge about mapping static features of branches to the probability that the branch will be taken. The static predictor may now be used to predict branches belonging to new unprocessed programs and the outcome is used to influence the dynamic predictor (there are several levels of influence, see further). The outcome of the static predictor is transformed according to the following rule: scalars greater than 0.5 are mapped to ‘1’and less than 0.5 to ‘0’. This partial result is then concatenated with the branch’s address and set as input into the dynamic predictor. To evaluate the influence of this “likely bit” upon the dynamic prediction it is applied in various levels (multiplied horizontally as number of occurrence, obtaining more that one “likely bit”, all identical) as stated by the “Static Influence” parameter in our developed software dedicated program. The neural networks used in this work in order to map static features to a branch taken probability and to dynamically predict a branch outcome, were feed-forward kinds of networks. An artificial neural network is composed from processing units or neurons. Each processing unit outputs a value known as its activity. Connections or weights links processing units are indicating the direction of activity flow. The connection pattern that links the units separates one type of neural network from another. Basically there are two types of neural nets: feed-forward nets (which have no loops) and recurrent nets (in which loops occurs because of feedback connections). Both neural networks used during this work falls into the first category, being thus feed-forward nets. In this kind of networks the activity flows from input to output. The activities of the hidden layer, denoted h i, and respectively of the output layer y k, are computed based on the very well-known formulas, as [2]:∑+⋅=ijiijjaxwfh)(eqn (1)and∑+⋅=jkjjkkbhvfy)(,eqn (2)The activation function used into this work is a fairly sigmoid standard one:uef−+=11eqn (3)The adaptive behavior of the neural network is achieved by setting its parameters, the weights w ij and v jk and biases a j and b k. The well-known back propagation algorithm based on the square root error (E) computation sets these parameters:∑−=kkk tyE2)(eqn (4)5. Experimental Methodology and Obtained ResultsTo quantify the performance of this static prediction scheme, during our experiments, we have used a set of 8 programs called globally the Stanford HSA (Hatfield Superscalar Architecture) benchmarks suite. The benchmark’s HSA assembler sources were used for the static analyze and static feature extraction while the statistics of the dynamic execution were extracted from the traces of the same benchmarks. These traces were obtained by running the Stanford benchmarks into an instruction-level simulator special dedicated to the HSA processor. The HSA is a high-performance multiple-instruction-issue architecture developed to exploit instruction-level parallelism through static instruction scheduling [6,7].To collect a body of knowledge only 7 (of the total of 8) programs are used. From the sources of these 7 programs the static feature sets are automatically extracted and a statistical evaluation is performed on the corresponding traces. Then, the neural net belonging to the static predictor is used to map these static feature sets to the probability that the branch will be taken or not taken. This probability is extracted from the statistical information earlier gathered. Now taking into account that the body of needed knowledge is available, we may proceed in predicting programs yet “unseen” by our neural static predictor. In order to do this, we used the eighth program from the HSA benchmarks suite, left out until now, which we further call it the test benchmark. Because every program from this suite covers just a particular domain (puzzle games, recursion programs, matrix problems, etc.), each experiment is executed 8-th times and every time is left out another program (as a test program). Finally an average of the eight results is computed. The neural net’s configuration presented in the results charts are represented as: [number of input units] x [number of hidden units] x [number of output units]. We have performed two distinct kinds of experiments. In the first one we predicted using just the first (static) neural network. The static prediction extracted from this first neural network output is compared with the perfect static prediction. By “perfect static prediction” we actually mean the asymptotic limit to which we could target out the maximum static prediction accuracy, considering an ideal “Oracle”processing model. In order to achieve this we considered the dynamic trace from which we extracted statistical information and for each benchmark we calculated its associated perfect static prediction (P.S.P.) using our following formula:∑∑===LkkLk kkNBRNBRMBRPSP112...eqn (5),where:NBR k – total number of dynamic instances of a branch belonging to a certain benchmarkNBR k = NT k (no. of taken instances for the k branch) + NNT k (no. of not taken instances for the k branch)MBR k = Max( NT k, NNT k )L = total number of static branches belonging to a certain benchmarkNow we will define the (imperfect) static prediction (S.P.) as the following formula:∑∑==−+=LkkkkkLkkkkNBRRNBRNNTRNBRNTPS1212))1(**(.. eqn (6),where:R k – the output of the static neural network predictor for the branch k (1 – taken; 0-not taken). It’s mathematical obviously that: P.S.P. ≥ S.P. eqn (7) Prediction results obtained from the hybrid predictor (static + dynamic) are computed using the same formulas but while in formula (5) the input indices (MBR k) are “coming”from trace statistics, in this case these indices are gathered from the output of the first static neural network (R k). Also, the branch’s PC constitutes an input parameter for the neural dynamic branch predictor.For the first type of experiments we have considered two ways of representing the output: as binary output (1 = taken, 0 = not taken) and as percentages of branch taken behavior (measured probability). Figure 2 and 3 presents the static prediction accuracies (P.S.P. and S.P.) according to these previous described two distinct conditions.BubbleMatrixPermPuzzleQueensSortTowerTreeAvg.Figure 2. Static prediction results with binary outputBubbleMatrixPermPuzzleQueensSortTow erTreeAvg.Figure 3. Static prediction results with percentage outputThe second type of experiments consists in measuring the Static Influence (SI) of the static neural predictor regarded to the dynamic neural predictor’s behavior. More precisely, we added supplementary outputs belonging to the static network as entries for the dynamic neural predictor. The number of these supplementary inputs – having each of them the same associated value (probability) - is noted here with SI.The influence of SI parameter is presented in Figure 4(SI=2 and 4). Related to Figure 4, it means that the dynamic predictor’s totally number of input cells is (8+SI) respectively (10+SI). A bigger number of inputsunits derived from the static predictor means,theoretically, a bigger influence related to the neural dynamic predictor’s accuracy. The neural network configurations are represented as:q the configuration for the static net as: [number of input units] x [number of hidden units] x [number of output units]q the configuration for the dynamic net as: [number of input units] x [number of hidden units] x [1 outputunit]7075808529x31x18x10x129x33x18x10x129x35x18x10x129x31x110x12x129x33x110x12x129x35x110x12x1Figure 4. Hybrid (static + dynamic) prediction results influenced by a binary static prediction resolution6. Conclusions and Further WorkThe method investigated through this paper has the advantages over the existing static prediction methods that rather than being based on heuristics it is based on general program structures and behaviour (experience).Another advantage is that no supplementary time orprogrammer intervention is required to generate profiling information.Our simulations focused on the neural static prediction (figures 2 and 3) suggests that predicting binary results (taken / not taken) is less efficient than generating percentage results (prediction accuracies).The best average result performed for the binary output static prediction was at average 66,21% while withpercentage output it reached 68.32%. Both these static prediction results must be compared with the perfect static prediction that was about 82.16%. The neural net’s percentage outputs, even if are harder to be assimilated in the learning phase, contains more information than a simple binary prediction. Also based on our simulations the influence (through simulated likely bits) of static predictor upon a neural dynamic predictor is minimal. The best results obtained were 80.34% for a SI=2 and respectively 81.1% for SI=4, both using the same hybrid configuration (29x33x1, 8x10x1). Figure 4 exposes that as static influence grows for smaller neural nets configurations the result is also positively influenced, but on bigger neural nets the static influence becomes negative by expanding too much the input layer of the net and being harder to assimilate by the neural net.As an immediately further work we are intending to develop also other neural nets topologies, including recurrent neural nets (NN). These NN contain connections from the hidden cells to the context cells in order to store the state of the net on the previous step of time. Some recent research prove that some recurrent nets with asymmetric connections or partially recurrent nets, perform sequence recognition far better than other (simple recurrent) NN. Also we intend to use the SPEC’2000 benchmarks that is known that are more predictable than our used benchmarks. AcknowledgmentsThis work was partially supported by two research grants (CNCSIS 8/2001 and ANSTI CG 12/05.06.2001) offered by Romanian Ministry of Education and Research (M.E.C.). Our gratitude to Professor Gordon B. Steven and Dr. Colin Egan from the University of Hertfordshire, England, for providing HSA Stanford benchmarks and for their useful helps. Also we like to thank Professor Theo Ungerer from Karlsruhe University, Germany, for a very useful professional discussion in January 2001.References[1] Calder, B., Grunwald, D., and Lindsay, D. - Corpus-based Static Branch Prediction, SIGPLAN Notices, June 1995, pp79-92[2] S.I. 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