PT_Unit_4(primetime)

n
4-4
Check for design rule and timing violations in the design
report_constraint -all_violators
n
To handle large problems use a divide and conquer method:
Simultaneous min/max Timing Models Advantages of analysis
Case analysis Creating Quick Timing Mode and its Application
On-Chip Variation Creating Quick Timing Mode and its Application
Use group_path to group paths of interest
4-5
group_path -name INPUTS -from [all_inputs] group_path -name OUTPUTS -to [all_outputs] report_constraint -all_violators report_timing -max_paths 5 -path short report_timing -group CLK
Agenda: Day One
DAY 1
4-1
Unit
Topic
Lab
1
Introduction to Static Timing Analysis
2
Advanced Clock Constraints
3
Timing Exceptions Advanced Timing Analysis Techniques
Simultaneous Min-Max Analysis
4-6
Using user defined path groups Creating Quick Timing Mode and its Application
Simultaneous min-max Timing Models Advantages of analysis
D Q
FF1
Organize paths for reports
A CLK
D Q
FF2
Байду номын сангаас
Z
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
Grouping Technique: Use group_path
l
l
n
With logic transitions:
l
PrimeTime uses only the specified transitions when timing through that particular cell
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
l
Divide paths into smaller groups with common specifications, analysis issues or solutions
An example of grouping timing paths
1 2 3
Input ports to registers Register to register Register to output ports
l
Use specific SDF, operating conditions and technology libraries for min and max calculations
n
Min-max values can also be specified for:
l l l l
Input and output delays Wire load models Clock attributes Driving cell and loads
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
What is Min-Max Analysis?
n
4-7
You can perform setup and hold analysis simultaneously
4
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
Unit Objectives
After completing this unit you should be able to:
n
4-2
State the command to create user defined path groups State 3 commands which can be used for simultaneous min-max analysis State 2 commands useful for case analysis State the command used for bottleneck analysis State the steps for an efficient static timing analysis methodology
Case analysis Creating Quick Timing Mode and its Application
On-Chip Variation Creating Quick Timing Mode and its Application
An efficient STA methodology Models Advantages of Timing
Advanced Timing Analysis Techniques PrimeTime Workshop
Synopsys 37038-000-S13
Case Analysis
4-9
Using user defined path groups Creating Quick Timing Mode and its Application
n
In this example, PrimeTime will:
l l
Calculate min delays for hold time analysis using cba_core_min Calculate max delays for setup time analysis using cba_core_max
4-8
pt_shell> set_operating_conditions -analysis_type bc_wc \ -min MIN -max MAX
… .or… .
pt_shell> read_sdf -analysis_type bc_wc ba_design.sdf
n
The read_min_max_lib command:
n
4-10
Case analysis allows you to perform timing analysis using logic constants or logic transitions on ports or pins With logic constants:
l
n
PrimeTime propagates the constant forward through the netlist PrimeTime automatically disables appropriate timing arcs based on the logic constant By default, constants do not propagate across sequential cells
Example Using Case Analysis
a
test_scan_in
4-11
D TI TE CP
Q
d e
b clk
test_scan_enable
D TI TE CP
Q
Setup and hold constraints disabled from clock to test input pin
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
How Do You Setup Min-Max Analysis?
pt_shell> read_min_max_lib -min cba_core_min.db \ -max cba_core_max.db -name min_max.db pt_shell> set link_path “* min_max.db” ; link_design
An efficient STA methodology Models Advantages of Timing
Synopsys 37038-000-S13
Advanced Timing Analysis Techniques PrimeTime Workshop
What is Case Analysis?
4-3
Simultaneous min-max Timing Models Advantages of analysis