LTC1562-2[1]
LTC3862-2管脚
Vin
主电源输入
21
RUN
运行控制输入，当引脚电压大于1.22v，芯片工作
22
SENSE1+
同SENSE2+
23
SENSE1-
同SENSE2-
24
3V8
内部LDO的3.8V输出。
电流比较器负极输入
15
NC
悬空
16
GATE2
门极驱动信号输出，CH2
17
PGND
电源地
18
GATE1
门极驱动信号输出，CH1。Ltc3862-2提供参考PGND 10V的门极驱动来驱动高电压MOSFET。GATE1的额定绝对最大电压在-0.3v到11v之间。
19
INTVCC
内部LDO(低差压线性稳压器)的10v输出。一个我低ESR 4.7uF陶瓷旁路电容应连接在INTVcc和PGND之间，尽量靠近IC。
8
FB
误差放大器的输入。通过一个电阻分压网络连接到Vout设置输出电压。
9
SGND
信号地
10
CLKOUT
主芯片同步时钟输出
11
SYNC
芯片同步时钟输入。在闭环操作中，SYNC输入波形的上升沿与GATE1上升沿一致。
12
PLLFLTR
PLL低通滤波输入。
13
SENSE2+
电流比较器正极输入
14
SENSE2-
13sense2电流比较器正极输入14sense2电流比较器负极输入15nc悬空16gate2门极驱动信号输出ch217pgnd电源地18gate1门极驱动信号输出ch1ltc38622提供参pgnd10v的门极驱动来驱动高电压mosfetgate1的额定绝对最大电压在03v到11v之间
LTC2941 LTC2942 电池气体计测试电路说明书
DC1496A-A1dc1496fD ESCRIPTION Battery Gas Gauge with I 2C Interface [and 14-Bit ADC(DC1496A-B)]Demonstration circuit 1496A-A (Figure 1) features the L TC ®2941. Demonstration circuit 1496A-B features the L TC2942. Both devices measure battery charge state in handheld PC and portable product applications. The operating range is perfectly suited for single cell Li-Ion batteries. A precision analog coulomb counter integrates current through a sense resistor between the battery’s positive terminal and the load or charger . The L TC2942 adds battery voltage and on-chip temperature measurement with an internal 14-bit No Latency ΔΣ™ ADC. The three measured quantities (charge, voltage and temperature) are stored in internal registers accessible via the onboard SMBus/I 2C interface.The L TC2941 has programmable high and low thresholds for accumulated charge. The L TC2942 has programmable high and low thresholds for all three measured quantities. If a programmed threshold is exceeded, the device reports an alert using either the SMBus alert protocol or by setting a fl ag in the internal status register .L , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and No Latency ΔΣ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.The L TC2941 and L TC2942 require only a single low value sense resistor to set the measured current range. The default value assembled on the DC1496 is 100mΩ for a maximum current measurement of 500mA. Both parts have a software-confi gurable charge complete/alert pin. When the pin is set for charge complete, a jumper con-nects the pushbutton which simulates a logic high input to indicate a full battery. When the pin is confi gured for alert, the same jumper is used to connect a red LED that indicates an alert is present.The DC1496A-A/B is a part of the QuikEval system for quick evaluation with a host controller through a PC.Design fi les for this circuit board are available at http://www.linear.com/demo.Figure 1. DC1496A-A/B2dc1496fDEMO MANUAL DC1496A-A/B QUICK START PROCEDUREDemonstration circuit 1496A is easy to set up to evaluate the performance of the L TC2941/L TC2942. Refer to Figure 2 for proper measurement equipment setup and follow the procedure below.1. C onnect a 1-cell Li-I on battery across V_BAT and GND.2. Connect a load across V_CHRG/LD and GND for battery discharge measurement. Up to 500mA supplied from the battery can be measured with the board default 100mΩ sense resistor . Use SENSE + and SENSE – test points to read voltage across the sense resistor .3. Connect a 2.7V to 5.5V battery charger supply across V_CHRG/LD and GND. Up to 500mA supplied to the battery can be measured with the board default 100mΩ sense resistor . Use SENSE + and SENSE – test points to read voltage across the sense resistor .4. Connect a DC590 to 14-pin connector J1 for evaluation with QuikEval, or connect a host controller I 2C bus to the SDA, SCL and GND test turrets.5. Set JP1 to QuikEval if a DC590 is present. Otherwise set JP1 to Bat/Chrg for bus pull-up to the battery, or fl oat JP1 and supply a bus pull-up voltage to VP .6. Read and write to the L TC2941/L TC2942 through I 2C.7. Through I 2C, configure the AL /CC pin. Set JP2 accordingly.8 f AL /CC is set for charge complete, use pushbutton switch S1 to simulate a logic high from a controller to indicate a fully charged battery.Figure 2. DC1496A-A/B Basic Setup3dc1496fDEMO MANUAL DC1496A-A/BQuikEval INTERFACEThe DC1496A-A/B can be connected to a DC590 and used with the QuikEval software. The DC590 connects to a PC through USB. QuikEval automatically detects the demo board and brings up the L TC2941/L TC2942 evaluation software interface (Figure 3). Compact and Detailed FormWhen the interface is brought up, a compact form is fi rst shown with a display for the accumulated charge register (ACR), voltage ADC and temperature ADC. To expand the form for a more detailed display of the L TC2941/L TC2942 registers and board confi gurations, click on Detail. To go back to the compact form, click on Hide.Start/RefreshClick on Start to begin a polling routine that refreshes the interface every 1 second. Click on Stop to halt the poll-ing. For a single update, click on Refresh. Each refresh scans through the internal I 2C registers and updates the respective displays.L TC2941 and L TC2942 DisplayOn a refresh or poll, the software reads Status bit A[7] to determine communication with an L TC2941 or L TC2942. When an L TC2941 is detected, the voltage and temperature ADC and threshold displays are not shown. Control bits B[7:6] confi gure VBAT Alert for the L TC2941 and ADC Mode for the L TC2942.ACR DisplayThe data in the ACR (registers C and D) is displayed in one of three selected formats: Counter in coulombs, Counter in mA • hour , battery gas gauge in mA • hour , and battery gas gauge in charge percentage of battery. The two gas gauge displays correspond to the battery gas gauge full battery confi guration set in the detailed form.Voltage and Temperature ADC (L TC2942)Data from the Voltage ADC (registers I and J) and the Temperature ADC (registers M and N) is displayed here in Volts and Celsius.Figure 3. L TC2941/LTC2942 QuikEval InterfaceDEMO MANUAL DC1496A-A/B QuikEval INTERFACEAddress/I2C StatusThe write address for the L TC2941/L TC2942 is C8h and the read address is C9h. The alert response address (ARA) is 19h. If an error occurs while reading from the L TC2941/ L TC2942, the I2C status will read as an error. Otherwise, the status is good. If the L TC2941/L TC2942 AL/CC pin is set for alert mode and an alert has been latched, the device will pull down this pin. Click on ARA to send out an ARA on to the bus lines and the device will respond with its address. The Alert pin will then be cleared if the alert is no longer present.StatusThe individual status bits A[0:7] and their states are shown here. A red indicator next to bits A[0:5] indicates the re-spective alert is currently present and will latch the Alert pin if confi gured for alert. Bit A[7] shows if an L TC2941 or L TC2942 is detected.Sense ResistorEnter here the sense resistor value used in the application. The default for the DC1496A-A/B is a 100mΩ sense resis-tor. Check L TC2941-1/L TC2942-1 if one of these devices is used in place of the default IC. This sets the sense resistor value to 50mΩ, the value of the internal sense resistor in these devices. The sense resistor can only be changed when not polling. The software only accepts sense resis-tors between 0.1mΩ to 5Ω.Battery Gas GaugeThe battery capacity in the application is entered here. The ACR full scale (FFFFh) is set to this value and affects the two Gas Gauge ACR display options. Instead of counting up from 0 as in the Coulomb Counters, the Gas Gauge is used to count down from a full battery. The battery capacity can only be entered when not polling. The data in the ACR when a battery should be empty is calculated based off of R SENSE, and pre-scaler M, and displayed in hexadecimal below the ACR full scale.ControlConfi gurations done in the Control section write to the Control register (register B). For the L TC2941, the Control bits B[7:6] enables a battery monitor to one of three set voltage thresholds (2.8V, 2.9V, or 3V) or disables this battery voltage alert. The ADC mode with the L TC2942 is default to Sleep where both Voltage and Temperature ADCs (L TC2942) are disabled. Setting ADC Mode to Automatic Mode enables full-time the Voltage and Temperature ADC. Selecting Manual Voltage or Temperature mode enables the respective ADC once and returns the ADC to Sleep mode.Select a pre-scaler M value to scale the ACR according to battery capacity and maximum current. Changing the pre-scaler will halt the poll. A calculator tool is provided in the tool bar under Tools to assist in calculating a pre-scaler value and sense resistor (Figure 4).The AL#/CC pin can be confi gured for Alert mode, Charge Complete mode, or disabled. Select the corresponding settings on the DC1496A-A/B jumper J2.The Shutdown Analog Section is checked to disable the Analog portion of the L TC2941/42 and set the device in a low current state.Register Read/WriteData in the internal registers of the L TC2941/L TC2942 is displayed here in hexadecimal or appropriate units. Data can also be entered and written to the write registers. Enter data to be written in hexadecimal, or select Unit and enter data in decimal form. Data in decimal scale is auto corrected if the maximum or minimum full scale is exceeded. Select the ACR display in Counter (Coulombs) to be able to write to the ACR and charge thresholds in Coulombs, or select Counter (mAh) to be able to write to the ACR and charge thresholds in mA • hour. Voltage and Temperature High thresholds are rounded down in the calculations to the nearest lower count, while the low thresholds are rounded up to nearest higher count.4dc1496f5dc1496fDEMO MANUAL DC1496A-A/BSwitching back and forth between Hex and Unit can be used as a conversion tool.The LSB value for the 16-bit ACR and charge thresholds is displayed on the bottom. This value is adjusted with the sense resistor and pre-scaler M. The units are in mAh or mC depending on the selected ACR display. Shown for the L TC2942 is the LSB for the 14-bit voltage ADC, 10-bit temperature ADC, and 8-bit high and low thresholds for voltage and temperature.Calculator ToolA calculator tool is available in the tool bar options under Tools. In this calculator (Figure 4), enter the maximum cur-rent passed through the sense and the maximum battery capacity. Click on Calculate to calculate a recommended sense resistor and pre-scaler (M) value. The display shows the battery capacity in comparison to ACR full scale and provides an LSB value in mAh. Also shown is the recom-mended equation to use to determine an appropriate sense resistor as a function of the maximum battery charge and maximum current.Figure 4. L TC2941/L TC2942 Pre-Scaler and Sense Resistor CalculatorQuikEval INTERFACEDEMO MANUAL DC1496A-A/BPARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURE/PART NUMBER12C1, C2CAP., CHIP X7R, 0.1μF, 25V, 0603AVX, 06033C104KAT2A24E1-E4TURRET, Test Point 0.094"MILL-MAX, 2501-2-00-80-00-00-07-035E5-E9TURRET, Test Point 0.064"MILL-MAX, 2308-241E10, E11TURRET, Test Point 0.037"MILL-MAX, 2309-150TP1, TP2(SMT Pads Only)62JP1, JP2HEADER, 3Pin 1 Row 0.079CC SAMTEC, TMM-103-02-L-S72for (JP1, JP2)SHUNT, 0.079" Center SAMTEC, 2SN-BK-G81J1HEADERS, Vertical Dual 2X7 0.079CC MOLEX, 87831-142091D1LED, RED, LIGHT EMITTING DIODES PANASONIC, LN1251CTR101R1RES., CHIP, 0.1Ω, 1/8W, 1%, 1206IRC, LRC-LR1206LF-01-R100-F113R6, R7, R8RES., CHIP, 5.10k, 1%, 0603VISHAY, CRCW06035K10FKEA123R2, R3, R4RES., CHIP, 10k, 5%, 0603VISHAY, CRCW060310K0JNEA131R5RES., CHIP, 1k, 5%, 0603VISHAY, CRCW06031K00JNEA141R9RES., CHIP, 100k, 5%, 0603VISHAY, CRCW0603100KJNEA151S1SWITCH, SMT Pushbutton PANASONIC, EVQPE105K161U2I.C., Serial EEPROM TSSOP8MICROCHIP, 24LC025-I/ST171for (J1)CABLE ASSY., 8" STRIP LINEAR RIBBON CABLE CA-24406dc1496f7dc1496fDEMO MANUAL DC1496A-A/BSCHEMATIC DIAGRAM8dc1496fDEMO MANUAL DC1496A-A/B Silkscreen TopComponent SideInner Layer 2PCB LAYOUT AND FILM9dc1496fDEMO MANUAL DC1496A-A/BI nformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.PCB LAYOUT AND FILMInner Layer 3Solder SideSilkScreen Bottom10dc1496f DEMO MANUAL DC1496A-A/BLinear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORA TION 2010LT 0510 • PRINTED IN USADEMONSTRATION BOARD IMPORTANT NOTICELinear Technology Corporation (L TC) provides the enclosed product(s) under the following AS IS conditions:This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONL Y and is not provided by L TC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union direc-tive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT , SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.The user assumes all responsibility and liability for proper and safe handling of the goods. Further , the user releases L TC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).No License is granted under any patent right or other intellectual property whatsoever. L TC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.L TC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive .Please read the DEMO BOARD manual prior to handling the product . Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged .This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a L TC applica-tion engineer .Mailing Address:Linear Technology1630 McCarthy Blvd.Milpitas, CA 95035Copyright © 2004, Linear Technology CorporationDC1496A-A。
基于LTC1562-2芯片的声纳高频带通滤波器设计
ＳＨ Ｉ Ｃｈｕ ｎｈ ｕａ
（ Ｓ ｈ ｉ ｐ Ａｕ ｔ ｏ ｍａ ｔ ｉ ｏ ｎ Ｂｒ ａ ｎ ｃ ｈ，Ｓ ｈ ａ ｎ ｇ ｈ ａ ｉ Ｓ ｈ ｉ ｐ＆ Ｓ ｈ ｉ ｐ ｐ ｉ ｎ ｇ Ｒｅ ｓ ｅ ａ ｒ ｃ ｈ Ｉ ｎ ｓ ｔ ｉ ｔ ｕ ｔ ｅ ，Ｓ ｈ ａ ｎ ｇ ｈ ａ ｉ ２ ０ ０ １ ３ ５，Ｃｈ ｉ ｎ ａ ）
ｃ ｙ ｏ ｆ ２ ０ ０ ｋＨ ｚ ｉ ｓ ｄｅ ｓ ｉ ｇ ｎｅ ｄ ａ ｎｄ ｔ ｅ ｓ ｔ ｅ ｄ．
Ｋｅ ｙ ｗｏ ｒ ｄ ｓ ：ｂ ａ ｎ ｄ — ｐ ａ ｓ ｓ ｆ ｉ ｌ ｔ ｅ ｒ ；ＬＴＣ１ ５ ６ ２ — ２ ；Ｂ ｕ ｔ ｔ ｅ ｒ ｗｏ ｒ ｔ ｈ；ｓ ｏ ｎ ａ ｒ
只有 １ ５ ０ ｋ Ｈｚ ， 无法 满 足 设 计 要 求 。在 对 多 家 厂 商 滤 波 芯 片 的 选 型 进 行 比较 后 ， 选 择使用 Ｌ ｉ ｎ ｅ ａ ｒ 公 司 的
Ｌ Ｔ Ｃ １ ５ ６ ２ — ２ 芯 片作 为 ２ ０ ０ ｋ Ｈｚ 滤 波器 芯片 。Ｌ Ｔ Ｃ１ ５ ６ ２ ～ ２芯 片能满 足设 计 中心频 率 为 ２ ０ ０ ｋ Ｈｚ的要 求 ， 功 能
（ 上 海船 舶运 输科 学研 究所 舰 船 自动化 分 所 ， 上海 ２ ０ ０ １ ３ ５ ）
摘
要： 在声纳接收机 中， 滤 波 器 是 一 个 非 常 重 要 的组 成 部 分 ， 其 性 能 的 好 坏 直 接 影 响 接 收 信 号 处 理 的 质 量 。采 用
Ｌ Ｔ Ｃ １ ５ ６ ２ － ２芯 片 代 替 Ｌ Ｔ Ｃ １ ５ ６ ２芯 片 ， 以Ｌ ｉ ｎ ｅ ａ ｒ 公 司的仿真软件 Ｌ Ｔ ｓ ｐ ｉ ｃ ｅ ｌ Ｖ和 Ｆ ｉ ｌ ｔ ｅ ｒ Ｃ ＡＤ为 辅 助 工 具 ， 结合理论计 算 。测 试 结 果 表 明 ， 所设 计 中 心 频 率 为 ２ ０ ０ ｋ Ｈｚ 的 巴特 沃 斯 型 带 通 滤 波 器 可满 足 某 型 声 纳 接 收 滤 波 电路 的 使 用 要 求， 并 根据 仿 真 和 计 算 结 果 进 行 了实 际 电路 测 试 。 关 键 词 ：带通 滤 波 器 ； Ｌ Ｔ Ｃ １ ５ ６ ２ — ２芯 片 ； 巴特 沃 斯 ； 声 纳
LTC1232 精密电源监控模块说明书
123sn1232 1232fasSYMBOL PARAMETER CONDITIONSMINTYP MAX UNITSV CC Supply Voltage● 4.555.5V V IH ST and PB RST Input High Level ●2V CC +0.3V V ILST and PB RST Input Low Level●–0.30.8VDC ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MINTYP MAX UNITS I IL Input Leakage (Note 3)●–11µA I OH Output Current at 2.4V (Note 5)●–1–13mA I OL Output Current at 0.4V (Note 5)●26mAI CC Supply Current (Note 4)●0.52mA V CCTP V CC Trip Point TOL = GND ● 4.5 4.62 4.74 V V CCTP V CC Trip PointTOL = V CC●4.254.37 4.49 V V HYS V CC Trip Point Hysteresis 40mV V RSTRST Output Voltage at V CC = 1VI SINK = 10µA4200mVThe ● denotes the specifications which applyover the full operating temperature. V CC = full operating range.The ● denotes the specifications which apply over the full operatingtemperature. V CC = full operating range.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS t PB PB RST = V IL ●40ms t RST RESET Active Time ●2506101000ms t ST ST Pulse Width●20ns t RPD V CC Detect to RST and RST ●100ns t f V CC Slew Rate 4.75V–4.25V ●300µs t RPU V CC Detect to RST and RSTt R = 5µs●2506101000ms (Reset Active Time)t R V CC Slew Rate 4.25V–4.75V ●0nst TDST Pin Detect to RST and RST TD = GND ●60150250ms (Watchdog Time-Out Period)TD = Floating ●2506101000ms TD = V CC●50012002000ms C IN Input Capacitance 5pF C OUTOutput Capacitance5pFNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: All voltage values are with respect to GND.Note 3: The PB RST pin is internally pulled up to V CC with an internal impedance of 10k typical. The TD pin has internal bias current.Note 4: Measured with outputs open.Note 5: The RST pin is an open drain output.The ● denotes the specifications which apply over the full operating temperature.V CC = full operating range.AC CHARACTERISTICSRECO E D ED OPERATI G CO DITIO SU U U U WW456Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.7Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LW/TP 1002 1K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORA TION 19928。
LTC1569-7 低通滤波器商品说明书
LTC1569CS8-7#PBF LTC1569IS8-7#PBF LTC1569CS8-6#PBF.12LTC1569-7PARAMETER CONDITIONSMIN TYP MAX UNITS Filter GainV S = 5V, f CLK = 8.192MHz,f IN = 5120Hz = 0.02 • f CUTOFF q –0.100.000.10dB f CUTOFF = 256kHz, V IN = 2.5V P-P ,f IN = 51.2kHz = 0.2 • f CUTOFF q –0.25–0.15–0.05dB R EXT = 5k, Pin 5 Shorted to Pin 4f IN = 128kHz = 0.5 • f CUTOFF q –0.50–0.41–0.25dB f IN = 204.8kHz = 0.8 • f CUTOFFq –1.1–0.65–0.40dB f IN = 256kHz = f CUTOFF , LTC1569C q –5.7–3.8–2.3dB f IN = 256kHz = f CUTOFF , LTC1569I q –6.2–3.8–2.0dB f IN = 384kHz = 1.5 • f CUTOFF q –58–48dB f IN = 512kHz = 2 • f CUTOFF q –62–54dB f IN = 768kHz = 3 • f CUTOFFq –67–64dB V S = 2.7V, f CLK = 1MHz,f IN = 625Hz = 0.02 • f CUTOFFq –0.080.000.12dB f CUTOFF = 31.25kHz, V IN = 1V P-P ,f IN = 6.25kHz = 0.2 • f CUTOFF q –0.25–0.15–0.05dB Pin 6 Shorted to Pin 4, External Clock f IN = 15.625kHz = 0.5 • f CUTOFFq –0.50–0.40–0.30dB f IN = 25kHz = 0.8 • f CUTOFF q –0.75–0.65–0.50dB f IN = 31.25kHz = f CUTOFFq –3.3–3.15–3.0dB f IN = 46.875kHz = 1.5 • f CUTOFF q –57–52dB f IN = 62.5kHz = 2 • f CUTOFF q –60–54dB f IN = 93.75kHz = 3 • f CUTOFFq –66–58dB Filter PhaseV S = 2.7V, f CLK = 4MHz,f IN = 2500Hz = 0.02 • f CUTOFF –11Deg f CUTOFF = 125kHz, Pin 6 Shorted to f IN = 25kHz = 0.2 • f CUTOFF q –114–112–110Deg Pin 4, External Clockf IN = 62.5kHz = 0.5 • f CUTOFF q 788082Deg f IN = 100kHz = 0.8 • f CUTOFF q –85–83–81Deg f IN = 125kHz = f CUTOFFq155158161Deg f IN = 187.5kHz = 1.5 • f CUTOFF–95DegFilter Cutoff Accuracy R EXT = 10.24k from Pin 6 to Pin 7,125kHz ±1%when Self-Clocked V S = 3V, Pin 5 Shorted to Pin 4Filter Output DC SwingV S = 3V, Pin 3 = 1.11V2.1V P-P q1.9V P-P V S = 5V, Pin 3 = 2V3.9V P-P q3.7V P-P V S = ±5V8.6V P-P LTC1569C q 8.4V P-P LTC1569Iq8.0V P-PA U G WA W U W A R BSOLUTEXI TI S W U UPACKAGE/ORDER I FOR ATIO(Note 1)Total Supply Voltage................................................11V Power Dissipation..............................................500mW Operating TemperatureLTC1569C ...............................................0°C to 70°C LTC1569I............................................–40°C to 85°C Storage Temperature............................–65°C to 150°C Lead Temperature (Soldering, 10 sec)..................300°CThe q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C.V S = 3V (V + = 3V, V – = 0V), f CUTOFF = 128kHz, R LOAD = 10k unless otherwise specified.ELECTRICAL C C HARA TERISTICSConsult factory for Military grade parts.3LTC1569-7Output DC Offset R EXT = 10k, Pin 5 Shorted to Pin 4V S = 3V ±2±5mV (Note 2)V S = 5V ±6±12mV V S = ±5V ±15mV Output DC Offset DriftR EXT = 10k, Pin 5 Shorted to Pin 4V S = 3V –25µV/°C V S = 5V –25µV/°C V S = ±5V ±25µV/°CClock Pin Logic Thresholds V S = 3V Min Logical “1” 2.6V when Clocked ExternallyMax Logical “0”0.5V V S = 5V Min Logical “1” 4.0V Max Logical “0”0.5V V S = ±5VMin Logical “1” 4.0V Max Logical “0”0.5VPower Supply Current f CLK = 1.028MHz (10k from Pin 6 to Pin 7,V S = 3V68mA (Note 3)Pin 5 Open, ÷ 4), f CUTOFF = 32kHzq9mA V S = 5V79mA q10mA V S = 10V913mA q14mA f CLK = 4.096MHz (10k from Pin 6 to Pin 7,V S = 3V 9.5mA Pin 5 Shorted to Pin 4, ÷ 1), f CUTOFF = 128kHz q14mA f CLK = 8.192MHz (5k from Pin 6 to Pin 7,V S = 5V20mA Pin 5 Shorted to Pin 4, ÷ 1), f CUTOFF = 256kHzq30mA V S = 10V27mA q37mA Power Supply Voltage where Pin 5 Shorted to Pin 4, Note 3q3.74.2 4.6V Low Power Mode is Enabled Clock Feedthrough R EXT = 10k, Pin 5 Open 0.4mV RMS Wideband Noise Noise BW = DC to 2 • f CUTOFF 125µV RMSTHDf IN = 10kHz, 1.5V P-P74dBClock-to-Cutoff 32Frequency Ratio Max Clock Frequency V S = 3V 5MHz (Note 4)V S = 5V 9.6MHz V S = ±5V13MHz Min Clock Frequency 3V to ±5V, T A < 85°C 3kHz (Note 5)Input Frequency RangeAliased Components <–65dB 0.9 • f CLKHzThe q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C.V S = 3V (V + = 3V, V – = 0V), f CLK = 4.096MHz, f CUTOFF = 128kHz, R LOAD = 10k unless otherwise specified.ELECTRICAL C C HARA TERISTICSPARAMETER CONDITIONSMINTYP MAX UNITS Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.Note 2: DC offset is measured with respect to Pin 3.Note 3: There are several operating modes which reduce the supply current. For V S < 4V, relative to divide-by-1 mode, the current is typically reduced by 50% relative to V S = 5V. If the internal oscillator is used as the clock source and the divide-by-4 or divide-by-16 mode is enabled, the supply current is typically reduced by 60%,relative to divide-by-1 mode,independent of the value of V S .Note 4: The maximum clock frequency is arbitrarily defined as thefrequency at which the filter AC response exhibits >1dB of gain peaking.Note 5: The minimum clock frequency is arbitrarily defined as the frequecy at which the filter DC offset changes by more than 5mV.Note 6: Thermal resistance varies depending upon the amount of PC board metal attached to the device. θJA is specified for a 2500mm 2 test board covered with 2oz copper on both sides.4LTC1569-7TYPICAL PERFOR A CE CHARACTERISTICSU WTHD vs Input VoltageTHD vs Input FrequencyINPUT VOLTAGE (V P-P )12345T H D (d B )1569-7 G02–50–60–70–80–90INPUT FREQUENCY (kHz)201030507090406080100T H D (d B )1569-7 G01–68–70–72–74–76–78FREQUENCY (kHz)L O G M A G (10d B /D I V )10–901569-7 G03FREQUENCY (kHz)G A I N (d B )DELAY (µs)1–1–2–3–420191817161514131211101569-7 G04Gain vs FrequencyPassband Gain and Group Delayvs Frequencyf CUTOFF (kHz)1I S U P P L Y (m A )1010010001569-7 G05121110987654f CUTOFF (kHz)1IS U P P L Y (m A )1010010001569-7 G06232119171513119755V Supply Current3V Supply CurrentfCUTOFF (kHz)1I S U P P L Y (m A )1010010001569-7 G0735322926232017141185± 5V Supply CurrentLTC1569-756LTC1569-7reduced. This results in a 60% power savings with a single 5V supply.Table1. f CUTOFF vs R EXT , V S = 3V, T A = 25°C, Divide-by-1 ModeR EXT Typical f CUTOFFTypical Variation of f CUTOFF3844Ω320kHz ±3.0%5010Ω256kHz ±2.5%10k 128kHz ±1%20.18k 64kHz ±2.0%40.2k32kHz±3.5%The power reduction in the divide-by-4 and divide-by-16modes, however, effects the fundamental oscillator fre-quency. Hence, the effective divide ratio will be slightly different from 4:1 or 16:1 depending on V S , T A and R EXT .Typically this error is less than 1% (Figures 4 and 6).Self-Clocking OperationThe LTC1569-7 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor . The design is optimized for V S = 3V, f CUTOFF =128kHz, where the filter cutoff frequency error is typically <1% when a 0.1% external 10k resistor is used. With different resistor values and internal divider settings, the cutoff frequency can be accurately varied from 2kHz to 150kHz/300kHz (single 3V/5V supply). As shown in Figure 1, the divider is controlled by the DIV/CLK (Pin 5).Table 1 summarizes the cutoff frequency vs external resistor values for the divide-by-1 mode.In the divide-by-4 and divide-by-16 modes, the cutoff frequencies in Table 1 will be lowered by 4 and 16respectively. When the LTC1569-7 is in the divide-by-4and divide-by-16 modes the power is automaticallyAPPLICATIO S I FOR ATIO W UU U Figure 4. Typical Divide Ratio in the Divide-by-4 Mode, T A = 25°CFigure 3. Filter Cutoff vs Temperature,Divide-by-1 Mode, R EXT = 10kFigure 2. Filter Cutoff vs V SUPPLY,Divide-by-1 Mode, T A = 25°CFigure 1V SUPPLY (V)2N O R M A L I Z E D F I L T E R C U T O F F1569-7 F021.041.031.021.011.000.990.980.970.9646810TEMPERATURE (°C)–50N O R M A L I Z E D F I L T E R C U T O F F1569-7 F031.0101.0081.0061.0041.0021.0000.9980.9960.9940.9920.990–250255075100V SUPPLY (V)2D I V I D E R A T I O1569-7 F044.084.044.003.9646810+–f 1569-7 F01LTC1569-778LTC1569-7input signal at IN + should be centered around the DC voltage at IN –. The input can also be AC coupled, as shown in the Typical Applications section.For inverting single-ended filtering, connect IN + to GND or to quiet DC reference voltage. Apply the signal to IN –. The DC gain from IN – to OUT is –1, assuming IN – is referenced to IN + and OUT is reference to GND.Refer to the Typical Performance Characteristics section to estimate the THD for a given input level.Dynamic Input ImpedanceThe unique input sampling structure of the LTC1569-7 has a dynamic input impedance which depends on the con-figuration, i.e., differential or single-ended, and the clock frequency. The equivalent circuit in Figure 8 illustrates the input impedance when the cutoff frequency is 128kHz. For other cutoff frequencies replace the 125k value with 125k • (128kHz/f CUTOFF ).When driven with a single-ended signal into IN – with IN +tied to GND, the input impedance is very high (~10M Ω).When driven with a single-ended signal into IN + with IN –tied to GND, the input impedance is a 125k resistor to GND.When driven with a complementary signal whose com-mon mode voltage is GND, the IN + input appears to have 125k to GND and the IN – input appears to have –125k to GND. To make the effective IN – impedance 125k when driven differentially, place a 62.5k resistor from IN – to GND. For other cutoff frequencies use 62.5k • (128kHz/f CUTOFF ), as shown in the Typical Applications section. The typical variation in dynamic input impedance for a given clock frequency is ±10%.Wideband NoiseThe wideband noise of the filter is the RMS value of the device’s output noise spectral density. The wideband noise data is used to determine the operating signal-to-noise at a given distortion level. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering (Table 2). Table 3 lists the typical wideband noise for each supply.APPLICATIO S I FOR ATIO W UU U The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 1µF ceramic capacitor be-tween V + (Pin 7) and V – (Pin 4) , as close as possible to the IC to minimize inductance. Avoid parasitic capacitance on R X and avoid routing noisy signals near R X (Pin 6). Use a ground plane connected to V – (Pin 4) for single supply applications. Connect a ground plane to GND (Pin 3) for dual supply applications and connect V – (Pin 4) to a copper trace with low thermal resistance.Input and Output RangeThe input signal range includes the full power supply range. The output voltage range is typically (V – + 50mV)to (V + – 0.8V) when V S = 3V. To maximize the undistorted peak-to-peak signal swing of the filter, the GND (Pin 3)voltage should be set to 2V (1.11V) in single 5V (3V)supply applications.The LTC1569-7 can be driven with a single-ended or differential signal. When driven differentially, the voltage between IN + and IN – (Pin 1 and Pin 2) is filtered with a DC gain of 1. The single-ended output voltage OUT (Pin 8) is referenced to the voltage of the GND (Pin 3). The common mode voltage of IN + and IN – can be any voltage that keeps the input signals within the power supply range.For noninverting single-ended applications, connect IN –to GND or to a quiet DC reference voltage and apply the input signal to IN +. If the input is DC coupled then the DC gain from IN + to OUT will be 1. This is true given IN + and OUT are referenced to the same voltage, i.e., GND, V – or some other DC reference. To achieve the distortion levels shown in the Typical Performance Characteristics theFigure 8OUTLTC1569-7910LTC1569-7Single 3V Operation, AC Coupled Input,128kHz Cutoff Frequencyf CUTOFF =n = 1, 4, 16 FOR PIN 5 ATGROUND, OPEN, V +128kHz n = 1()10k R EXT()n = 1, 4, 16 FOR PIN 5 ATGROUND, OPEN, V +n = 4R EXTSingle 3V Supply Operation, DC Coupled,32kHz Cutoff FrequencySingle 5V Operation, 300kHz Cutoff Frequency,DC Coupled Differential Inputs with Balanced Input ImpedanceFf CUTOFF ~n = 1, 4, 16 FOR PIN 5 ATGROUND, OPEN, V +128kHz n = 1()10k 4.1k()TYPICAL APPLICATIO SUSingle 3V, AC Coupled Input,128kHz Cutoff FrequencyFREQUENCY (Hz)G A I N (d B )GROUP DELAY 1569-7 TA02a0–10–20–30–40–50–60–70–80–90µs µsµsevery clock period. Therefore, the sampling frequency is twice the clock frequency and 64 times the filter cutoff frequency. Input signals with frequencies near 2 • f CLK ± f CUTOFF will be aliased to the passband of the filter and appear at the output unattenuated.Power Supply CurrentThe power supply current depends on the operating mode.When the LTC1569-7 is in the divide-by-1 mode, or whenclocked externally, the supply current is reduced by 50%for supply voltages below 4V. For the divide-by-4 and divide-by-16 modes, the supply current is reduced by 60% relative to the current when clocked externally,independent of the power supply voltage. Power supply current versus cutoff frequency for various operating modes is shown in the “Typical Performance Characteris-tics” section.APPLICATIO S I FOR ATIO WUU ULTC1569-711 Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.12LTC1569-7PART NUMBER DESCRIPTIONCOMMENTSLTC1064-3Linear Phase, Bessel 8th Order Filter f CLK /f CUTOFF = 75/1 or 150/1, Very Low Noise LTC1064-7Linear Phase, 8th Order Lowpass Filter f CLK /f CUTOFF = 50/1 or 100/1, f CUTOFF(MAX) = 100kHzLTC1068-x Universal, 8th Order Filterf CLK /f CUTOFF = 25/1, 50/1, 100/1 or 200/1, f CUTOFF(MAX) = 200kHz LTC1069-7Linear Phase, 8th Order Lowpass Filter f CLK /f CUTOFF = 25/1, f CUTOFF(MAX) = 200kHz, SO-8LTC1164-7Low Power, Linear Phase Lowpass Filter f CLK /f CUTOFF = 50/1 or 100/1, I S = 2.5mA, V S = 5V LTC1264-7Linear Phase, 8th Order Lowpass Filter f CLK /f CUTOFF = 25/1 or 50/1, f CUTOFF(MAX) = 200kHz LTC1562/LTC1562-2Universal, 8th Order Active RC Filterf CUTOFF(MAX) = 150kHz (LTC1562)f CUTOFF(MAX) = 300kHz (LTC1562-2)© LINEAR TECHNOLOGY CORPORA TION 1998sn15697 15697fs LT/TP 0300 4K • PRINTED IN THE USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 q FAX: (408) 434-0507 q RELATED PARTSTYPICAL APPLICATIOSUµF1569-7 TA09µF1569-7 TA10D D Pulse Shaping Circuit for Single 3V Operation, 300kbps2 level data, 150kHz Cutoff FilterPulse Shaping Circuit for Single 3V Operation, 400kbps(200ksps) 4 Level Data, 128kHz Cutoff Filter1569-7 TA070.25V /D I V1µs/DIV1569-7 TA080.3V /D I V1µs/DIV2-Level, 300kbps Eye Diagram4-Level, 400kbps (200ksps)Eye DiagramLTC1569CS8-7#PBF LTC1569IS8-7#PBF LTC1569CS8-6#PBF.。
LTC4213 1 4213f 电子电路保护器说明书
2µs/DIV4213 TA01b124213fBias Supply Voltage (V CC )...........................–0.3V to 9V Input VoltagesON, SENSEP, SENSEN.............................–0.3V to 9V I SEL ..........................................–0.3V to (V CC + 0.3V)Output VoltagesGATE .....................................................–0.3V to 15V READY.....................................................–0.3V to 9V Operating Temperature RangeLTC4213C ...............................................0°C to 70°C LTC4213I.............................................–40°C to 85°C Storage Temperature Range.................–65°C to 150°C Lead Temperature (Soldering, 10sec)...................300°CORDER PART NUMBER DDB PART*MARKING T JMAX = 125°C, θJA = 250°C/WEXPOSED PAD (PIN 9)PCB CONNECTION OPTIONALConsult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.LBHVLTC4213CDDB LTC4213IDDB ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOUUW (Note 1)ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Bias Supply Voltage ● 2.36V V SENSEP SENSEP Voltage ●06V I CC V CC Supply Current●1.63mA V CC(UVLR)V CC Undervoltage Lockout Release V CC Rising● 1.8 2.07 2.23V ∆V CC(UVHYST)V CC Undervoltage Lockout Hysteresis ●30100160mV I SENSEP SENSEP Input Current V SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA I SENSENSENSEN Input CurrentV SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA V SENSEP = V SENSEN = 5V,50280µAReset Mode or Fault ModeV CBCircuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●22.52527.5mV V CB = V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●455055mV I SEL = V CC, V SENSEP = V CC ●90100110mV V CB(FAST)Fast Circuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●63100115mV V CB(FAST)= V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●126175200mV I SEL = V CC, V SENSEP = V CC ●252325371mV I GATE(UP)GATE Pin Pull Up Current V GATE = 0V●–50–100–150µA I GATE(DN)GATE Pin Pull Down Current ∆V SENSEP – V SENSEN = 200mV, V GATE = 8V ●1040mA ∆V GSMAX External N-Channel Gate Drive V SENSEN = 0, V CC ≥ 2.97V, I GATE = –1µA ● 4.8 6.58V V SENSEN = 0, V CC = 2.3V, I GATE = –1µA ● 2.65 4.38V ∆V GSARMV GS Voltage to Arm Circuit BreakerV SENSEN = 0, V CC ≥ 2.97V ● 4.4 5.47.6V V SENSEN = 0, V CC = 2.3V●2.53.57VTOP VIEWDDB PACKAGE8-LEAD (3mm × 2mm) PLASTIC DFN567894321READY ON I SEL GND V CC SENSEP SENSEN GATE34213f∆V GSMAX – ∆V GSARM Difference Between ∆V GSMAX and V SENSEN = 0, V CC ≥ 2.97V ●0.3 1.1V ∆V GSARMV SENSEN = 0, V CC = 2.3V●0.150.8VV READY(OL)READY Pin Output Low Voltage I READY = 1.6mA, Pull Down Device On ●0.20.4V I READY(LEAK)READY Pin Leakage Current V READY = 5V, Pull Down Device Off ●0±1µA V ON(TH)ON Pin High Threshold ON Rising, GATE Pulls Up ●0.760.80.84V ∆V ON(HYST)ON Pin Hysteresis ON Falling, GATE Pulls Down104090mV V ON(RST)ON Pin Reset Threshold ON Falling, Fault Reset, GATE Pull Down ●0.360.40.44V I ON(IN)ON Pin Input Current V ON = 1.2V●0±1µA ∆V OV Overvoltage Threshold ●0.410.7 1.1V ∆V OV = V SENSEP – V CCt OVOvervoltage Protection Trip Time V SENSEP = V SENSEN = Step 5V to 6.2V 2565160µs t FAULT(SLOW)V CB Trips to GATE Discharging ∆V SENSE Step 0mV to 50mV,●71627µs V SENSEN Falling, V CC = V SENSEP = 5V t FAULT(FAST)V CB(FAST) Trips to GATE Discharging ∆V SENSE Step 0V to 0.3V, V SENSEN Falling,●12.5µs V SENSEP = 5Vt DEBOUNCE Startup De-Bounce Time V ON = 0V to 2V Step to Gate Rising,2760130µs (Exiting Reset Mode)t READY READY Delay Time V GATE = 0V to 8V Step to READY Rising,2250115µs V SENSEP = V SENSEN = 0t OFF Turn-Off Time V ON = 2V to 0.6V Step to GATE Discharging 1.5510µs t ON Turn-On Time V ON = 0.6V to 2V Step to GATE Rising,4816µs (Normal Mode)t RESETReset TimeV ON Step 2V to 0V2080150µsNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOLPARAMETERCONDITIONSMIN TYP MAX UNITSNote 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.4564213ft RESET vs Temperaturet FAULT(SLOW) vs V CCt FAULT(SLOW) vs Temperaturet FAULT(FAST) vs V CCt FAULT(FAST) vs TemperatureTYPICAL PERFOR A CE CHARACTERISTICSU WSpecifications are at T A = 25°C. V CC = 5Vunless otherwise noted.t F A U L T (F A S T ) (µs )4213 G230.90.80.71.01.11.21.3TEMPERATURE (°C)–50050100125–252575BIAS SUPPLY VOLTAGE (V)2.010t F A U L T (S L O W ) (µs )14121618 3.0 4.0 5.0 6.04213 G202022 2.53.54.55.5TEMPERATURE (°C)–500501001254213 G21–25257510t F A U L T (S L O W ) (µs )141216182022TEMPERATURE (°C)–500501001254213 G19–252575t R E S E T (µs )60708090100BIAS SUPPLY VOLTAGE (V)2.0t F A U L T (F A S T ) (µs )3.04.05.06.04213 G222.53.54.55.50.90.80.71.01.11.21.374213fPI FU CTIO SU U UREADY (Pin 1): READY Status Output. Open drain output that goes high impedance when the external MOSFET is on and the circuit breaker is armed. Otherwise this pin pulls low.ON (Pin 2): ON Control Input. The LTC4213 is in reset mode when the ON pin is below 0.4V. When the ON pin increases above 0.8V, the device starts up and the GATE pulls up with a 100µA current source. When the ON pin drops below 0.76V, the GATE pulls down. To reset a circuit breaker fault, the ON pin must go below 0.4V.I SEL (Pin 3): Threshold Select Input. With the I SEL pin grounded, float or tied to V CC the V CB is set to 25mV, 50mV or 100mV, respectively. The corresponding V CB(FAST)values are 100mV, 175mV and 325mV.GND (Pin 4): Device Ground.GATE (P in 5): GATE D rive Output. An internal charge pump supplies 100µA pull-up current to the gate of the external N-channel MOSFET. Internal circuitry limits thevoltage between the GATE and SENSEN pins to a safe gate drive voltage of less than 8V. When the circuit breaker trips, the GATE pin abruptly pulls to GND.SENSEN (Pin 6): Circuit Breaker Negative Sense Input.Connect this pin to the source of the external MOSFET.During reset or fault mode, the SENSEN pin discharges the output to ground with 280µA.SENSEP (P in 7): Circuit Breaker Positive Sense Input.Connect this pin to the drain of external N-channel MOSFET.The circuit breaker trips when the voltage across SENSEP and SENSEN exceeds V CB . The input common mode range of the circuit breaker is from ground to V CC + 0.2V when V CC < 2.5V. For V CC ≥ 2.5V, the input common mode range is from ground to V CC + 0.4V.V CC (Pin 8): Bias Supply Voltage Input. Normal operation is between 2.3V and 6V. An internal under-voltage lockout circuit disables the device when V CC < 2.07V.Exposed Pad (Pin 9): Exposed pad may be left open or connected to device ground.8910114213fsupply transient dips below 1.97V of less than 80µs are ignored.ON FunctionWhen V ON is below comparator COMP1’s threshold of 0.4V for 80µs, the device resets. The system leaves reset mode if the ON pin rises above comparator COMP2’s threshold of 0.8V and the UVLO condition is met. Leaving reset mode, the GATE pin starts up after a t DEBOUNCE delay of 60µs. When ON goes below 0.76V, the GATE shuts off after a 5µs glitch filter delay. The output is discharged by the external load when V ON is in between 0.4V to 0.8V. At this state, the ON pin can re-enable the GATE if V ON exceeds 0.8V for more than 8µs. Alternatively, the device resets if the ON pin is brought below 0.4V for 80µs. Once reset, the GATE pin restarts only after the t DEBOUNCE 60µs delay at V ON rising above 0.8V. To protect the ON pin from overvoltage stress due to supply transients, a series resistor of greater than 10k is recommended when the ON pin is connected directly to the supply. An external resis-tive divider at the ON pin can be used with COMP2 to set a supply undervoltage lockout value higher than the inter-nal UVLO circuit. An RC filter can be implemented at the ON pin to increase the powerup delay time beyond the internal 60µs delay.Gate FunctionThe GATE pin is held low in reset mode. 60µs after leaving reset mode, the GATE pin is charged up by an internal 100µA current source. The circuit breaker arms when V GATE > V SENSEN + ∆V GSARM . In normal mode operation,the GATE peak voltage is internally clamped to ∆V GSMAX above the SENSEN pin. When the circuit breaker trips, an internal MOSFET shorts the GATE pin to GND, turning off the external MOSFET.READY StatusThe READY pin is held low during reset and at startup. It is pulled high by an external pullup resistor 50µs after the circuit breaker arms. The READY pin pulls low if the circuit breaker trips or the ON pin is pulled below 0.76V, or V CC drops below undervoltage lockout.∆V GSARM and V GSMAXEach MOSFET has a recommended V GS drive voltage where the channel is deemed fully enhanced and R DSON is minimized. Driving beyond this recommended V GS volt-age yields a marginal decrease in R DSON . At startup, the gate voltage starts at ground potential. The GATE ramps past the MOSFET threshold and the load current begins to flow. When V GS exceeds ∆V GSARM , the circuit breaker is armed and enabled. The chosen MOSFET should have a recommended minimum V GS drive level that is lower than ∆V GSARM . Finally, V GS reaches a maximum at ∆V GSMAX.Trip and Reset Circuit BreakerFigure 2 shows the timing diagram of V GATE and V READY after a fault condition. A tripped circuit breaker can be reset either by cycling the V CC bias supply below UVLO thresh-old or pulling ON below 0.4V for >t RESET . Figure 3 shows the timing diagram for a tripped circuit breaker being reset by the ON pin.Calculating Current LimitThe fault current limit is determined by the R DSON of the MOSFET and the circuit breaker voltage V CB .I V R LIMIT CB DSON=()2The R DSON value depends on the manufacturer’s distribu-tion, V GS and junction temperature. Short Kelvin-sense connections between the MOSFET drain and source to the LTC4213 SENSEP and SENSEN pins are strongly recommended.For a selected MOSFET, the nominal load limit current is given by:I V R LIMIT NOM CB NOM DSON NOM ()()()()=3The minimum load limit current is given by:I V R LIMIT MIN CB MIN DSON MAX ()()()()=4APPLICATIO S I FOR ATIOW UUU1213144213fOperating temperature of 0° to 70°C.R DSON @ 25°C = 100%R DSON @ 0°C = 90%R DSON @ 70°C = 120%MOSFET resistance variation:R DSON(NOM) = 15m • 0.82 = 12.3m ΩR DSON(MAX) = 15m • 1.333 • 0.93 • 1.2 = 15m • 1.488= 22.3m ΩR DSON(MIN) = 15m • 0.667 • 0.80 • 0.90 = 15m • 0.480= 7.2m ΩV CB variation:NOM V CB = 25mV = 100%MIN V CB = 22.5mV = 90%MAX V CB = 27.5mV = 110%The current limits are:I LIMIT(NOM) = 25mV/12.3m Ω = 2.03A I LIMIT(MIN) = 22.5mV/22.3m Ω = 1.01A I LIMIT(MAX) = 27.5mV/7.2m Ω = 3.82AFor proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. So this system is suitable for operating load current up to 1A. From this calculation, we can start with the general rule for MOSFET R DSON by assuming maxi-mum operating load current is roughly half of the I LIMIT(NOM). Equation 7 shows the rule of thumb.I V R OPMAX CB NOM DSON NOM =()()•()27Note that the R DSON(NOM) is at the LTC4213 nominal operating ∆V GSMAX rather than at typical vendor spec.Table 1 gives the nominal operating ∆V GSMAX at the various operating V CC . From this table users can refer to the MOSFET’s data sheet to obtain the R DSON(NOM) value.Table 1. Nominal Operating ∆V GSMAX for Typical Bias Supply VoltageV CC (V)∆V GSMAX (V)2.3 4.32.5 5.02.7 5.63.0 6.53.37.05.07.06.07.0Load Supply Power-Up after Circuit Breaker Armed Figure 4 shows a normal power-up sequence for the circuit in Figure 1 where the V IN load supply power-up after circuit breaker is armed. V CC is first powered up by an auxiliary bias supply. V CC rises above 2.07V at time point 1. V ON exceeds 0.8V at time point 2. After a 60µs debounce delay, the GATE pin starts ramping up at time point 3. The external MOSFET starts conducting at time point 4. At time point 5, V GATE exceed ∆V GSARM and the circuit breaker is armed. After 50µs (t READY delay), READY pulls high by an external resistor at time point 6. READY signals the V IN load supply module to start its ramp. The load supply begins soft-start ramp at time point 7. The load supply ramp rate must be slow to prevent circuit breaker tripping as in equation (8).∆∆V t I I C IN OPMAX LOADLOAD<−()8Where I OPMAX is the maximum operating current defined by equation 7.For illustration, V CB = 25mV and R DSON = 3.5m Ω at the nominal operating ∆V GSMAX . The maximum operating current is 3.5A (refer to equation 7). Assuming the load can draw a current of 2A at power-up, there is a margin of 1.5A available for C LOAD of 100µF and V IN ramp rate should be <15V/ms. At time point 8, the current through the MOSFET reduces after C LOAD is fully charged.APPLICATIO S I FOR ATIOW UUU1516174213fThe selected MOSFET V GS absolute maximum rating should meet the LTC4213 maximum ∆V GSMAX of 8V.Other MOSFET criteria such as V BDSS , I DMAX , and R DSON should be reviewed. Spikes and ringing above maximum operating voltage should be considered when choosing V BDSS . I DMAX should be greater than the current limit. The maximum operating load current is determined by the R DSON value. See the section on “Calculating Current Limit” for details.Supply RequirementsThe LTC4213 can be powered from a single supply or dual supply system. The load supply is connected to the SENSEP pin and the drain of the external MOSFET. In the single supply case, the V CC pin is connected to the load supply, preferably with an RC filter. With dual supplies,V CC is connected to an auxiliary bias supply V AUX where V AUX voltage should be greater or equal to the load supply voltage. The load supply voltage must be capable of sourcing more current than the circuit breaker limit. If the load supply current limit is below the circuit breaker trip current, the LTC4213 may not react when the output overloads. Furthermore, output overloads may trigger UVLO if the load supply has foldback current limit in a single supply system.V IN Transient and Overvoltage ProtectionInput transient spikes are commonly observed whenever the LTC4213 responds to overload. These spikes can be large in amplitude, especially given that large decoupling capacitors are absent in hot swap environments. These short spikes can be clipped with a transient suppressor of adequate voltage and power rating. In addition, the LTC4213can detect a prolonged overvoltage condition. WhenAPPLICATIO S I FOR ATIOW UUU point 6 should be within the circuit breaker limits. Other-wise, the system fails to start and the circuit breaker trips immediately after arming. In most applications additional external gate capacitance is not required unless C LOAD is large and startup becomes problematic. If an external gate capacitor is employed, its capacitance value should not be excessive unless it is used with a series resistor. This is because a big gate capacitor without resistor slows down the GATE turn off during a fault. An alternative method would be a stepped I SEL pin to allow a higher current limit during startup.In the event of output short circuit or a severe overload, the load supply can collapse during GATE ramp up due to load supply current limit. The chosen MOSFET must withstand this possible brief short circuit condition before time point 6 where the circuit breaker is allowed to trip. Bench short circuit evaluation is a practical verification of a reliable design. To have current limit while powering a MOSFET into short circuit conditions, it is preferred that the load supply sequences to turn on after the circuit breaker is armed as described in an earlier section.Power-Off CycleThe system can be powered off by toggling the ON pin low.When ON is brought below 0.76V for 5µs, the GATE and READY pins are pulled low. The system resets when ON is brought below 0.4V for 80µs.MOSFET SelectionThe LTC4213 is designed to be used with logic (5V) and sub-logic (3V) MOSFETs for V CC potentials above 2.97V with ∆V GSMAX exceeding 4.5V. For a V CC supply range between 2.3V and 2.97V, sub-logic MOSFETs should be used as the minimum ∆V GSMAX is less than 4.5V.1819Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.201630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2005LT/TP 0405 500 • PRINTED IN USA。
LTC6912IDE-1中文资料
12UUUGAI SETTI GS A D PROPERTIESTable 1. LTC6912-1 GAIN SETTINGS AND PROPERTIESUPPER/LOWER NOMINALNIBBLE VOLTAGE GAIN MAXIMUM LINEAR INPUT RANGE (V P-P)Q7Q6Q5Q4Dual 5V Single 5V Single 3V NOMINAL INPUT NOMINAL OUTPUT Q3Q2Q1Q0Volts/Volt dB Supply Supply Supply IMPEDANCE (kΩ) IMPEDANCE (Ω) 00000–1201053(Open)0.4 0001–101053100.7 0010–265 2.5 1.55 3.4 0011–514210.62 3.4 0100–102010.50.31 3.4 0101–20260.50.250.151 6.4 0110–50340.20.10.06115 0111–100400.10.050.03130 10X X0–1201053(Open)(Open) 11X X Not Used (Note 11)Not UsedTable 2. LTC6912-2 GAIN SETTINGS AND PROPERTIESUPPER/LOWER NOMINALNIBBLE VOLTAGE GAIN MAXIMUM LINEAR INPUT RANGE (V P-P)Q7Q6Q5Q4Dual 5V Single 5V Single 3V NOMINAL INPUT NOMINAL OUTPUT Q3Q2Q1Q0Volts/Volt dB Supply Supply Supply IMPEDANCE (kΩ) IMPEDANCE (Ω) 00000–1201053(Open)0.4 0001–101053100.7 0010–265 2.5 1.55 3.4 0011–412 2.5 1.250.75 2.5 3.4 0100–818.1 1.250.6250.375 1.25 3.4 0101–1624.10.6250.31250.188 1.25 6.4 0110–3230.10.31250.1560.094 1.2515 0111–6436.10.1560.0780.047 1.2530 10X X0–1201053(Open)(Open) 11X X Not Used (Note 11)Not Used36912fa4567891011121314151617181920216912faAPPLICATIO S I FOR ATIOW UUU Offset Voltage vs Gain SettingThe electrical tables list DC offset (error), V OS(OA), at the inputs of the internal op amp (See Figure 1). The electrical tables also show the resulting, gain dependent offset voltage referred to the INA, or INB pins, V OS(IN). The two measures are related through the feedback/input resistor ratio, which equals the nominal gain-magnitude setting,|GAIN|:V OS(IN) = (1 + 1/|GAIN|) V OS(OA)Offset voltages at any gain setting can be inferred from this relationship. For example, an internal amplifier offset V OS(OA) of 1mV will appear referred to the INA, INB pins as 2mV at a gain setting of 1, or 1.5mV at a gain setting of 2.At high gains, V OS(IN) approaches V OS(OA). (Offset voltage is random and can have either polarity centered on 0V).The MOS input circuitry of the internal op amp in Figure 1draws negligible input currents (less than 10µA), so only V OS(OA) and the GAIN affect the overall amplifier’s offset.AC-Coupled OperationAdding capacitors in series with the INA and INB pins converts the LTC6912-X into a dual AC-coupled inverting amplifier, suppressing the input signal’s DC level (and also adding the additional benefit of reducing the offset voltage from the LTC6912-X’s amplifier itself). No further compo-nents are required because the input of the LTC6912-X biases itself correctly when a series capacitor is added.The INA and INB analog input pins connect internally to a resistor whose nominal value varies between 10k Ω and 1k Ω depending on the version of LTC6912 used (see the rightmost column of Tables 1 and 2). Therefore, the low frequency cutoff will vary with capacitor and gain setting.If, for example, a low frequency corner of 1kHz (or lower)on the LTC6912-1 is desired, use a series capacitor of 0.16µF or larger. 0.16µF has a reactance of 1k Ω at 1kHz,giving a 1kHz lower –3dB frequency for gain settings of 10V/V through 100V/V. If the LTC6912-1 is operated at lower gain settings with a 0.16µF capacitor, the higher input resistance will reduce the lower corner frequency down to 100Hz at a gain setting of 1V/V. These frequencies scale inversely with the value of input capacitor used.Note that operating the LTC6912 family in “zero” gain mode (digital state 0000) open circuits both the INA and INB pins and this demands some care if employed with a series AC coupling input capacitor. When the chip enters the zero gain mode, the opened INA or INB pin tends to sample and freeze the voltage across the capacitor to the value it held just before the zero gain state. This can place the INA or INB pin at or near the DC potential of a supply rail. (The INA or INB pin may also drift to a supply potential in this state due to small leakage currents.) To prevent driving the INA or INB pin outside the supply limit and potentially damaging the chip, avoid AC input signals in the zero gain state with an AC coupling capacitor. Also,switching later to a non-zero gain value will cause a transient pulse at the output of the LTC6912-1 (with a time constant set by the capacitor value and the new LTC6912-1input resistance value). This occurs because the INA and INB pins return to the AGND potential forcing transient current sourced by the amplifier output to charge the AC coupling capacitor to its proper DC blocking value.SNR and Dynamic RangeThe term “dynamic range” is much used (and abused)with signal paths. Signal-to-noise (SNR) is an unambigu-ous comparison of signal and noise levels, measured in the same way and under the same operating conditions. In a variable gain amplifier, however, further characterization is useful because both noise and maximum signal level in the amplifier will vary with the gain setting, in general. In the LTC6912-X, maximum output signal is independent of gain (and is near the full power supply voltage, as detailed in the swing sections of the Electrical Characteristics table). The maximum input level falls with increasing gain,and the input-referred noise falls as well (listed also in the table). To summarize the useful signal range in such an amplifier, we define dynamic range (DR) as the ratio of maximum input (at unity gain) to minimum input-referred noise (at maximum gain). This DR has a physical interpre-tation as the range of signal levels that will experience an SNR above unity V/V or 0dB. At a 10V total power supply,DR in the LTC6912-X (gains 0V/V to 100V/V), the DR is typically 115dB (the ratio of 9.9 V P-P , or 3.5V RMS , maxi-mum input to the 6.3µV RMS high gain input noise). The2223Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.24Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2004LT/LT 1005 REV A • PRINTED IN USA。
现代传感器技术-11-低功耗的传感器电路设计和数据获取及处理方法-2016
11 低功耗的传感器电路设计和数据获取及处理方法
11.2 典型信号调理集成器件及应用 11.2.2多功能集成调理器件 (1) AD693型多功能传感信号调理器 性能特点 (g)利用外部电阻选配不同类型的热电偶并设定最高测温， (h)具有过电流保护和反向过电压保护功能； (i)通常由环路电源供电，特殊情况可由本地电源单独供电。 主要构成: PGA(A1)+ U/I转换器+基准电压及分压器+备用A2 工作原理 A1用于信号缓冲放大和输入范围设定，改变P1、P2接线方 式可调A1的增益，设置输入电压范围；U/I转换器内设限流 比较器，能将环路电流限制在±25 mA以下；+6.200V电压 基准源为U/I转换器提供偏置电压，用来调输出电流零点。
图a为采用2.5V双电源的接线图， 图b为+5V单电源的接线图，C3、C4 为退耦电容。CF调带宽，Rp调增益。 输出电压从Uo、AGND端引出。
2018/7/4
CS2001的典型应用电路
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11 低功耗的传感器电路设计和数据获取及处理方法
11.2 典型信号调理集成器件及应用 11.2.2多功能集成调理器件 (1) AD693型多功能传感信号调理器 可用作小信号U/I转换器及多种传感器的高精度信号调理。 性能特点 (a) 含PGA、U/I转换器和多路输出式基准电压源; (b) 三种输出电流形式: 4~20mA(单极性), 0~20mA(单极性)， 12mA±8mA(双极性); (c) 输入电压范围和电流零点均可单独调节; (d) 高精度。调零后的总转换误差小于±0.1%; (e) 含备用放大器，可对由铂热电阻、热电偶及电阻应变片 桥路的信号进行调理； (f)带Pt100型铂热电阻(PRTD)专设接口，测温误差±0.5℃；
一种多通道数字接收机的设计与测试方法
收稿日期：２０２２－０４－２１基金项目：国家自然科学基金（Ｕ２２４１２７７）引用格式：史磊，晏怀斌，于骏申．一种多通道数字接收机的设计与测试方法［Ｊ］．测控技术，２０２３，４２（７）：８０－８６．ＳＨＩＬ，ＹＡＮＨＢ，ＹＵＪＳ．ＤｅｓｉｇｎａｎｄＴｅｓｔＭｅｔｈｏｄｏｆａＭｕｌｔｉｃｈａｎｎｅｌＤｉｇｉｔａｌＲｅｃｅｉｖｅｒ［Ｊ］．Ｍｅａｓｕｒｅｍｅｎｔ＆ＣｏｎｔｒｏｌＴｅｃｈｎｏｌｏｇｙ，２０２３，４２（７）：８０－８６．一种多通道数字接收机的设计与测试方法史 磊，晏怀斌，于骏申（上海船舶电子设备研究所，上海 ２０１１０８）摘要：设计了一种可用于测控系统的多通道数字接收机，结合性能指标测试，表明该接收机具有有效性和通用性。
重点阐述了该多通道数字接收机设计组成和下属各模块的设计原理，通过对幅度相位一致性、短路噪声、固定增益和采集预处理效果等接收机关键性能指标开展仿真测试和数据分析，给出某型测控设备中的实际测试结果，验证了设计的多通道数字接收机满足某型测控系统实际使用需求。
针对特定功能的测控系统，可通过尝试调整接收机相关模块的设计参数，为特定功能接收机设计提供参考。
关键词：多通道；数字接收机；信号调理；采集预处理中图分类号：ＴＰ２９ 文献标志码：Ａ 文章编号：１０００－８８２９（２０２３）０７－００８０－０７ｄｏｉ：１０．１９７０８／ｊ．ｃｋｊｓ．２０２２．１０．３０９ＤｅｓｉｇｎａｎｄＴｅｓｔＭｅｔｈｏｄｏｆａＭｕｌｔｉｃｈａｎｎｅｌＤｉｇｉｔａｌＲｅｃｅｉｖｅｒＳＨＩＬｅｉ牞ＹＡＮＨｕａｉｂｉｎ牞ＹＵＪｕｎｓｈｅｎ牗ＳｈａｎｇｈａｉＭａｒｉｎｅＥｌｅｃｔｒｏｎｉｃＥｑｕｉｐｍｅｎｔＲｅｓｅａｒｃｈＩｎｓｔｉｔｕｔｅ牞Ｓｈａｎｇｈａｉ２０１１０８牞Ｃｈｉｎａ牘Ａｂｓｔｒａｃｔ牶Ａｍｕｌｔｉｃｈａｎｎｅｌｄｉｇｉｔａｌｒｅｃｅｉｖｅｒｆｏｒｍｅａｓｕｒｅｍｅｎｔａｎｄｃｏｎｔｒｏｌｓｙｓｔｅｍｉｓｄｅｓｉｇｎｅｄ．Ｃｏｍｂｉｎｅｄｗｉｔｈｔｈｅｐｅｒｆｏｒｍａｎｃｅｉｎｄｅｘｔｅｓｔ牞ｔｈｅｅｆｆｅｃｔｉｖｅｎｅｓｓａｎｄｕｎｉｖｅｒｓａｌｉｔｙｏｆｔｈｅｒｅｃｅｉｖｅｒａｒｅｓｈｏｗｎ．Ｔｈｅｄｅｓｉｇｎｃｏｍｐｏｓｉｔｉｏｎｏｆｔｈｅｍｕｌｔｉｃｈａｎｎｅｌｄｉｇｉｔａｌｒｅｃｅｉｖｅｒａｎｄｔｈｅｄｅｓｉｇｎｐｒｉｎｃｉｐｌｅｏｆｉｔｓｓｕｂｏｒｄｉｎａｔｅｍｏｄｕｌｅｓａｒｅｅｍｐｈａｓｉｚｅｄ．Ｔｈｒｏｕｇｈｔｈｅｓｉｍｕｌａｔｉｏｎｔｅｓｔａｎｄｄａｔａａｎａｌｙｓｉｓｏｆｔｈｅｋｅｙｐｅｒｆｏｒｍａｎｃｅｉｎｄｅｘｅｓｏｆｔｈｅｒｅｃｅｉｖｅｒ牞ｓｕｃｈａｓａｍｐｌｉｔｕｄｅａｎｄｐｈａｓｅｃｏｎｓｉｓｔｅｎｃｙ牞ｓｈｏｒｔ ｃｉｒｃｕｉｔｎｏｉｓｅ牞ｆｉｘｅｄｇａｉｎａｎｄａｃｑｕｉｓｉｔｉｏｎｐｒｅｐｒｏｃｅｓｓｉｎｇｅｆｆｅｃｔ牞ｔｈｅａｃｔｕａｌｔｅｓｔｒｅｓｕｌｔｓｉｎａｃｅｒｔａｉｎｔｙｐｅｏｆｍｅａｓｕｒｅｍｅｎｔａｎｄｃｏｎｔｒｏｌｅｑｕｉｐｍｅｎｔａｒｅｇｉｖｅｎ牞ｗｈｉｃｈｖｅｒｉｆｉｅｓｔｈａｔｔｈｅｄｅｓｉｇｎｅｄｍｕｌｔｉ ｃｈａｎｎｅｌｄｉｇｉｔａｌｒｅｃｅｉｖｅｒｍｅｅｔｓｔｈｅａｃｔｕａｌｕｓｅｒｅｑｕｉｒｅｍｅｎｔｓｏｆａｃｅｒｔａｉｎｔｙｐｅｏｆｍｅａｓｕｒｅｍｅｎｔａｎｄｃｏｎｔｒｏｌｓｙｓｔｅｍ．Ｔｈｅｍｅａｓｕｒｅｍｅｎｔａｎｄｃｏｎｔｒｏｌｓｙｓｔｅｍｗｉｔｈｏｔｈｅｒｓｐｅｃｉｆｉｃｐａｒａｍｅｔｅｒｓｃａｎｐｒｏｖｉｄｅｒｅｆｅｒｅｎｃｅｆｏｒｔｈｅｄｅｓｉｇｎｏｆｔｈｅｒｅ ｃｅｉｖｅｒｗｉｔｈｓｐｅｃｉｆｉｃｆｕｎｃｔｉｏｎｓｂｙｔｒｙｉｎｇｔｏａｄｊｕｓｔｔｈｅｄｅｓｉｇｎｐａｒａｍｅｔｅｒｓｏｆｒｅｃｅｉｖｅｒｒｅｌａｔｅｄｍｏｄｕｌｅｓ．Ｋｅｙｗｏｒｄｓ牶ｍｕｌｔｉｃｈａｎｎｅｌ牷ｄｉｇｉｔａｌｒｅｃｅｉｖｅｒ牷ｓｉｇｎａｌｃｏｎｄｉｔｉｏｎｉｎｇ牷ａｃｑｕｉｓｉｔｉｏｎｐｒｅｐｒｏｃｅｓｓｉｎｇ 伴随着单片微波集成电路、微组装技术、Ａ／Ｄ采样电路、大规模可编程逻辑电路、多通道数字接收技术的快速发展，数字接收机几乎已经可以完全取代模拟接收机，成为当前接收机技术发展的主要方向。
LTC1298 微功耗双通道采样12位A D转换器演示手册说明书
1DESCRIPTIOUThe LTC ®1298 is a micropower, 11.1ksps, two-channel sampling 12-bit A/D converter that draws only 1.25mW from a single 5V supply. The LTC1298 demo board pro-vides the user with a stable and consistent platform on which to evaluate the LTC1298 A/D converter. In addition,the LTC1298 demo board illustrates the layout and by-passing techniques required to obtain optimum perfor-mance from this part. The LTC1298 demo board is de-signed to be easy to use and requires only a 7V to 15V supply, a clock signal, and an analog input signal. As shown in the Board Photo, the LTC1298 is a very space efficient solution for A/D users. By combining a mi-cropower 12-bit A/D, sample-and-hold, two-channel mul-tiplexer, serial port, and auto shutdown circuit into a single 8-pin SOIC package, all the data acquisition circuitry including the bypass caps occupy an area of only 0.1square inch.This manual shows how to use the demo board. It includes timing diagrams, power supply requirements, and analog input range information. Additionally, a schematic, parts list, drawings, and dimensions of all the PC board layers are included. Finally, an explanation of the layout andbypass strategies used in this board allows anyone de-signing a PC board to achieve maximum performance from the device.12-Bit A/D ConverterDemo Boards Proven µPower 12-Bit ADC Surface Mount Layout s On-Chip Two-Channel MulitplexersActual ADC Footprint Only 0.1 Inch 2 Including Bypass Capacitorss 71dB SINAD, 84dB THD and ±0.25LSB DNL sGerber Files for This Circuit Board Are Available.Call the LTC Factory.FEATURESTYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTOU UW DC045 • BP01SAMPLE FREQUENCY (Hz)0.1k11010010001k 10k 100kLT1286/98 G03S U P P L Y C U R RE N T (µA )Supply Current vs Sample Rate2DEMO MANUAL DC045W W T O P V I E WA EC 1DEMO MANUAL DC045 REFERENCEDESIGNATOR QUANTITY PART NUMBER DESCRIPTION VENDOR TELEPHONE C11TAJD476M01047µF 10V 20%, Tantalum Capacitor AVX(207) 282-5111 C2 to C5, C85GRM42-6X7R104K050AD0.1µF 50V 10%, X7R Chip Capacitor Murata Erie(814) 237-1431 C6, C9, C12312063G105ZATMA1µF 25V +80%/–20%, Y5V Chip Capacitor AVX(803) 448-9411 C71TAJB106M01010µF 10V 20%, Tantalum Capacitor AVX(207) 282-5111 C10112062R150K9BB215pF 50V 10% NPO Chip Capacitor Philips(407) 744-4200 C11108055A470GATBA47pF 50V 2% NPO Chip Capacitor AVX(803) 448-9411 D0 to D1112SF1-BR Red LED Data Display(800) 421-6815 E1, E22575-4Banana Jack Keystone(718) 956-8900 E3 to E531502-2Turret Keystone(718) 956-8900 JP11TSW-101-07-G-D Header Samtec(800) 726-8329 JP21TSW-104-07-G-D Header Samtec(800) 726-8329 JP31TSW-107-06-G-D Header Samtec(800) 726-8329 JP41TSW-105-07-G-SN Header Samtec(800) 726-8329 J11227699-3BNC Connector AMP(717) 564-0100 R1 to R1212CR32-621J-T620Ω 1/8W 5% 1206 Chip Resistor AVX(803) 448-9411 R13 to R153CT32-223J-T22k 1/8W 5% 1206 Chip Resistor AVX(803) 448-9411 R161CT32-102J-T1k 1/8W 5% 1206 Chip Resistor AVX(803) 448-9411 R171CT32-103J-T10k 1/8W 5% 1206 Chip Resistor AVX(803) 448-9411 R181CT32-5101J-T51Ω 1/8W 5% 1206 Chip Resistor AVX(803) 448-9411 S1190HBW03S DIP Switch Grayhill(708) 354-1040 U1174HC592IC Toshiba(408) 737-9844 U2174HC165IC Toshiba(408) 737-9844 U31LTC1298CS8IC LTC(408) 432-1900 U41LTC1021DCS8-5IC LTC(408) 432-1900 U5174HC14IC Texas Instruments(800) 336-5236 U61LT1121CST-5IC LTC(408) 432-1900 U7, U8274HC595IC Toshiba(408) 737-9844 4HTSP-3Plastic Stand.Micro Plastic(501) 453-88615SNT-100-BK-5Shunt Samtec(800) 726-832944/40 × 3/8Steel ScrewPARTS LISTOPERATIOUOPERATING THE BOARDPowering the BoardTo use the demo board, apply a 7V to 15V power source capable of supplying ≥100mA to the banana jacks (E1 and E2). Be careful to observe the correct polarity. On-board regulators provide 5V to the LTC1298’s V CC pin. LT1121-5 and LT1021 regulators generate 5V for the digital circuitry and ADC, respectively.Applying the Analog InputAnalog input signals are applied to the LTC1298’s two-channel (CH0 and CH1) input multiplexer through the demonstration board’s turret terminals E3 (CH0) and E4 (CH1). The input signals’ ground reference is applied to turret terminal E5. The analog signal input range is 0V to 5V. Optimum performance is achieved using a signal source that has low output impedance, is low noise, and34DEMO MANUAL DC045OPERATIOUhas low distortion. Signal generators such as the B & K Type 1051 sine generator give excellent results.Applying the Clock SignalThe clock signal is applied to BNC connector J1 and the CS signal is generated on the board. The clock input uses TTL or CMOS levels. The maximum clock frequency is 200kHz. While the clock signal is active, a high-to-low logic level transition is generated on the LTC1298’s CS input which initiates a conversion. The data transfer is shown in the timing diagrams (Figure 1).Reading the Output DataThe LTC1298 serial data outputs are buffered by the two 74HC595 latches and are available as a parallel output on connector JP3. The latches are used to drive the LEDs D0to D11. (Refer to the LTC1298 data sheet for details on different digital interface modes.)The LTC1298 output data is in unipolar format. A Data Ready line, RDY, (JP3 pin 13) is provided to latch the data.Data is valid on the rising edge of RDY. Connector JP3 has one ground pin (JP3 pin 14). Connect this pin to the data receiving system’s digital ground.MSB-First Data (MSBF = 0)Figure 1. Timing DiagramD CLKODD/ CSD LTC1286/98 • F02*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.ODD/ D t DATA : DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUTBECOMES A HIGH IMPEDANCE NODE. WITH CS LOW AND THE CLOCK ACTIVE, THE OUTPUT ON D OUT IS EITHER LSB-FIRST DATA (MSBF = 0) OR ZEROS (MSBF = 1).MSB-First Data (MSBF = 1)5DEMO MANUAL DC045OPERATIOUTable 1.JUMPER JUMPER NAME JUMPER CONNECTIONJP1LED EnableShorted to enable LEDs. Open to disable the LEDs.JP2A CS Shorted for normal operation. If open, the CS line can be driven externally to select or deselect the LTC1286.JP2B CLK Shorted for normal operation. If open, the CLK line can be driven externally to clock the LTC1286.JP2C D OUT Shorted for normal operation. If open, the D OUT line can drive a scope probe.JP2DD INShorted for normal operation. If open, the D IN line can be driven externally to configure the input multiplexer.The LTC1298’s data word can be acquired with a logic analyzer. By using a logic analyzer that has a PC-compat-ible floppy drive, (such as an HP1663A), conversion data can be stored on a disk and easily transferred to a PC. Once the data is transfered to a PC, programs such as Mathcad or Excel can be used to calculate FFTs. The FFTs can be used to obtain LTC1298 AC specifications such as signal-to-noise ratio and total harmonic distortion.LEDs D0 to D11 provide a visual display of the LTC1298’s digital output word. D0 is the LSB and D11 is the MSB.Jumper JP1 can be removed to disable the LEDs, reducing supply consumption by up to 56mA.Driving CS, D IN , and CLKJumpers for CS, CLK, D IN , and D OUT (JP2) are shorted for normal operation. The jumpers can be removed and CS,D IN , and CLK lines can be externally driven if desired. See the LTC1298 data sheet for details on driving these YOUTThe use of separate analog and digital ground planes is a good practice for a well designed LTC1298 PC board. Theproper way to make the analog and digital ground planes can be seen by examining the solder side of the PCB layout. The two ground planes are completely isolated except for one connection at the power supply ground input, E1. The two ground planes follow the same path on the component and solder sides of the board to reduce coupling between the ground planes. Also ensure that the analog ground plane’s solder side has a limited number of plane-breaking traces within it. Any trace that opens a portion of the ground plane may reduce the ground plane’s efficiency. Further, the analog and digital traces do not cross each other (whether on the board’s top or bottom side) or run adjacent to each other.BYPASSINGIt is important to place the supply/reference bypass ca-pacitor as close as possible to the LTC1298’s supply/reference pin. The ground side of the capacitor should have a very short path to analog ground. The V CC /V REF pins should be bypassed with high quality ceramic capaci-tors of at least 0.1µF.6DEMO MANUAL DC045OPERATIOUTable 2.INPUT/OUTPUT PINFUNCTIONJ1Clock InputE1GroundE27V to 15V at ≥100mA CH0Multiplexer Input Channel 0CH1Mulitplexer Input Channel 1AGND Input signals’ ground reference JP3-1D0 (LSB)JP3-2D1JP3-3D2JP3-4D3JP3-5D4JP3-6D5INPUT/OUTPUT PINFUNCTIONJP3-7D6JP3-8D7JP3-9D8JP3-10D9JP3-11D10JP3-12D11 (MSB)JP3-13RDY. Can be used by an external system to latch the ADC’s output. Latch data on the rising edge.JP3-14Ground. Connect to the digital ground of a data receiving system.PCB LAYOUT A D FILU WComponent Side Silkscreen7DEMO MANUAL DC045Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.PCB LAYOUT A D FILUWCircuit: Component SideCircuit: Solder SideComponent Side Solder MaskSolder Side Solder Mask8DEMO MANUAL DC045SYMBOL DIAMETER # OF HOLESA 0.1254B 0.2102C 0.0943D 0.035129E 0.04029F 0.0455UNMARKED0.01897TOTAL HOLES269Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7487(408) 432-1900 qFAX : (408) 434-0507 qTELEX : 499-3977© PC FAB DRAWI GUA DAFEX8EX5F FF FAE X 14D X 128B C CC BEE NOTES:1.MATERIAL IS FR4, 0.062˝ THICK WITH 2 OUNCE COPPER.2.PCB WILL BE DOUBLE-SIDED WITH PLATED THROUGH-HOLES.3.HOLE SIZES ARE AFTER PLATING. PLATED THROUGH-HOLE WALL THICKNESS MINIMUM 0.0014˝ (1OZ.).E PADMASTER PROCESS.5.SOLDER MASK BOTH SIDES WITH PC401 USING FILM PROVIDED.6.SILKSCREEN COMPONENT SIDE USING FILM E WHITE, NON-CONDUCTIVE INK.7.ALL DIMENSIONS ARE IN INCHES.。
LTC4266A Quad LTPoE++ PSE Controller 演示电路 1815A 数据
DC1815A-A DC1815A-B DC1815A-C DC1815A-DDescriptionQuad LTPoE++ PSE ControllerDemonstration circuit 1815A features the L TC®4266A quadpower sourcing equipment (PSE) controller, capable ofdelivering up to 90W of L TPoE++™ power to a compatibleL TPoE++ powered device (PD). A proprietary detection/classification scheme allows mutual identification betweenan L TPoE++ PSE and L TPoE++ PD while remaining com-patible and interoperable with existing Type 1 (13W) andType 2 (25.5W) PDs. The L TC4266A feature set is a supersetof the popular L TC4266. These PSE controllers utilize lowR ON external MOSFETs and 0.25Ω sense resistors whichare especially important at the L TPoE++ current levels tomaintain the lowest possible heat dissipation.The L TC4266A is available in multiple power grades, allow-ing delivered PD power of 13W, 25.5W, 38.7W, 52.7W, 70Wand 90W. The DC1815A has four variations DC1815A-A,DC1815A-B, DC1815A-C, and DC1815A-D which accom-modate the four L TPoE++ power levels (Table 1).Advanced power management features of the L TC4266Ainclude: a 14-bit current monitoring ADC, DAC-program-mable current limit, and versatile quick port shutdown.Advanced power management host software is availableunder a no-cost license. PD discovery uses a proprietarydual mode 4-point detection mechanism ensuring excellent immunity from false PD detection. The L TC4266A includes L, L T, L TC, L TM, Linear Technology and the Linear logo are registered trademarks andL TPoE++ and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.an I2C serial interface operable up to 1MHz. Optional I2C control is accessed on the DC1815A either with test points or a 14-pin ribbon cable for DC590B QuikEval™ GUI operation.The L TC4266A is configurable on the DC1815A as an AUTO pin high, MID pin high, autonomous midspan power injec-tor; input data from an existing network system is sent out, along with power, to a PD. The L TC4266A autonomously detects a PD, turns power on to the port, and discon-nects port power without the need for a microcontroller. OUT n LEDs indicate that port power is present. A single 55V supply is required to power the DC1815A. A simple LDO regulator circuit on the board powers the digital sup-ply of the L TC4266A. A SHDN pushbutton for each port shuts down the respective port and disables detection. Pre-programmed masked shutdown ports are shut down with the MSD pushbutton. A RESET pushbutton resets the L TC4266A to its AUTO pin logic state. Ports shut down with the SHDN or MSD pushbutton must be re-enabled via I2C or a device reset with the AUTO pin high. Design files for this circuit board are available at /demoTable 1. DC1815A Power Levels and Power SupplyDEMO BOARD PSE CONTROLLER MAX DELIVERED PD POWER POWER SUPPL Y*DC1815A-A L TC4266A-138.7W300WDC1815A-B L TC4266A-252.7W300WDC1815A-C L TC4266A-370W420WDC1815A-D L TC4266A-490W540W*Recommended DC1815A power supply minimum to avoid drooping in a worst-case scenario with I LIM current at all four ports. Set the voltage between 54.75V to 57V for L TPoE++ compliance1dc1815afc2dc1815afcDEMO MANUAL DC1815A quick start proceDureFigure 1. DC1815A SetupDemonstration circuit 1815A is easy to set up for evaluat-ing the performance of the L TC4266A. Refer to Figure 1 for proper test equipment setup and follow the procedure below.1. Set MID jumper JP5 to LO which disables midspan mode.2. Set AUTO jumper JP4 to HI which enables AUTO pin high mode.3. Connect a 55V to 57V power supply across AGND (+) and VEE (–). Size the power supply considering the maximum power delivered to the PDs.4. Connect with an Ethernet cable an 802.3at Type 1 or Type 2, or L TPoE ++ compatible PD to one of the four bottom ports of 2x4, RJ45 connector J1.5. (Optional) For data tests, connect a PHY with anEthernet cable to one of the four top ports of 2x4, RJ45 connector J1.6. (Optional) Connect a DC590B via ribbon cable to the DC1814A and via USB to a PC. Open the QuikEval software for I 2C GUI interfacing.3dc1815afcDEMO MANUAL DC1815AoperationIntroductionThe DC1815A demonstrates the features and capabilities of the L TC4266A, a quad controller for L TPoE ++ power sourcing equipment. The DC1815A provides a quick and simple PSE solution requiring only a VEE supply.Supply VoltagesSelect a VEE supply with enough power to sustain all four ports at maximum load. Table 1 shows the maximum delivered PD power of a single port as well as a recom-mended VEE power supply minimum to avoid drooping in a worst-case scenario with I LIM current at all four ports.The L TC4266A also requires a digital 3.3V supply. The DC1815A uses a simple LDO regulator circuit to power the 3.3V digital supply from the VEE supply. The L TC4266A VDD supply is allowed to be within 5V above or below AGND. On the DC1815A, VDD is tied to AGND and DGND is a negative voltage below AGND. D1, R5, Q5, R14, R15, and R25 generate the negative voltage referenced to AGND (Figure 2). These components are sized to handle the power required to supply the L TC4266A and LEDs on the DC1815A. Contact Linear Technology Applications for 3.3V options.AUTO PinThe L TC4266A AUTO pin is set high or low with jumper JP4 on the DC1815A. With the AUTO pin high after a device reset or power on, the L TC4266A operates in fully autonomous mode without the need for a microcontroller . The L TC4266A will automatically detect, classify, and power on IEEE 802.3at Type 1, Type 2 and L TPoE ++ PDs up to the power level rating of the L TC4266A version used. For full control via I 2C, the AUTO pin is to be pulled low. Modification of the AUTO pin jumper requires a device reset or power cycle.Endpoint vs MidspanThe L TC4266A can be configured either for endpoint or midspan operation by setting the MID pin high or low respectively. This is selected with jumper JP5 on the DC1815A. The MID pin high state enables a two second detection back-off timer . The L TC4266A must be reset or power-cycled for the MID pin to be detected. For proper midspan operation the AUTO pin must also be high.I 2C ControlThe L TC4266A is a slave-only I 2C device, and commu-nicates with a host using a standard SMBus/I 2C 2-wire interface. On the DC1815A, a host can be connected to the SCL and SDA test points. Optionally, a DC590B board can be connected with a 14-pin ribbon cable to header J6.The L TC4266A has separate pins for SDAIN and SDAOUT to facilitate the use of opto-couplers. The SDAIN and SDAOUT lines are tied together on the DC1815A with a shunt resis-tor (R10) to provide a traditional bi-directional SDA line. The 7-bit I 2C address of the L TC4266A is 010A 3A 2A 1A 0b, where A 3 through A 0 are determined by pins AD3 through AD0 respectively. On the DC1815A board the state of these pins are controlled by the quad DIP switch, S1. All L TC4266 chips also respond to the global address 0110000b regardless of the state of their AD3-AD0 pins.Interrupts are signaled by the L TC4266A to the host via the INT pin. A red LED on the DC1815A indicates if the INT line is being pulled low.Figure 2. DC1815A LDO Circuit for the LTC4266A Digital Supply.4dc1815afcDEMO MANUAL DC1815A operationBoard LayoutProper components placement and board layout with the L TC4266A is important to provide electrical robustness and correct operation. The following mentioned components, also shown in Figure 3, must be close to their respective L TC4266A pins with no other components in between on the connection path. Place a 0.1µF capacitor (C1) directly across VDD and DGND. Place a 1µF , 100V capacitor (C4) and a SMAJ58A TVS (D3) directly across AGND and VEE. Place the OUT 0.22µF , 100V capacitors (C22, C36, C47, and C58) directly to their respective OUT pins all going to an AGND plane.The power path is from VEE to the sense resistor , to the MOSFET , and out to the port. Select a trace width appro-priate for the maximum current.Kelvin sensing is necessary to provide accurate current readings particularly with DC Disconnect. The sense resis-tors used with the L TC4266A must be 0.25Ω, 1% or better , and with a power rating that can handle the maximum DC current passed through them. A dedicated sense trace from each SENSE pin of the L TC4266A must go directly to the respective sense resistor solder pad (Figure 4). Do not connect to a copper area or trace between the sense resistor and the MOSFET .Figure 3. L TC4266A Key Application Componentsfor Board PlacementThe VEE side of the sense resistor must connect to a thick VEE plane through several large vias. At the L TC4266A, the VEE pins and exposed pad tie together on the top layer and connect to the VEE plane as well through its own multiple large vias. The via size, number of vias, copper thickness, trace width, and number of layers that connect VEE between the sense resistors and the L TC4266A VEE pins must total less than 15mΩ. A 2oz. copper thickness for the VEE copper plane must be used if there is only a single VEE plane connecting the L TC4266A VEE pins to the sense resistors.The VEE current path from the sense resistors to the main VEE power supply must be either through a copper plane, or a thick trace. If a trace is used, it must not pass under the L TC4266A. Instead the path must go out to VEE from the sense resistors as shown in Figure 4. The VEE connection is from the VEE supply to the sense resistors to the L TC4266A VEE pins and must stay in that order.Figure 4. L TC4266A VEE Pins and Sense Resistors Connect to a VEE Inner Layer Plane. A Kelvin Sense T race from each SENSE Pin Runs to the Respective Sense Resistor Pad. Connect the VEE Supply Path to the Sense Resistors First, Then to the L TC4266AVEE PinsDEMO MANUAL DC1815A operationWhen laying out multiple L TC4266A devices, group the four sets of port MOSFET and sense resistor with their respective L TC4266A as shown in Figure 5. Each L TC4266A has its own copper fill area on the surface that connects to the VEE plane with multiple large vias. The net effect is to reduce the layout problem down to 4-port groups;this arrangement is expandable to any number of ports.Figure 5. Multiple L TC4266 Layout Strategyto Reduce Mutual ResistancepcB LayoutTop SilkscreenLayer 1: Top Layer5dc1815afc6dc1815afcDEMO MANUAL DC1815A pcB LayoutLayer 2: Plane LayerLayer 3: Plane LayerLayer 4: Bottom LayerBottom SilkscreenDEMO MANUAL DC1815A parts ListITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 12C4, C65CAP, 0603 0.1µF 10% 25V X7R TDK C1608X7R1E104K216CT1-CT16CAP, 0805 0.01µF 5% 100V X7R AVX 0805C103JAT2A32C64, C66CAP, 0805 1µF 10% 100V X7S TDK C2012X7S2A105K41C2CAP, 10uF 20% 100V ALUM.PANASONIC EEE-2AA100UP 54C22, C36, C47, C58CAP, 1206 0.22µF 5% 100V X7R AVX 12061C224JAT2A610C5, C6, CG1-CG8CAP, 1808 1000pF 10% 2KV X7R TDK C4520X7R3D102K72J2, J3CONN, JACK, BANANA KEYSTONE 575-481J1CONN, RJ45, 8-PORT DUAL ROW SHIELDED TE CONNECTIVITY, 5569262-1 91CLD1DIODE, CURRENT LIMITING, 2.7mA, SOD-80CENTRAL SEMI CCLM2700108D8-D11, D24-D27DIODE, RECTIFIER, 100V 1A, SMA FAIRCHILD S1B111D3DIODE, TVS, 400W, 58V, SMA DIODES INC. SMAJ58A122D18, D20DIODE, TVS, 5000W, 60V, SMC LITTLEFUSE 5.0SMDJ60A131D1DIODE, ZENER 3.9V SOD-123ON SEMI, MMSZ4686T1G141D23DIODE, ZENER, 5.6V, SOT23FAIRCHILD, BZX84C5V6151J6HEADER, 2 × 7 2mm MOLEX 87831-1420162JP4, JP5HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S171U3IC, 24LC025, EEPROM, TSSOP MICROCHIP 24LC025-I/ST182D5, D7LED, AMBER ROHM SML-010DTT86L194D12-D15LED, GREEN ROHM SML-010FTT86L201D6LED, RED ROHM SML-010VTT86L2116F-1-F16FUSE, 3A, 63VDC 1206BEL FUSE C1Q3221R9RES, 0603 1Ω 5% 1/10W VISHAY CRCW06031R00JNEA231R10RES, 0603 10Ω 5% 1/10W VISHAY CRCW060310R0JNEA241R5RES, 0603 100k 5% 1/10W VISHAY CRCW0603100KJNEA252R1, R2RES, 0603 10k 5% 1/10W VISHAY CRCW060310K0JNEA266R8, R13, R18, R21, R24, RL1RES, 0603 1.0k 5% 1/10W VISHAY CRCW06031K00JNEA274R7, R17, R20, R23RES, 0603 10M 5% 1/10W VISHAY CRCW060310M0JNEA284R6, R16, R19, R22RES, 0603 2M 5% 1/10W VISHAY CRCW0603910KJNEA293REP3-REP5RES, 0603 5.1k 5% 1/10W VISHAY CRCW06035K10JNEA3032RT1-RT32RES, 0603 75Ω 5% 1/10W VISHAY CRCW060375R0JNEA313R14, R15, R25RES, 1206 4.7k 5% 1/4W VISHAY CRCW12064K70JNEA324RS1-RS4RES, 2512, 0.25Ω 1% 2W STACKPOLE, CSRN2512FKR250334MH1-MH4STAND-OFF, NYLON 0.75"KEYSTONE, 8834(SNAP ON)341S1SWITCH, DIP 4-POSITION TYCO/ALCOSWITCH ADE04356S2-S7SWITCH, MOMENTARY WÜRTH 434 123 050 8163616E1-E16TESTPOINT, TURRET, 0.094" PBF MILL-MAX, 2501-2-00-80-00-00-07-0374T1-T4TRANSFORMER, POE++(OPTION)MIDCOM WÜRTH 749022016 COILCRAFT ETH1-460L384Q9-Q12XSTR, MOSFET P-CHANNEL 30V (D-S), SOT-23VISHAY Si2343DS394Q1-Q4XSTR, MOSFET, N-CHANNEL 100V FAIRCHILD FDMC86102401Q5XSTR, PNP, 100V, SOT223ZETEX ZXTP19100CG7dc1815afcDEMO MANUAL DC1815Aparts ListITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 413XJP4, XJP5SHUNT, 2mm SAMTEC 2SN-BK-G421FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1815A-2432STENCIL TOP & BOTTOM DC1815A-2DC1815A-A11DC1815A GENERAL BOM216FB1-FB16FERRITE BEAD, 1k, 0805TDK MPZ2012S102A31U1IC, L TC4274A-1, QUAD PORT 38.7W PSE CONTROLLER LINEAR L TC4274AIUHF-141FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1815ADC1815A-B11DC1815A GENERAL BOM216FB1-FB16FERRITE BEAD, 1k, 0805TDK MPZ2012S102A31U1IC, L TC4266A-2 QUAD PORT 52.7W PSE CONTROLLER LINEAR L TC4266AIUHF-241FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1815ADC1815A-C11DC1815A GENERAL BOM216FB1-FB16FERRITE BEAD, 1k, 0805TDK MPZ2012S102A31U1IC, L TC4266A-3, QUAD PORT 70W PSE CONTROLLER LINEAR L TC4266AIUHF-341FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1815ADC1815A-D11DC1815A GENERAL BOM216FB1-FB16FERRITE BEAD, 1300Ω, 1812TAIYO YUDEN FBMH4532HM132-T 31U1IC, L TC4266A-4, QUAD PORT 90W PSE CONTROLLER LINEAR L TC4266AIUHF-441FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1815A8dc1815afcDEMO MANUAL DC1815A schematic Diagram9DEMO MANUAL DC1815Aschematic Diagram10dc1815afcDEMO MANUAL DC1815A schematic Diagram1112dc1815afcDEMO MANUAL DC1815ALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX : (408) 434-0507 ● www.linear .comLINEAR TECHNOLOGY CORPORA TION 2011LT 0613 REV C • PRINTED IN USADEMONSTRATION BOARD IMPORTANT NOTICELinear Technology Corporation (L TC) provides the enclosed product(s) under the following AS IS conditions:This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONL Y and is not provided by L TC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT , SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.The user assumes all responsibility and liability for proper and safe handling of the goods. Further , the user releases L TC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).No License is granted under any patent right or other intellectual property whatsoever. L TC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.L TC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive .Please read the DEMO BOARD manual prior to handling the product . Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged .This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a L TC applica-tion engineer .Mailing Address:Linear Technology 1630 McCarthy pitas, CA 95035Copyright © 2004, Linear Technology CorporationDC1815A-A DC1815A-B DC1815A-C DC1815A-D。
LTC3862-2管脚
Vin
主电源输入
21
RUN
运行控制输入，当引脚电压大于1.22v，芯片工作
22
SENSE1+
同SENSE2+
23
SENSE1-
同SENSE2-
24
3V8
内部LDO的3.8V输出。
电流比较器负极输入
15
NC
悬空
16
GATE2
门极驱动信号输出，CH2
17
PGND
电源地
GATE1
门极驱动信号输出，CH1。Ltc3862-2提供参考PGND 10V的门极驱动来驱动高电压MOSFET。GATE1的额定绝对最大电压在-0.3v到11v之间。
19
INTVCC
内部LDO(低差压线性稳压器)的10v输出。一个我低ESR 4.7uF陶瓷旁路电容应连接在INTVcc和PGND之间，尽量靠近IC。
引脚号
引脚名称
引脚功能
1
Dmax
最大占空比控制引脚。此引脚悬浮输出驱动信号最大占空比为84%，接3V8为75%，接SGND为96%。
2
SLOPE
控制内部电流环的斜坡增益引脚。此引脚悬浮归一化斜率补偿增益为1，接3V8斜率补偿增益增加66%，接SGND减少37.5%。
3
BLANK
消隐事件引脚。此引脚悬浮最小导通时间为290ns，接3V8为375ns，接SGND为210ns。
4
PHASEMODE
此引脚电压控制两相通道(CH1、CH2)信号，以及通道1(CH1)与时钟输出(CLKOUT)的相位关系。悬浮此引脚、连接到3V8、SGND会改变CH1\CH2\CLKOUT的相位关系。
5
FREQ
LTC2612IMS8中文资料
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 12 12
LTC2622 TYP MAX
MIN 14 14
LTC2612 TYP MAX
MIN 16 16
LTC2602 TYP MAX
UNITS Bits Bits
± 0.5 ± 0.75 ±4 ±3 0.1 0.2 0.2 0.4 1 ±1 ±5
元器件交易网
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP
FEATURES
s
DESCRIPTIO
s s s s s s s s s
U APPLICATIO S
s s s s
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
VCC = 5V, VREF = 4.096V Code = 0 q VCC = 5V, VREF = 4.096V, (Note 7) q
± 0.1 ±0.7 ±3
± 0.1 ±0.7 ±3
2
U
LSB LSB
2602f
W
U
U
W WБайду номын сангаас
W
元器件交易网
新晔电子 NCP1562 中文说明书
Characteristic
Symbol
Min
Typ
Max
Unit
STARTUP CONTROL AND VAUX REGULATOR
VAUX Regulation (VUVOV = 0 V) Inhibit Threshold Voltage
Startup Threshold/VAUX Regulation Peak (VAUX Increasing) Operating VAUX Valley Voltage
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 100 V.
2. This device contains Latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
1. This device series contains ESD protection and exceeds the following tests:
Pins 2−16:
Human Body Model 2000 V per MIL–STD–883, Method 3015.
Machine Model Method 160 V.
5.0 V Reference Output Current
单片机及图像识别技术下心肌梗死监测与甄别系统的设计
Science &Technology Vision科技视界0引言,、[1]。
,,。
2013,54.4,1[2]。
,,,。
,,,。
、,,、、、,。
,,,,。
STM32L476,、、、A/D ,,,Ⅰ、(CK-MB)[3]。
,,。
1。
图1总体结构图1硬件设计、、、A/D 、、。
、,;,;A/D ,。
,单片机及图像识别技术下心肌梗死监测与甄别系统的设计曹璐莹张艳敏朱淑芳郭冰艳(新乡医学院三全学院,河南新乡453003)【摘要】心肌梗死在老年人群中是一种主要的疾病,但由于前期症状易于与其他常见病状混淆从而延误最佳治疗时间。
目前市场上的心率监测及预警的可穿戴设备大多不可作为临床依据,即针对心肌梗死以及防猝死装置仍无有效的预警设计。
为解决以上问题,文章在分析了目前市场上现有设备的背景下,提出了一种基于单片机及图像识别技术的心梗监测及甄别预警系统,该系统融入了磁性免疫层析试纸条,通过心梗三项标记物的测量,以达到临床诊断快速、精确、定量检测的效果。
【关键词】单片机技术;图像识别;磁性免疫层析试纸;心梗预警中图分类号:R542.22;R541.7文献标识码:ADOI:10.19694/ki.issn2095-2457.2022.16.16※基金项目:2020年新乡医学院三全学院“优秀青年教师培养计划”。
*通信作者:曹璐莹,硕士,研究方向为医学仪器、医学图像分析、智能医学。
50Science &Technology Vision 科技视界,,5,,,,1~3mL 。
2。
图2系统硬件框图1.1微处理器,、,。
,,STM32L476(),,[4],、,,。
3。
图3内部管脚图1.2生理信号采集模块,,、,,。
,。
,。
4。
1.3放大电路模块,,,。
AD797,、,(0.9n V/Hz)(-120d B),(20V/μs)(110MHz),16[5]。
5。
图5放大电路图4信号引入电路51Science &Technology Vision科技视界1.4滤波电路模块,,,,。
有源参差带通滤波器设计
有源参差带通滤波器设计
卢容德;易国华
【期刊名称】《长江大学学报（自然版）理工卷》
【年(卷),期】2005(002)001
【摘要】将参差调谐放大器的理论与设计方法移植到RC带通滤波器中,提出了有源参差带通滤波器的概念及设计方法,给高阶RC有源带通滤波器的工程设计提供了一种简单易行的方法,并且给出了用EWB进行仿真的结果.
【总页数】4页(P57-60)
【作者】卢容德;易国华
【作者单位】长江大学电子信息学院,湖北,荆州,434023;长江大学电子信息学院,湖北,荆州,434023
【正文语种】中文
【中图分类】TN713
【相关文献】
1.参差调谐多路反馈有源带通滤波器的设计和调试 [J], 万国庆
2.基于LTC1562的多通道有源带通滤波器设计与实现 [J], 李伟;石建飞;王文琮
3.椭圆逼近模拟有源带通滤波器设计 [J], 郑成霞
4.音频信号有源带通滤波器设计与电路仿真 [J], 李邵男
5.基于带通滤波器的参差滤波实现高增益宽带有源滤波的方法 [J], 赵辉;张杰因版权原因，仅展示原文概要，查看原文内容请购买。
常用滤波电路
C
C
＋
＋
. Uo
C
C
＋
＋
. Uo
.
. Ui
RR
Ui
RR
(a) 二阶高通滤波电路
(b) 改进型二阶高通滤波电路
16
幅频特性曲线
1+RF/R1
Uo Ui
0.707(1+RF/R1)
0
0
17
• 3、带通滤波电路和带阻滤波电路
• 将截止频率为ωh的低通滤波电路和截止频率为ωl的高通 滤波电路进行不同的组合, 就可获得带通滤波电路和带阻 滤波电路。将一个低通滤波电路和一个高通滤波电路 “串接”组成带通滤波电路, ω＞ωh的信号被低通滤波电 路滤掉, ω＜ωl的信号被高通滤波电路滤掉, 只有当ωl＜ω ＜ωh时信号才能通过, 显然, ωh＞ωl才能组成带通电路。
1
1 jRC
j C
1
1 j
0
0
1 RC
7
Uo
Ui
1
0.707
此电路的缺点： 1、带负载能力差。
0 0
2、无放大作用。
3、特性不理想，边沿不陡。
截止频率
8
通频带宽度(带宽)
Uo
Ui
1
0.707
带宽:0 - 0
1 0 RC
0 0
设R=10k,C为下列各值时
的带宽:
C
fo
1F
16Hz
截止频率
O
高通 l
阻
通
阻
l
h
(a) 带通滤波电路
低通
.
.
Ui
高通
Uo
. A
Au p 1
低通
滤波器交流电参数快速测试技术浅谈
相干多音信号的生成
在测试LTC1562滤波器时，考虑到测试设备（ATE）的硬件能力，我们将LTC1562 配置为中心频率（fo）为10kHz的低通滤波器。为了同时测试带内和衰减带的 特性，设计采用由11个等幅单音正弦信号构成的多音相干复合信号。通过分 析计算，所选用的11个单音信号的频率、相位、傅里叶频率BIN如表1所示。
图1：LTC1562典型应用及频响曲线图（4阶低通滤波器）
3
LTC1562的特点以及滤波器的相关知识
• 图1为采用LTC1562器件构建的双通道4阶巴特沃斯（ BUTTER-WORTH）低通滤波器。左图为滤波器的硬件连接 ：每个4阶滤波器由LTC1562内部两个独立的二阶滤波器级 联实现，仅需要3个电阻（RIN、RQ、R2）即可实现中心频 率（fo）、品质因数（Q）和通带增益（GAIN）的设置， 线路非常简单。
相干多音信号的生成
相干采样(coherent-sampling)：为了避免频谱泄露而采取的一种 采样方法，需要遵守一定的规则。1）采样信号为周期信号 ；2）满足FS/N=FC/M；3）N和M最好互质。
在许多模拟通道器件测试条件中，为了激励器件，需要给DUT 施加相干多音信号。根据下面公式，仅需要通过I个正弦波 简单地相加即可产生这样的复合信号：
基于DSP的滤波器交流电参 数的测试方法浅谈
作者：李 雷
引言
• 对于滤波器增益和频率响应参数的检测，国内生产厂商和检验机构大 多采用基于模拟台式设备（如：扫频仪）的传统测试方法:即通过精密 信号源和RMS-电压表以扫频的方式完成AC参数的测试。
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CONDITIONS VS = ± 2.375V, RL = 5k, CL = 30pF, Outputs at 0V VS = ± 5V, RL = 5k, CL = 30pF, Outputs at 0V VS = ± 2.375V, RL = 5k, CL = 30pF, Outputs at 0V VS = ± 5V, RL = 5k, CL = 30pF, Outputs at 0V
Total Supply Voltage (V + to V –) .............................. 11V Maximum Input Voltage at Any Pin ....................(V – – 0.3V) ≤ V ≤ (V + + 0.3V) Storage Temperature Range ................. – 65°C to 150°C Operating Temperature Range LTC1562C-2 ............................................ 0°C to 70°C LTC1562I-2 ........................................ – 40°C to 85°C Lead Temperature (Soldering, 10 sec).................. 300°C
0.1µF R24 7.87k RQ4 10.2k
VOUT2
U
de Response
100k FREQUENCY (Hz)
1562-2 TA02
U
1M 1.5M
15622fa
1
LTC1562-2
ABSOLUTE
(Note 1)
AXI U
RATI GS
U U W PACKAGE/ORDER I FOR ATIO
TJMAX = 150°C, θJA = 136°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
VS = ± 2.375V, RL = 5k, CL = 30pF VS = ± 5V, RL = 5k, CL = 30pF VS = ± 2.375V, RL = 5k, CL = 30pF, f = 250kHz VS = ± 5V, RL = 5k, CL = 30pF, f = 250kHz VS = ± 2.375V, Input at AGND Voltage VS = ± 5V, Input at AGND Voltage VS = Single 5V Supply VS = ± 5V, V2 Output Has RL = 5k, CL = 30pF VS = ± 2.375V, fIN = 10kHz, V2 Output Has RL = 5k, CL = 30pF VS = ± 2.375V, V2 Output Has RL = 5k, CL = 30pF VS = ± 2.375V, BW = 400kHz, Input AC GND VS = ± 5V, BW = 400kHz, Input AC GND BW = 400kHz, f O = 200kHz, Q = 1, Input AC GND
q q q q
Output Voltage Swing, V2 Outputs Output Voltage Swing, V1 Outputs VOS DC Offset Magnitude, V2 Outputs DC AGND Reference Point Center Frequency (f O) Error (Notes 2, 3) HL Lowpass Passband Gain at V2 Output Q Accuracy Wideband Output Noise Input-Referred Noise, Gain = 100
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The LTC®1562-2 is a low noise, low distortion continuous time filter with rail-to-rail inputs and outputs, optimized for a center frequency (fO) of 20kHz to 300kHz. Unlike most monolithic filters, no clock is needed. Four independent 2nd order filter blocks can be cascaded in any combination, such as one 8th order or two 4th order filters. Each block’s response is programmed with three external resistors for center frequency, Q and gain, using simple design formulas. Each 2nd order block provides lowpass and bandpass outputs. Highpass response is available if an external capacitor replaces one of the resistors. Allpass, notch and elliptic responses can also be realized. The LTC1562-2 is designed for applications where dynamic range is important. For example, by cascading 2nd order sections in pairs, the user can configure the IC as a dual 4th order Butterworth lowpass filter with 90dB signal-to-noise ratio from a single 5V power supply. Low level signals can exploit the built-in gain capability of the LTC1562-2. Varying the gain of a section can achieve a dynamic range as high as 114dB with a ± 5V supply. Other cutoff frequency ranges can be provided upon request. Please contact LTC Marketing.
10 0 –10 –20 –30 –40 –50 –60 –70 –80 50k
RIN4 7.87k
1562-2 TA01
INV B V1 B V2 B
INV C V1 C V2 C
16 V+ LTC1562-2 V – 15 SHDN AGND 13 V2 A V2 D 12 V1 A V1 D 11 INV A INV D
ELECTRICAL CHARACTERISTICS
SYMBOL VS IS PARAMETER Supply Current
The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ± 5V, outputs unloaded, SHDN pin to logic “low”, unless otherwise noted. AC specs are for a single 2nd order section, RIN = R2 = 10.4k ± 0.1%, RQ = 9.09k ± 0.1%, fO = 175kHz.
TOP VIEW INV B V1 B V2 B V –* V+ SHDN V –* V2 A V1 A INV A 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 INV C V1 C V2 C V –* V– AGND V –* V2 D V1 D INV D
LTC1562-2 Very Low Noise, Low Distortion Active RC Quad Universal Filter
FEATURES
s s
DESCRIPTIO
s
s s s s s s s s s
U APPLICATIO S
s s s s
Continuous Time—No Clock Four 2nd Order Filter Sections, 20kHz to 300kHz Center Frequency Butterworth, Chebyshev, Elliptic or Equiripple Delay Response Lowpass, Bandpass, Highpass Responses 99dB Typical S/N, ± 5V Supply (Q = 1) 93dB Typical S/N, Single 5V Supply (Q = 1) Rail-to-Rail Input and Output Voltages DC Accurate to 3mV (Typ) ± 0.5% Typical Center Frequency Accuracy “Zero-Power” Shutdown Mode Single or Dual Supply, 5V to 10V Total Resistor-Programmable fO, Q, Gain