Chapter 2 VHDL Models

2.1.3 Event Scheduling The assignment to signal x does not happen instantly. Each of the values assigned to signal x contain an AFTER clause. The mechanism for delaying the new value is called scheduling an event.
Example 2.6 3-input AND gate entity andgate is port(a, b, c: in bit; x: out bit); end andgate; architecture structure of andgate is begin x<=a and b and c; end structure;
Example 2.11 Better multiple driver model
architecture better of multiplexer is begin q <= i0 when a = ‘0’ and b = ‘0’ else i1 when a = ‘1’ and b = ‘0’ else i2 when a = ‘0’ and b = ‘1’ else i3 when a = ‘1’ and b = ‘1’ else ‘X’; end better;
Example 2.10 Bad multiple driver model library IEEE; use IEEE.std_logic_1164.all; entity multiplexer is port (i0, i1, i2, i3, a, b : in std_ulogic; q : out std_ulogic); end multiplexer; architecture bad of multiplexer is begin q <= i0 when a = ‘0’ and b = ‘0’ else ‘0’; q <= i1 when a = ‘1’ and b = ‘0’ else ‘0’; q <= i2 when a = ‘0’ and b = ‘1’ else ‘0’; q <= i3 when a = ‘1’ and b = ‘1’ else ‘0’; end bad;
2.4 Signal assignments
2.4.1 Signal delays
There are two kinds of delays: inertial delay and transport delay. Inertial: b <= a AFTER 20 ns; Transport: b <= TRANSPORT a AFTER 20 ns;
Example 2.1 Entity of two-input AND gate entity and2 is port( x, y : in bit; z: out bit); end entity and2; Example 2.2 Entity of 1-OF-4 multiplexer entity mux is port( a, b, c, d : in bit; s0, s1: in bit; x : out bit); end mux;
Each VHDL file should include a header. -------------------------------------------------------------------- Design unit : andgate(structure) -- File name : andgate.vhd -- Description : Two-input and gate -- Limitations : None lists -- System : VHDL'93 -- Author : Fan Bishuang -- Email : fbshfj@ -- Revision : Version 1.0 16/5/06 -------------------------------------------------------------------
Chapter 2 VHDL Models
VHDL terms: Entity Architecture Configuration Package Driver Bus Attribute Generic Process
2.1 Entities and architectures
2.1.1Entities
architecture and2_gate of and2 is signal internal : bit; begin internal <= a and b; c <= internal after (rise + (load * 2 ns)) when internal = ‘1’ else internal after (fall + (load * 3 ns)); end and2_gate;
2.1.2 Architectures
Example 2.3 Architecture of two-input AND gate architecture ex1 of and2 is begin z <= x and y; end architecture ex1; Example 2.4 Architecture of 1-OF-4 multiplexer ARCHITECTURE dataflow OF mux IS SIGNAL s : INTEGER RANGE 0 TO 3; BEGIN s <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE 1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE 2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE 3; x <=a AFTER 0.5 NS WHEN s = 0 ELSE b AFTER 0.5 NS WHEN s = 1 ELSE c AFTER 0.5 NS WHEN s = 2 ELSE d AFTER 0.5 NS; END dataflow;
Inertial delay of 20 ns
Transport delay of 20 ns
2.4.2 Drivers Drivers are sources on signals.
Example 2.9 A signal with two drivers architecture test of test is begin a <= b after 10 ns; a <= c after 10 ns; end test; Synthesizing the example would short c and b together.
2.5 Generiபைடு நூலகம்s
Generics are parameters that are used to pass information into entities. z <= x and y after 5 ns; z <= x and y after delay; Example 2.12 2-input AND gate delay entity and2 is generic(rise, fall : time; load : integer); port(a, b : in bit; c : out bit); end and2;
2.3 Netlists Example 2.5 inverter entity inverter is port (a: in bit; x: out bit); end inverter; architecture structure of inverter is begin x <= not a; end structure;
2.1.3 Concurrent Signal Assignment Inside a VHDL architecture, there is no specified ordering of the assignment statements. The order of execution is solely specified by events occurring on signals that the assignment statements are sensitive to. An event on a signal is a change in the value of that signal.
component orgate port(a, b, c, d : in bit; x : out bit); end component; signal s0_inv, s1_inv, x1, x2, x3, x4 : bit; begin g1 : inverter port map (s0, s0_inv); g2 : inverter port map (s1, s1_inv); g3 : andgate port map (a, s0_inv, s1_inv, x1); g4 : andgate port map (b, s0, s1_inv, x2); g5 : andgate port map (c, s0_inv, s1, x3); g6 : andgate port map (d, s0, s1, x4); g7 : orgate port map (x2 => b, x1 => a, x4 => d, x3 => c, x => x); end netlist;
2.2 Identifiers, spaces and comments • VHDL is not case sensitive(unlike C). • Identifiers may consist of letters, numbers and underscores(‘_’), but the first character must be a letter and two underscores in succession are not allowed. Reserved words(entity, architecture, is, begin, port and so on) can not be identifiers. • There is no difference between one whitespace character and many.