巴克码序列检测

设计范例(续)
state_comb: Process (present_state, Xi) begin case Present_state is when S0 => Z <= ' 0 '; if Xi =' 1' then next_state <= S l; else next_state <= S0; end if; when Sl => Z <= ' 0 '; if Xi = ' l ' then next_state <= S2; else next_state <= S0; end if; When S2 => Z <= ' 0'; if Xi = ' l ' then next_state <= S3; else next_state <= S0; end if; when S3 => Z <=' 0‘; if Xi =' l ' then next_state <= S3; else next_state <= S4; end if; when S4 => Z <= ' 0‘; if Xi =' l ' then next_state <= S l; else next_state <= S5; end if;
双进程状态机模型
输出信号 外界输入信号
下一状态
当前状态信号
状态 译码 PROCESS1
下一状态
状态 当前状态信号2
END
state_clk: process (clk) begin if (clk'event and clk =' l ' ) ) then present_state <= next_state; end if; end process state_clk; end archjcq;
波形仿真
序列检测器仿真波形
设计范例(续)
when S5 => Z <= ' 0 '; if Xi =' l ' then next_state <= S6; else next_state <= S0; end if; when S6 => Z <= ' 0'; if Xi = ' l ' then next_state <= S2; else next_state <= S7; end if; when S7=> Z <=' l '; if Xi = ' 1 ' then next_state <= Sl ; else next_state <= S0; end if; end case; end process state_comb;
巴克码序列检测器设计
物理与电子工程学院 廖磊
设计要求
某通信接收机的同步信号为巴克码 1110010。 设计一个检测器，其输入位串行码x，输 出位检测结果y，当检测到巴克码时，输 出1。
巴克码序列检测器状态转换图
设计范例
library ieee; use ieee.std_logic_ll64.all; entity jcq is port (clk, Xi: in std_logic; Z: out stdJogic ); end jcq; architecture archjcq of jcq is type StateType is (S0, Sl, S2, S3, S4, S5, S6, S7); signal present_state, next_stat: StateTyPe; begin