位同步的FPGA实现

摘要

同步是通信系统中很重要的一个过程，它可以使通信系统更稳定、更可靠、更准确，它是数字通信系统有顺序进行的技术支撑。同步分为位同步、帧同步和载波同步，我们对数字通信信号的同步除了载波同步和帧同步之外，还要进行位同步。位同步也就是保证接收端准确有效抽样判决数字基带信号序列的基础，一般位同步信号从解调后的基带信号中提取出来，同时也可以从已调频带信号当中直接提取位同步信号，一般可以进行一元中央位置采样的决定，最好是在接收元素结束时间采样的决定。位同步有插入导频法（一种外同步法）和直接法（一种自同步法），本文运用了数字锁相法提取位同步电路的方案，以大规模可编程逻辑器件FPGA为主控制器，以VHDL硬件描述语言为主要语言对其进行在线编程，在QuartusⅡ软件工具中进行仿真和调试，以达到功耗低、成本低、效率高的技术要求。

关键词：位同步；数字锁相电路；FPGA；VHDL；QuartusⅡ

ABSTRACT

Synchronization is a very important process in communication system, it can make the system more stable, more reliable, more accurate, it is the digital communication system has the technical support of the order. Synchronization is divided into bit synchronization, frame synchronization and carrier synchronization, we on the digital communication signal in addition to frame and carrier synchronization and bit synchronization. Bit synchronization is the basis to ensure the correct and effective decision receiver sampling digital baseband signal sequence,general synchronization signal is extracted from the baseband demodulated signals, but also can directly extract bit synchronization signal from the frequency band signal has, in general can be a central position sampling decisions, preferably in the receiving elements in the end time sampling decision. Bit synchronization is the pilot insertion method (a kind of external synchronization method) and direct method (a self synchronizing method), this paper uses digital PLL method of bit synchronization circuit extraction, with the large-scale programmable logic device FPGA as the main controller, using the VHDL hardware description language is the main language of the online programming, simulation and debugging in QuartusⅡsoftware tools, to meet the requirements of low power consumption, low cost, high efficiency technology

Keywords: Bit synchronization (symbol extraction process); digital phase locked loop circuit (bit synchronization circuit); FPGA; VHDL; QuartusⅡ

目录

摘要........................................................................................................................... I ABSTRACT.................................................................................................................... II 第1章绪论.. (1)

第2章同步技术 (3)

2.1 同步技术 (3)

2.2 同步的分类 (3)

2.3 位同步 (3)

2.3.1 位同步方法 (4)

2.3.2 位同步系统性能指标 (5)

第3章基于FPGA设计流程的介绍 (7)

3.1 FPGA器件概述 (7)

3.2 FPGA设计操作流程 (7)

第4章微分型位同步的FPGA实现 (11)

4.1 微分型位同步原理 (11)

4.2 微分鉴相模块的VHDL实现 (12)

4.3 双相时钟信号的VHDL实现 (16)

4.4 单稳触发器的VHDL实现 (17)

4.5 控制及分频模块的VHDL实现 (19)

第5章系统仿真与结果分析 (21)

5.1 顶层模块的VHDL实现 (21)

5.2 系统的整体仿真与结果分析 (24)

结论 (25)

参考文献 (26)

致谢 (27)