大马士革工艺
合集下载
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Three damascene structures were proposed
R. H. HAVEMANN,PROCEEDINGS O THE IEEE, VOL. 89, NO. 5, MAY 200
Damascene structures
Damascene structures may change
n
Barrier
n n
n
D源自文库electric
n n n
Cu/Low k Damascene Process
Cu interconnect integration technology is an innovation of IC technology
Solution of Cu interconnect
qDamascene Structure and Process for the pattern qBarrier Layer Technology for the contamination CMP process is the technology basis
Cu/Low k Damascene Process
Cu/Low k Damascene Process
R. H. HAVEMANN,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001
Cu Interconnect Integration Process Flowchart
Cu/low k Technology Challenge
qProcess
ØDeposition ØEtch
qReliability
R. H. HAVEMANN,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001
Damascene structures
n n
n
the approach to photoresist stripping The subsequent cleaning for interconnect layers.
Global Interconnect Materials
n
Conductor
n n
Tungsten Copper Ta, TaN, TaSiN, W, WN, WSiN by PVD Ta, TaN, TaSiN, W, WN, WSiN by CVD, ALD or other Low ? (k<4) for interlayer dielectrics Standard k (k=4~10) for etch stop dielectrics High k (k>20) for decoupling capacitor
Interconnect Materials and Process 2.The Trends of IC and Interconnect
Cu/Low k Damascene Process Characteristics of Cu interconnect
qLow resistivity of Cu Conductor qHigh Electro- and Stress-Migrate Reliability qCopper readily diffuses into silicon and most dielectrics qTraditional RIE is not practical for Cu etching
R. H. HAVEMANN,PROCEEDINGS O THE IEEE, VOL. 89, NO. 5, MAY 200
Damascene structures
Damascene structures may change
n
Barrier
n n
n
D源自文库electric
n n n
Cu/Low k Damascene Process
Cu interconnect integration technology is an innovation of IC technology
Solution of Cu interconnect
qDamascene Structure and Process for the pattern qBarrier Layer Technology for the contamination CMP process is the technology basis
Cu/Low k Damascene Process
Cu/Low k Damascene Process
R. H. HAVEMANN,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001
Cu Interconnect Integration Process Flowchart
Cu/low k Technology Challenge
qProcess
ØDeposition ØEtch
qReliability
R. H. HAVEMANN,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001
Damascene structures
n n
n
the approach to photoresist stripping The subsequent cleaning for interconnect layers.
Global Interconnect Materials
n
Conductor
n n
Tungsten Copper Ta, TaN, TaSiN, W, WN, WSiN by PVD Ta, TaN, TaSiN, W, WN, WSiN by CVD, ALD or other Low ? (k<4) for interlayer dielectrics Standard k (k=4~10) for etch stop dielectrics High k (k>20) for decoupling capacitor
Interconnect Materials and Process 2.The Trends of IC and Interconnect
Cu/Low k Damascene Process Characteristics of Cu interconnect
qLow resistivity of Cu Conductor qHigh Electro- and Stress-Migrate Reliability qCopper readily diffuses into silicon and most dielectrics qTraditional RIE is not practical for Cu etching