[整理]Cadence教程.
cadence教程
cadence教程Cadence 是一款流行的电路设计和仿真工具。
它广泛应用于电子工程领域，可以帮助工程师进行电路设计、布局、仿真和验证。
以下是一个简单的 Cadence 教程，帮助你快速入门使用该软件。
第一步: 下载和安装 Cadence首先，你需要从 Cadence 官方网站下载适用于你操作系统的Cadence 软件安装包。
在下载完成后，双击安装包文件并按照安装向导的指示进行安装。
第二步: 创建新项目打开 Cadence 软件后，你将看到一个初始界面。
点击“File”菜单，然后选择“New”来创建一个新的项目。
第三步: 添加电路元件在新项目中，你可以开始添加电路元件。
点击菜单栏上的“Library”按钮，然后选择“Add Library”来添加一个元件库。
接下来，使用菜单栏上的“Place”按钮来添加所需的电路元件。
第四步: 连接电路元件一旦添加了电路元件，你需要使用连线工具来连接它们。
点击菜单栏上的“Place Wire”按钮，然后将鼠标指针移到一个元件的引脚上。
点击引脚，然后按照电路的设计布局开始连接其他元件。
第五步: 设置仿真参数在完成电路布局后，你需要设置仿真参数。
点击菜单栏上的“Simulate”按钮，然后选择“Configure”来设置仿真器类型、仿真时间等参数。
第六步: 运行仿真设置完成后，你可以点击菜单栏上的“Simulate”按钮，然后选择“Run”来运行仿真。
仿真过程会模拟电路的运行情况，并生成相应的结果。
总结通过这个简单的 Cadence 教程，你了解了如何下载安装Cadence 软件、创建新项目、添加电路元件、连接元件、设置仿真参数和运行仿真。
掌握了这些基本操作后，你可以进一步学习和探索 Cadence 的更多功能和高级技巧。
祝你在使用Cadence 中取得成功！。
cadence入门教程
Cadence 系列软件从schematic到layout入门一．客户端软件使用及icfb启动要使用工作站上的软件，我们必须在PC中使用xwinpro等工具连接到工作站上。
从开始菜单中，运行xwinpro的xSettings,按照下图设置：点击上图的Settings在出现的窗口中按如下设置（connect host选择为192.168.1.137）：设置完后，从开始菜单中运行xwinpro的xsessions,应该就可以进入登陆界面，用户名为user1,密码为root。
二、SchematicCadence系列软件包含了电路图工具Schematic，晶体管级电路仿真工具Spectre，以及版图工具Virtuoso等。
一般来说，我们先用Schematic画好电路原理图然后进行仿真，最后用Virtuoso手动画版图或者直接进行版图综合，最后对版图进行L VS,DRC等验证。
在登陆进工作站后，点击鼠标右键，选择tools——>terminal，在弹出的terminal窗口中敲入命令icfb&就可以启动cadence了。
图1 icfb的主界面我们以建立一个反相器电路为例子：在icfb中，任何一个电路，不论是已经存在的可以引用的库，还是用户新建立的一个电路，都是一个library. 一个library一般有若干个Cell(单元电路)，每个cell有若干个schematic(电路原理)和若干个layout（版图）。
所以，我们要做的第一步，就是先创建一个自己的“库”，File菜单->new->library图2 新建一个库的界面从这个新建一个library的界面，我们必须输入新建立的库的名称，并且选择好这个库应该存放的目录，然后注意看右边的三个选项，关于新建立的库是否需要链接到Technology File 的问题。
首先，这个Technology File一般是指工艺库，由Foundry提供。
(整理)Cadence_SPB16.2入门教程——PCB布线.
Cadence_SPB16.2入门教程——PCB布线（一）PCB布线4.1 PCB层叠结构层叠结构是一个非常重要的问题，不可忽视，一般选择层叠结构考虑以下原则：·元件面下面（第二层）为地平面，提供器件屏蔽层以及为顶层布线提供参考平面；·所有信号层尽可能与地平面相邻；·尽量避免两信号层直接相邻；·主电源尽可能与其对应地相邻；·兼顾层压结构对称。
对于母板的层排布，现有母板很难控制平行长距离布线，对于板级工作频率在 50MHZ以上的（50MHZ以下的情况可参照，适当放宽），建议排布原则：·元件面、焊接面为完整的地平面（屏蔽）；·无相邻平行布线层；·所有信号层尽可能与地平面相邻；·关键信号与地层相邻，不跨分割区。
基于以上原则，对于一个四层板，优先考虑的层叠结构应该是：·S ←信号·G ←地平面·P ←电源层·S ←信号对于一个六层板，最优的层叠结构是：·S1 ←信号·G1 ←地平面·S2 ←信号·G2 ←地平面·P ←电源层·S4 ←信号对于一个八层板，有两种方案：方案 1：方案2：·S1 ←信号S1 ←信号·G1 ←地平面G1 ←地平面·S2 ←信号S2 ←信号·G2 ←地平面P1 ←电源层·P ←电源层G2 ←地平面·S3 ←信号S3 ←信号·G3 ←地平面P2 ←电源层·S4 ←信号S4 ←信号方案2主要是比方案1多了一个电源层，在电源比较多的情况下可以选择方案2。
对于更多层的结构也是按照上面的原则来定，可以参考其它的资料。
下面以SMDK6410核心板(设计为八层板)来设置层叠结构，包括规则设置，PCB布线等。
打开程序->Cadence SPB 16.2->PCB Editor，然后打开在第3 章布局好的PCB文件。
cadence教程
Cadence TutorialI. IntroductionThis tutorial provides an introduction to analog circuit design and simulation with Cadence, and covers the features that are relevant for the homework assignments. The tutorial is divided into the following topics:•Logging on and Starting Cadence•Creating a Designo Creating a new library and cellviewo Placing the Partso Editing the Symbol Propertieso Wiring the Schematico Modifying Wire Attributes•Analyzing the Design and Plotting Resultso Finding the DC Operating Point and performing a DC Sweepo Performing a Transient Analysiso Performing an AC Analysiso Performing a Parametric Sweepo A Note on Measuring Currentso A Note on Plotting•Invoking Cadence Helpo Getting Additional Help with CadenceThroughout the document, the followingII. Logging on and Starting CadenceIn order to use the ECE164-provided installation of Cadence, you either need to be sitting at one of the Linux workstations provided for use by ECE264 students (see the ECE264 website for the locations of these workstations), or you can login remotely to . In either case, you should login with your Open Computing Environment account obtained via Academic Computing Services (ACS).If you wish to login remotely, you will need SSH and X-server software on your local machine. The necessary software is available as part of the operating systems on Sun Workstations, PCs running Linux, and Macintosh computers running OS X. It can be obtained via third parties for computers running Windows. Students who wish to login remotely are responsible for obtaining (if running Windows), learning how to use, and maintaining their own SSH and X-server software.Once you have logged in, open a terminal window if one does not open automatically and type the following in the window:ee264acd ece-cadenceicfb &A window containing text should appear at the bottom of the screen, labeled “icfb - ...”. This is sometimes called the CIW (Command Interpreter Window). A window explaining new features should also come up; in this window, select “Edit > Off at Startup”, and then close it. The CIW window is the main Cadence window, and much useful information is displayed here. If Cadence isn’t doing what you expect, it is often helpful to look here to read the error messages. You may find it helpful to enlarge the window.You now need to bring up the library manager. To do this, select “Tools > Library Manager” in the CIW. A “Library Manager” window appears. Notice the library “ece264lib”.This library contains most if not all of the IC components (e.g., transistors, resistors, etc.) that will be used in this class.II.Creating a DesignThe creation of a simple transistor amplifier is described in this section. The following notational conventions are used in the description:•The text “[LIB]” should be replaced with “164” if you are taking ECE164 and by “264” if you are taking ECE264.•Bracketed letters such as “[a]” denote keyboard shortcuts (bindkeys) which can be used instead of the menus or buttons to accomplish the given task. To use them, place the pointer over the appropriate window and simply press the key. Please note that these bindkeys are case sensitive.For letters enclosed by square brackets such as “[a]”, the pointer must be in a schematic window.For letters enclosed by curly brackets such as “{a}”, the pointer must be in a waveform window. A summary of the most useful bindkeys is listed in Appendix A.Creating a new library and cellview1.Create a new library named “tutorial”:(a)In the CIW, select “File > New > Library”, and a “New Library” windowwill appear.(b)In the “Name” field, enter “tutorial”.(c)Verify that the path (near the bottom of the dialog box) points to your working directory(or wherever you’d like to place all your class libraries). This path will by default pointto the directory from which you invoked Cadence(d)Select the “Don't need a techfile” button, then click “OK”. In the LibraryManager, an entry “tutorial” should appear.2.Create a new schematic cellview in our new library.(a)In the CIW, select “File > New > Cellview...”, and a “Create New File”dialog box appears.(b)Ensure that the “tutorial” is selected for Library Name (by clicking on the squarebutton).Type “tutorial” in the “Cell Name” field as well.(c) Type “schematic” in the “View Name” field.(d)Select “Composer - Schematic” in the “Tool” field if it is not already selected,then click “OK”. An empty schematic window appears.(e)In the schematic window, select “Design > Save”. You have now successfullycreated a cellview.Placing the PartsYou will now place symbols on the Schematic Window as shown in Figure 1.Figure 1: Initial parts placement.1.Find and place the pMOST symbol as follows:(a)With the schematic window active, press “i” on the keyboard. An “Add Instance”dialog box will appear. The “i” key is a bindkey, or shortcut key, to this dialog box.You can also get the same dialog box by click on the “Instance” button on the lefthand side of the schematic window (it looks like a little DIP), or by going to “Add >Instance” in the menu bar (there is an “i” next to this menu selection, notice). Thereare many shortcuts like this throughout Cadence, and you can create more if you wish -see the online help. Note also that at the bottom of the schematic window and the CIW,the instructions “Point at location for the instance” appears, along withinformation about what the mouse buttons do: “mouse L: ...”. It’s often importantto look at these messages to figure out what is going to happen when you press theleft/middle/right mouse buttons. The mouse buttons are bound to Skill functions, but canbe reconfigured - see the online help for more details.(b)In the dialog box Library field, enter “ece[LIB]lib”. For Cell, enter “pmos4”. ForView, enter “symbol”. You can also use the Browse button to invoke the LibraryBrowser to find a part.(c)When you move the mouse over the schematic window, you will see the outline of a 4-terminal pMOST. Move the cursor to the desired location and press the left mousebutton. Repeat for the other pMOST transistor.(d)To stop placing pMOST symbols, press “ESC” on the keyboard (with the SchematicWindow active), or click the “Cancel” button in the Add Instance dialog box.2.Place an nMOST using a similar procedure. This time, try using the Library Browser to place the“nmos4” symbol. Position it relative to the pMOST symbols as shown in Figure 1, then press “ESC” to get rid of the Add Instance window.3.Next, place the DC Current Source symbol as follows:(a)Press “i” as before, then click “Browse” to bring up the Library Browser.(b)Select “ece[LIB]lib” in the Browser library list, then find the “idc” componentsymbol using the scroll bar. Highlight this component in the browser by left-clicking on“idc”. Sometimes you may need to specify that you want to place the “symbol”version of this part.(c)Move the mouse over the schematic window and place it in the desired location. Don’tpress “ESC” yet.4.Go back to the Library Browser and find the “vdc” part. Place it.5.Similarly, place the “vsin”, “res”, and five copies of “gnd”. Finally, press “ESC” (remember,the Schematic Window must be active) to stop placing parts.6.If you need to move any of the parts, use the following procedure:(a)Press “M” (stretch) or “m” (move). Note the message at the bottom of the SchematicWindow. At this point, there is no difference between these two commands. But whenwires are attached to the parts, “M” will move the wires as well, whereas “m” will justmove the part.(b)Click on the part you wish to move. Again, keep an eye on the bottom of the SchematicWindow. Follow the instructions there. Repeat as needed.(c)Note that you can also move items by moving the cursor over the item, pressing andholding the left mouse button, moving the mouse, and then releasing the mouse button.Editing the Symbol PropertiesOnce all the parts are placed on the schematic, you can set property values that are specific to the design on each symbol. Figure 2 shows many of the property values that you will add in this part of the tutorial. The “vsin” symbol has many properties: “acm” is “AC Magnitude”, the amplitude of the AC signal applied to the linearized circuit (small signal circuit) during an AC Analysis. The “acp” is the “AC Phase”, “vo” refers to “DC Offset”, and “vm” refers to “Amplitude”, the amplitude of the signal applied to the large-signal (non-linear) circuit during a Transient Analysis.Figure 2: Symbol property values.e the following procedure to change a symbol’s properties. Before you begin, make sure thatyou have pressed ESC to clear the last action performed (the bottom line of the Schematic Window should read “>”):(a) Move the cursor to a location where there are no parts. Then press “q”. An “EditObject Properties” dialog box will appear.(b)Click on the item whose properties you’d like to change. The dialog box will expand todisplay a list of properties that can be changed. If you can’t see any properties, makesure thatthe “CDF” box is checked near the top of the “Edit Object Properties”window.(c)In the list of properties, edit those that you would like to change or specify. DO NOTinclude units such as “Volts” or “Ohms” - you’ll notice that these are filled inautomatically after you move on to the next property. DO NOT press return after youenter a property - use the mouse or use the “TAB” key to proceed. DO specifyabbreviations for scientific notation such as “k” (kilo),”u” (micro), “m” (milli), “M”(mega), “p” (pico), “f” (femto).(d)Click on the next part to change its properties. Cadence will ask whether you want tosave the property changes from the old part - say yes.(e)When you’re done entering properties, click “Cancel” at the top of the “EditObject Properties” dialog box.2. Change the names of the transistors according to Figure 2 by changing the “Instancename” field. Note: The name must be unique. Also insert the values for the transistor widthsand lengths.3.Flip the display of transistor M0 by first pressing “m” and clicking on the transistor to move it.While you are “holding” it, press “R” on the keyboard. The symbol outline should flip. Place theflipped part as shown in Figure 2.4.Note that the ac magnitude and phase of the “vsin” part are not displayed by default. Edit theproperties of this part (with the “q” key, and then look at the “AC Magnitude” property. Clickon the button to the right of the property value, and a list of choices will appear. Select “Both”.This will cause this property to be displayed on the schematic.Wiring the SchematicAfter the symbols are placed and the properties are set, you can wire the parts together as shownin Figure 3 by doing the following:1.One way to create a wire between two ports is as follows:(a)Position the mouse cursor over the first port (for example, start with the top of theconstant voltage source).(b)Click and hold the left mouse button.(c)Position the mouse cursor over the second port (the Vdd symbol above the Vdc symbol).(d)Release the left mouse button.(e)Repeat steps a through d to connect each Ground and Vdd symbol to the associatedparts, as shown in Figure 3.2. To connect the Gate terminals of the pMOSTs to the Drain terminal of M1, do the following:(a)Press “w” on the keyboard. Note the instructions at the bottom of the SchematicWindow.(b)Click and hold the left mouse button.(c)Position the cursor over the mid-point of the wire between the Gate terminals of M1 andM2, and click the left mouse button.(d)Move the mouse cursor four grid-points down, and click the left mouse button.(e)Move the mouse cursor six grid-points to the left, and click the left mouse button. Thiscompletes the connection.plete the remaining wire connections as shown in Figure 3.Figure 3: Schematic Wire Connections.Modifying Wire AttributesIf you do not label wires, Cadence automatically provides names for each wire, such as “net30”. It can be helpful later on during design and analysis if you label the wires with meaningful designators that are easy to understand and refer to. To add the attribute “vout” to the wire shown in Figure 3, do the following:1. Press “l” (for label) on the keyboard. An “Add Wire Name” dialog box appears.2.Enter “vout vin” in the “Names” field and press “Return”3.Move the cursor until the dot is on top of the wire to be labeled “vout”. Left click once with themouse. The label will be attached to the wire, and the label you are moving with your cursor changes.4.Place the “vin” label in an appropriate spot. Make sure the dot is on top of the wire before youleft-click.Finally, add a single instance of “ece[LIB]lib title” underneath your schematic. Please make sure that this is always placed in all your schematics.At this point you have a completed design that is ready to be analyzed. In the next part of the tutorial, you will simulate the amplifier. First, save the design by clicking the checkmark icon (the Check and Save icon) on the left hand side of the Schematic Window (top). Check the CIW. There should be a message saying that “Schematic Check completed with no errors”. Whenever you make a change to your design, you’ll need to check and save before you simulate. Otherwise, you may get an error, which will show up in the CIW window. Again, the CIW is extremely important for finding errors. You should read any errors carefully, and sometimes warnings are important too.III. Analyzing the DesignBefore performing the circuit analysis, you need to start the analog environment by going to “Tools > Analog Environment” in the schematic window. A new window called the“Simulation Window” will appear.Next you need to tell Cadence where to find the model library. For this class, we have a single model library file, called “cmos018.scs”, which contains an nMOST model named “N”, and a pMOST model named “P”. The symbols we’re using by default have these names specified in their symbol properties (look at the properties for one of the transistors). If you ever decide to use a different symbol, you’ll need to make sure the “Model name” property is correctly filled in. To tell Cadence where to look for the model file, go to “Setup > Model Libraries” in the Simulation Window. In the “Model Library File” field, enter:/home/linux/ieng6/ee164f/your_login_name/ece-cadence/cmos018.scs(if you are taking EE164)or/home/linux/ieng6/ee264a/your_login_name/ece-cadence/cmos018.scs(if you are taking EE264a)where “your_login_name” should be replaced by the name of the account under which you logged into the system (e.g., bobama). Then click on “Add” (NOT “OK”). You’ll see the path placed in the list of Model Library Files. Now click on “OK”.Finding the DC Operating Point and Performing a DC SweepIn this section, you’ll find and annotate the DC operating point, and you’ll sweep the input voltage to find the correct bias voltage for the nMOST transistor.1.Now go to “Analyses > Choose...”. A new dialog box will appear. [a]2.In the new dialog box, select the “dc” button. Check the “Save DC Operating Point” box.This will allow us to annotate node voltages later. Finally click “OK”3.We’ll now perform our first simulation. Click on the “Netlist and Run” icon, which is thegreen traffic light on the right hand side of the Simulation Window. If this is your first time running Cadence, a “Welcome” menu appears – close it. A new window will appear, hopefully saying that the simulation was successful, and providing a brief summary of the simulation convergence. [s]4.If everything went well, go to the Simulation Window, and select “Results > Annotate >DC Node Voltages”[d]. Note that the voltages at each terminal of each device are now marked on the schematic. Now go to “Results > Annotate > DC Operating Point”[D]. Note that important voltages and currents are now marked on each device. You can quicklysee whether the devices are biased properly. You can remove this annotation by using “Results > Annotate >Design Defaults”[^d].5.You should see a problem with the node voltages. The node “vout” should be about 2.4V. Thismeans that the top pMOST is operating in triode, and this amplifier will not work properly. You’ll now fix this using a DC sweep to find the correct bias point.6.Go back to the Simulation Window, and select “Analyses > Choose...” [a]. Under “SweepVariable” on the DC Analysis Form, select “Component Parameter”. The form will become larger.7.On the expanded form, click the “Select Component” button. You will be prompted to selecta component on the schematic. Select the “vsin” symbol at the nMOST input. A new window willappear, and you should select “dc” as the parameter you wish you vary, then click “OK” in the new window.8.Fill in the rest of the form so that the voltage is swept from 0 to 2.5V. Set the sweep type to“Linear”, and set the number of points to be plotted to 500. When you’re done, click “OK” on the Choose Analyses window.9.Now you need to select an output to plot. To plot a voltage, use the following procedure:10.Go to “Outputs > To Be Saved > Select on Schematic” in the SimulationWindow. Left-click on the “vout” and “vin” nets in the schematic window, and then press “ESC”. This step is typically not done as you can simply click on the nodes you want to plot after the simulation is complete. However, go ahead and try it this time.11.Go to “Outputs > Setup...”. In the Setting Outputs window, click on the “vout” line onthe right hand side. Then select the “Plotted” button, and press “Apply”. Do the same for the “vin” line. Then click “OK” in the Setting Outputs window.12.Finally, we can perform the DC Sweep. Press the green traffic light. The Waveform Window withthe simulation results should appear.13.We need to find the input voltage which will place our output bias at roughly Vdd/2. Move yourcursor over the waveform plot of “vout”. You’ll see the x and y coordinates at the top of the window. Using this method, select the DC value of “vin” which will give an output of approximately 1.25V. You should get about 550mV. Update the “vsin” symbol with this new DC offset voltage.14.Repeat the DC simulation, and verify from the annotated voltages that your output is now roughlyat Vdd/2. If so, you’re ready to move on to the next simulation.15.But first, unless you like to repeat things, you should learn how to save the simulation state.Go to“Session > Save State...”, and you’ll be prompted to save your current state. Enter the name of a state of your choosing, or just stick with the default. This state can be reloaded later (using “Session > Load State...”, and you won’t have to enter all of the setup data again.Performing a Transient AnalysisIn this section, we’ll look at the amplifier’s large signal response to a sinusoidal input signal at 100kHz.1.First, turn off the DC Sweep analysis by bringing up the choose Analysis window and unselectingthe “Enabled” box at the bottom of the form.2.Select the “tran” button. Enter “100u” in the “Stop Time” field. If you want, you can alsoclick the “moderate” button, but this is not necessary. It is recommended by Cadence you never click the other two.3.Click the “Options” button. A new dialog box appears. In this Transient Options window,change the following attributes: “step” to 10n, “maxstep” to 10n, then press “OK”. These options make sure that enough points are taken during the transient analysis. They will be different for other simulations in this class, and you’ll need to experiment with them. Typically, you can leave this field blank and see how well the transient results look. If they seem “choppy,” go ahead and enter a number here. Refer to the Cadence documentation for more information on the other parameters on this form.4.You’re now ready to simulate, and you haven’t changed the schematic, so you can press the yellowtraffic light to simply run the simulation.5.After a few moments, the waveform window should appear with a nice sinusoid. You can removethe input sinusoid (we know it’s just a 2mV peak-to-peak wave) to get a better view of the output.Go to “Curves > Edit” in the Waveform Window, and turn off the “vin” waveform or click on the waveform and press “del”.6.To measure the peak-to-peak amplitude of the output, use the “Markers” {a},{b} menu to placemarkers A and B at the highest and lowest points of “vout”. From the display at the bottom of the window which will appear after you have done this, you should find the peak-to-peak amplitude to be about 63mV, meaning the circuit has a gain of about 30.Performing an AC AnalysisIn this section, we’ll look at the amplifier’s frequency response. Hopefully you’re becoming proficient with Cadence now, so not as much detail about the individual steps will be provided.1.Bring up the Choosing Analyses window, and disable the transient simulation, and the sweepportion of the DC simulation. Then click the “ac” button, and set up this simulation to sweep frequency from 100Hz to 1GHz, with 100 points per decade. You will need to change the sweep type to “logarithmic”.list and Run the simulation (or just run it, if your schematic is unchanged). [s]3.In the schematic window, we will now create a Bode plot. The easy way to do this is to go to“Axes” and change the scale of the y-axis to be logarithmic. We’ll use a different approach, usingthe Waveform Calculator, an important Cadence tool.(a)First, add a new subwindow to plot our new graph in. Do this by going to the “Window >Subwindows...” menu option, or by clicking on the subwindow icon on the left-handside of the Waveform Window{S}. Make sure that the new subwindow is active by left-clicking in its area. Now click on the calculator icon on the left side of the waveformwindow. The calculator will appear. By default, the calculator uses RPN (Reverse PolishNotation), but this can be changed in the “Options” menu item, if you’d like. For thefollowing, I assume you’re using RPN.(b)Click on the “wave” button in the calculator. You will be prompted to click on a wave -select the “vout” waveform. The expression for this wave will appear in the calculatorwindow.(c)You want to plot 20*log10(vout). To do this in RPN, now click on the “log10” button,then enter “20” on the keypad, then press the multiply button. You should see thecalculation take place in the calculator window. If you prefer, you can simply type “*20”at the end of the expression in the calculator window. – in other words, use it as a normalcalculator.(d)Now press the calculator “plot” button. The new wave will appear in the subwindow.4.You can also make measurements with the calculator. If you click and hold the “SpecialFunctions” button, you will see a list of functions. Select “bandwidth”. A form will come up, and you can click “OK”. Then press the “print” button on the calculator. This will bring up a window with the measured 3-db bandwidth of your circuit.5.You’re done with the AC Analysis now. We’ve only scratched the surface of what can be donewith the Waveform Calculator. Feel free to experiment more with it if you wish. Then go to the next section.Performing a Parametric SweepSometimes it’s important to perform sweeps of two variables simultaneously. This section shows you how to do this. We will sweep the nMOST bias voltage over a few values, and plot the frequency response of the amplifier for each value. This will demonstrate how drastically the bias point (which determines whether transistors are saturated) can affect circuit performance.1.For a parametric analysis, you must first define the variable to be parameterized (the one whichtakes on discrete values). In our case, this will be the offset voltage of the “vsin” symbol. Go to this symbol and edit its properties. In place of the number which you currently have entered in the “Offset voltage” field, enter “vgs”. Then click “OK”. Check and save.2.Go to the Simulator Window and select “Variables > Copy From Cellview”. You willnotice that “vgs” appears in the Design Variables subwindow.3.Go to “Variables > Edit...” (or use the shortcut) and set the value of “vgs to the bias voltage youfound during the DC Sweep portion of the tutorial.4.Next, you will need to re-enable the DC simulation. To do so, go back to the analysis chooser andselect the DC analysis button. Choose to enable this simulation; however, make sure you disable the “component parameter” sweep.5.Now netlist the schematic. (You can find the option to just netlist under “Simulation”, or youcan just netlist and run. It doesn’t make any difference. We just need to netlist somehow.) This is a critical step. If you forget to do this, the parametric analysis will seem to do nothing.6.In the Simulation Window, go to “Tools > Parametric Analysis...”. Set up the formso that “vgs” is swept from 0.4V to 0.8V in 9 total steps. In the same form, go to “Analysis > Start” to begin the analysis.7.When the Waveform window comes back, it should have multiple distinct curves, showing thefrequency response for each value of vgs. Notice how dramatically the gain drops off away from the correct bias point!A Note on Measuring CurrentsYou select a current to be plotted in much the same way as you select a voltage. When selecting outputs to be plotted (see the beginning of “Analyzing the Design”), click on the terminal of adevice rather than a wire. A circle should surround the terminal to show that the current flowing INTO this terminal will be plotted. A few caveats: first, sometimes it can be very difficult to select a node - you may have to click on the center of the symbol at which you want to measure current, which will select all nodes of that symbol, and then delete the currents you don’t want in the Simulation Window. Second, the transistor symbols used for the class don’t allow their currents to be plotted for some reason. Remember, you can always put in a zero-volt voltage source if you need some usable terminals for measuring current!A Note on Printing/PlottingSome information on customizing printing was given earlier in this tutorial. In order to actually bring up a plotting dialog box, you can go to “Design > Plot > Submit..” in the Schematic Window, or “Window > Hardcopy” in the Waveform Window. You’ll have to experiment with the forms to get what you want. The forms are quite versatile. Keep in mind you can print to a postscript file as well as directly to a printer.When printing, it is suggested that you do the following:(a)Unselect the [Plot with] “Header” button.(b)On the Plot options page:i.Unselect the “Mail Log to” button.ii.Select the “Center plot” button. [Not available when printing waveforms]iii. Select the “Fit to page” button. [Not available when printing waveforms]iv. Check that the correct printer is selected (or)v. If you want to print to a postscript file, select the “Send plot only tofile” button.If you decide to print to a file, the output will be a postscript file. This may be inconvenient for some students. If this is the case, you can run “ps2pdf <filename.ps>” to convert the postscript file to a PDF. This program, however, is not available in your path, by default. You will need to add it to your path before ps2pdf will work. To do so, at the UNIX command prompt (not the CIW!), type:set path = ( $path /software/common/ghostscript-8.0.0/bin )Note: Due to a “bug” in Cadence, waveforms are printed as they appear on the screen. In other words, if the waveform window is small, on the screen, the printout will be equally small. It is suggested that you make the waveform windows large to get the clearest printouts.。
cadence使用教程
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PMOS layout view
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Start schematic
一. 建立 Schematc view：跟建立 layout view 方法一樣（請參考 Start Cadence 的第 五大點的第二小點），先點選要 LM 視窗預定的 library，再點選 LM 視窗的 File→New→Cell view，按 OK 之後，即可建立 Schematic View
1.數字應該是 4.4.5 2.若不是 4.4.5,代表使用到舊版 的 cadence 了,請從第一點重新 開始
CIW(command Interpreter window)
三.點選在 CIW 視窗的上面工具列 Tools→Library Manager， 會出現 LM 視窗 LM(Library Manager)
1. 桌面改為 1024*768*256 色 2. 執行 xwin 程式 3. Netterm telnet 140.116.164.112~141 (CIC 電腦教室) 4. e2486***@eesol08:~> who
e2486*** pts/2 Dec 28 11:43 (.tw) 5. e2486***@eesol08:~> setenv DISPLAY .tw:0.0 6. 完成上述五個步驟後，Start Cadence 的方法，請參閱使用手冊第六頁。
10
四.當在畫的途中，可以使用 on-line drc(DIVA)來檢查是否違反 design rule 1. 點選 Layout 視窗上面的指令 Verify→DRC 2. 出現 DRC 視窗
cadence 教程
cadence 教程Cadence 是一种电子设计自动化工具，常用于模拟、验证和布局设计。
它可以帮助工程师在各种电子系统中设计和验证电路，从而提高电路设计的效率和可靠性。
下面将介绍一些 Cadence 的基本使用方法和技巧。
1. 创建新项目要使用 Cadence，首先需要创建一个新项目。
可以通过菜单栏上的"File" -> "New"来创建新项目。
然后输入项目名称、路径等信息，并选择适当的项目类型。
2. 添加电路在 Cadence 中，可以通过绘制电路原理图来添加电路。
可以使用"Create Schematic"工具来创建新的电路原理图。
在绘制电路原理图时，注意使用正确的元件符号和连线方式。
3. 设置仿真参数在进行电路仿真之前，需要设置仿真参数。
可以通过菜单栏上的"Simulator" -> "Edit Simulation"来打开仿真设置窗口。
在仿真设置窗口中，可以设置仿真类型（如DC、AC、Transient 等）、仿真时间范围、仿真步长等参数。
4. 运行仿真设置好仿真参数后，可以通过菜单栏上的"Simulator" -> "Run Simulation"来运行仿真。
运行仿真后，可以查看仿真结果，如电压波形、电流波形等。
5. 进行验证在验证电路设计时，可以使用 Cadence 提供的调试工具和验证功能。
可以通过菜单栏上的"Debug" -> "Start Debugging"来启动调试。
在调试过程中，可以查看电路元件的属性、信号的波形等信息，以发现和解决问题。
6. 进行布局设计在电路设计完成后，可以进行布局设计。
可以使用 Cadence 提供的布局工具来布局电路版图。
布局时，要注意合理安排电路元件的位置和走线方式，以满足电路设计的要求。
Cadence软件使用教程 ppt课件
Allegro PCB Router 自动布线工具，对于有复杂设计规则的高密度电路板处理能力很强， 可以在Allegro PCB Editor中用自动布线命令调出来。这个布线工 具名气很大，对于简单的电路板，布线很美观，布通率很高。
Cadence软件使用教程
Cadence软件使用教程
1、利用OrCAD Capture CIS进行原理图设计 2、利用Cadence PCB Editor进行PCB布局布线 3、光绘文件(Artwork)制作，如何生成Gerber文件
Cadence软件使用教程
Cadence软件使用教程
1、系统的原理图工程文件 2、系统的PCB图工程文件 3、原件库、封装库文件 4、板上芯片的datasheet 5、给PCB厂商的Gerber文件（Artwork） 6、DSP6713程序的C语言源代码
Padstack Designer 创建及修改焊盘padstacks Allegro在创建零件封装时，焊盘需要单独设计，必须使用这个工具先创建焊盘。 DB Doctor 用于检查设计数据中的错误，在设计的每一个阶段执行，可以部分修复数据错误。 在生成光绘文件前必须进行DBDoctor检查。
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
2020年整理Cadence教程(D422).pdf
规定：本实验教材中红色为键入命令或字符，兰色为菜单项，紫色为键盘功能键；“单击”指鼠标左键按下一次。
实验一、Virtuoso Schematic Editor实验目的：掌握电原理图（schematic）设计输入方法。
[1]启动IC Design 软件:首先，登陆Linux，在username文件夹中建立一个你命名的文件夹，然后在Terminal窗口中进入这个文件夹，在该文件夹目录下输入:icfb&，（这样，你在cadence中做的一切工作都会自动保存在这个文件夹中，如果直接icfb&的话，会导致你的工作成果，例如：电路图、仿真结果等，会在/home中保存，影响其他人的使用）[2]建立新库、新单元以及新视图（view）:首先，输入icfb&后，出现下图窗口在图中CIW窗口中依次打开：Tools->Library Manager，出现下图窗口：在图中窗口中依次打开：File->New->Library，出现下图窗口：输入Library Name：test，然后点OK。
（注意下面的保存路径就是你第一步建立的文件夹）出现下一个窗口：选中Attach to an existing techfile，然后OK。
出现下一个窗口：选中右下方Technology Library：chrt35dg_SiGe，然后OK。
下面我们来画一个nand2电路。
选中左侧的test，在Library Manager 窗口，File->New->Cellview，如下图：在弹出的“Create New File”窗口Cell Name栏中，nand2 Tool栏中，选Composer-SchematicOK，如下图[3]添加元件（实例instance）在弹出的“Virtuos o Schematic Editing:…”窗口中，左边为工具栏，选instance 图标（或i）单击“Add instance”窗口Library栏最右侧Browser,弹出“Library Browser-…”窗口，Library选chrt35dg_SiGe，Cell选nmos_3p3, View选symbol鼠标回到“Add instance”窗口，Model name栏：nmos_3p3, width(Total Width): 3.0u , Length: 0.5u，Hide 如下图在“Virtuoso Schematic Editing:…”窗口, 鼠标左键单击一次，间隔一定距离再单击一次，这样就增加了2个nmos元件，ESC（试一试：先选中一个元件，再q ，查看/改变属性）。
Cadence的经典教程
启动 librarymanager : libManager&
使用手册
本手册共分为三部分： 第一部分分为四章， 分别介绍 Cadence cdsSpice、 virtuoso Editing、 Diva 和 verilog。第二部分主要介绍 MEDICI。第三部分是附录部分，是对前两章的一个补 充,并简要的介绍了寄生元件提取语句的语法。 第一章． CdsSpice 的使用说明 ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ．1 § 1－1 进入 Cadence 软件包 ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ．1 一．在工作站上使用． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． 1 二．在 PC 机上使用． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ．1 § 1－2 建立可进行 SPICE 模拟的单元文件． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． 2 一．File 菜单． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ． ．
Cadence入门教程
Cadence使用初步简介在早期的ASIC 设计中电路图起着更为重要的作用作为流行的CAD软件Cadence 提供了一个优秀的电路图编辑工具Composer。
Composer不但界面友好操作方便而且功能非常强大电路图设计好后其功能是否正确性能是否优越必须通过电路模拟才能进行验证Cadence 同样提供了一个优秀的电路模拟软件Analog Artist由于Analog Artist 通过Cadence 与Hspice 的接口调用Hspice 对电路进行模拟。
但是我们的虚拟机中并没有安装Hspice软件，所以我们使用Cadence自带的仿真软件进行仿真。
本章将介绍电路图设计工具Composer 和电路模拟软件Analog Artist 的设置启动界面及使用方法简单的示例以及相关的辅助文件以便大家能对这两种工具有一个初步的理解。
一、Cadence平台的启动：①右击桌面，在弹出菜单中单击open Terminal②在弹出的终端中输入icfb&然后按回车启动Cadence③Cadence启动过程④Cadence启动完成后，关闭提示信息①点击Tools—Library Manager…启动设计库管理软件②启动设计库管理软件③点击File—New--Library新建设计库文件④在弹出的菜单项中输入你的设计的库的名称，比如MyDesign，点击OK⑤选择关联的工艺库文件，我们选择关联已有的工艺库文件，点击OK⑥在弹出菜单中的Technology Library下拉菜单中选择我们需要的TSMC35mm 工艺库，然后点击OK。
⑦设计的项目库文件建立完成，然后我们在这个项目库的基础上建立其子项目。
点击选择mydesign,然后点击File-New-Cell View…⑧输入子项目的名称及子项目的类型，多种类型，目前课程设计中用到的主要是电路图编辑和版图编辑。
在设计版图之前我们假定先设计原理图：所以我们选择，然后点击OK。
cadence使用教程
cadence使用教程Cadence是一种电路设计和仿真软件，非常适合电子工程师用于电路设计和分析。
在本教程中，我们将介绍如何使用Cadence进行基本的电路设计和仿真。
首先，打开Cadence软件，并新建一个新项目。
请确保你已经安装了Cadence软件，并且拥有一个有效的许可证。
在新项目中，你需要定义电路的基本参数，如电源电压、电阻值等。
可以通过绘制原理图的方式来完成这些参数的定义。
在绘图界面中，你可以选择不同的元件，包括电源、电阻、电容、电感等。
你可以使用菜单栏中的工具来放置和连接这些元件。
一旦电路图绘制完成，你可以对电路进行仿真。
首先，需要选择合适的仿真器。
Cadence提供了多种仿真器，如Spectre和HSPICE。
选择一个适合你电路的仿真器，并设置仿真参数，如仿真时间、仿真步长等。
在仿真之前，你首先需要对电路进行布局。
布局涉及将电路中的元件放置在芯片上，并根据布线规则进行连接。
Cadence提供了强大的布局工具，可以帮助你完成这个过程。
完成布局后，你可以进行后仿真。
后仿真涉及将布局好的电路导入到仿真器中，并进行仿真分析。
你可以查看电路的性能指标，如电压、电流和功耗等。
除了基本的电路设计和仿真，Cadence还提供了其他功能，如噪声分析、温度分析和优化设计等。
你可以根据需要选择适合的功能。
总的来说，Cadence是一个功能强大的电路设计和仿真软件。
通过本教程，你可以学会如何使用Cadence进行基本的电路设计和仿真。
希望这对你的电子工程项目有所帮助。
cadence中文教程整理版
cad ence中文教程整理版cadence教程第一章． Cadence cdsSPICE的使用说明Cadence cdsSPICE 也是众多使用SPICE内核的电路模拟软件之一。
因此他在使用上会有部分同我们平时所用到的PSPICE相同。
这里我将侧重讲一下它的一些特殊用法。
§ 1－1 进入Cadence软件包一．在工作站上使用在命令行中（提示符后，如：ZUEDA22>）键入以下命令icfb&↙(回车键)，其中& 表示后台工作。
Icfb调出Cadence软件。
出现的主窗口如图1-1-1所示：图 1-1-1Candence主窗口二．在PC机上使用1）将PC机的颜色属性改为256色（这一步必须）；2）打开Exceed软件，一般选用xstart软件，以下是使用步骤：start method选择REXEC（TCP-IP） ,Programm选择Xwindow。
Host选择10.13.71.32 或10.13.71.33。
host type选择sun。
并点击后面的按钮，在弹出菜单中选择command tool。
确认选择完毕后，点击run！3）在提示符ZDASIC22> 下键入:setenv DISPLAY 本机ip:0.0(回车) 4）在命令行中（提示符后，如：ZUEDA22>）键入以下命令icfb&↙(回车键)即进入cadence中。
出现的主窗口如图1-1-1所示。
以上是使用xstart登陆cadance的方法。
在使用其他软件登陆cadance时，可能在登录前要修改文件.cshrc，方法如下：在提示符下输入如下命令：vi .cshrc↙（进入全屏幕编辑程序vi）将光标移至setevn DISPLAY ZDASIC22:0.0 处，将“ZDASIC22”改为PC机的IP，其它不变（重新回到服务器上运行时，还需按原样改回）。
[整理]CadenceSPB165的安装及破解图文教程.
![[整理]CadenceSPB165的安装及破解图文教程.](https://img.taocdn.com/s3/m/5ffa904d482fb4daa48d4b0b.png)
SPB16.5基于pubkey1.30的安装及破解一、破解的预期工作，文件准备：The first.rar和licens_gen.rar，如下：注：在图标上点右键，复制粘贴到你电脑上除桌面以外的任意位置。
注：在图标上点右键，复制粘贴到你电脑上除桌面以外的任意位置。
二、安装步骤1.网上下载Cadence16.5安装文件，一般是5个压缩包，先都解压出来，把2-5的文件夹内容直接复制到第一个压缩包解压出来的文件夹下。
这样安装时不用再选择文件地址，比较省事。
2.运行“setup.exe”首先，安装license manager，步骤如下：点击LicenseManager。
选择接受许可，点击Next选择LicenseManager安装目录，根据个人习惯修改吧。
选择要安装的模块，点击Next。
到这里要刹车，直接Cancel。
最后完成安装，点击Finish接下来，要安装Cadence的主要工具：Product Installation。
安装Product Installation，一路Next到下图。
注：可以在安装界面中选择Custom方式，里面可以选择需要安装的模块，如果是初学者，不知道自己会用到哪些，并且电脑还承受的住，就全部安装，大概需要4.3G，然后点击Next。
选择安装目录，点击Next。
预览安装信息，不满意的点击Back修改，感觉ok的点击Next。
点击Install开始安装。
耐心等待。
一般安装到最后，出现要寻找firewall的允许项添加什么的，需要等很长一会，一开始以为软件装的不动了，不想一会又开始装了。
这里不用管，直接Next。
要查看产品信息了就在选中该项，不需要了直接点击Finsh，就完成了安装工作。
三、破解步骤。
1、在任务管理器中确认一下是否有这两个进程,有就结束掉,即cdsNameServer.exe和cdsMsgServer.exe,没有就算了。
说明：看来没有。
2、把安装目录下的SPB_16.5/tools/pspice目录下的orSimSetup.dll剪切出来找个地方先放着不理（待完成破解后再拷回原来的地方,如果不用仿真部分删掉也无所谓）。
Cadence快速教程
一．原理图（ORCAD工具）1．建立工程与其他绘图软件一样，OrCAD以Project来管理各种设计文件。
点击开始菜单，然后依次是所有程序—打开cadence软件—》一般选用Design Entry CIS，点击Ok进入Capture CIS。
接下来是File--New--Project，在弹出的对话框中填入工程名、路径等等，点击Ok进入设计界面。
2．绘制原理图新建工程后打开的是默认的原理图文件SCHEMATIC1 PAGE1，右侧有工具栏，用于放置元件、画线和添加网络等等，用法和Protel类似。
点击上侧工具栏的Project manager（文件夹树图标）或者是在操作界面的右边都能看到进入工程管理界面，在这里可以修改原理图文件名、设置原理图纸张大小和添加原理图库等等。
1）修改原理图纸张大小：双击SCHEMATIC1文件夹，右键点击PAGE1，选择Schematic1 Page Properties，在Page Size中可以选择单位、大小等；2）添加原理图库：File--New--Library，可以看到在Library文件夹中多了一个library1.olb的原理图库文件，右键单击该文件，选择Save，改名存盘；（注意：在自己话原理图库或者封装库的时候，在添加引脚的时候，最好是画之前设定好栅格等参数，要不然很可能出现你画的封装，很可能在原理图里面布线的时候通不过，没法对齐，连不上线！）3）添加新元件：常用的元件用自带的（比如说电阻、电容的），很多时候都要自己做元件，或者用别人做好的元件。
右键单击刚才新建的olb库文件，选New Part，或是New Part From Spreadsheet，后者以表格的方式建立新元件，对于画管脚特多的芯片元件非常合适，可以直接从芯片Datasheet中的引脚描述表格中直接拷贝、粘贴即可（pdf格式的Datasheet按住Alt键可以按列选择），可以批量添加管脚，方便快捷。
cadence详细教程
cadence详细教程第⼀次⽬录1.Cadence系统编辑环境 (2)实验1：Cadence系统编辑环境设置与基本操作 (2) 2.电路图设计⼯具－Schematic (8)实验2：⼆与⾮门电路原理图设计 (8)实验3：数、模混合集成电路原理图设计 (14)3.电路仿真⼯具－ADE (18)实验4：ADE环境设置 (18)实验5：差分放⼤器电路仿真 (23)4.版图设计⼯具－Layout Editor (30)实验6：Layout Editor环境设置 (30)实验7：MOS管版图设计 (35)实验8：BJT管版图设计 (38)实验9：CMOS反相器版图设计 (42)实验10：Pcells版图设计 (46)实验11：pk44chip芯⽚版图综合设计 (53)5.版图验证⼯具－Diva (57)实验12：版图验证 (57)实验13：版图识别 (66)实验14：版图改错 (71)6.设计性实验 (73)实验15：RS触发器设计 (73)实验16：静态存储器设计 (76)实验17：三态与⾮门设计 (79)实验18：基准电压源设计 (81)实验19：CMOS放⼤器设计 (83)实验20：异或门设计 (84)Lab 1 Cadence系统环境设置与基本操作1.实验⽬的熟悉Cadence系统环境了解CIW窗⼝的功能掌握基本操作⽅法2.实验原理系统启动Cadence系统包含有许多⼯具（或模块），不同⼯具在启动时所需的License 不同，故⽽启动⽅法各异。
⼀般情况下涉及到的启动⽅式主要有以下⼏种，本实验系统所⽤到的有icms、icfb、layoutPlus等。
①前端启动命令：表1.1 前端启动命令命令规模功能icde s 基本数字模拟设计输⼊icds s icde以及数字设计环境icms s 前端模拟、混合、微波设计icca xl 前端设计加布局规划②版图⼯具启动命令表1.2 版图⼯具启动命令命令规模功能Layout s 基本版图设计（具有交互DRC功能）layoutPlus m 版图设计（具有⾃动化设计⼯具和交互验证功能）③系统级启动命令表1.3 系统级启动命令命令规模功能swb s PCB设计msfb l 混合型号IC设计icfb xl 前端到后端⼤多数⼯具CIW窗⼝Cadence系统启动后，⾃动弹出“what’s New…”窗⼝和命令解释窗⼝CIW （Command Interpreter Window）。
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OrCAD 培训教材深圳光映计算机软件有限公司——洪永思Capture Features●Vendor specific libraries●Integration with all other OrCAD EDA tools●Netlist interface to other PCB desig1packages●Cross-probing and bi-directional annotation between schematicand PCB designs.●Integration of company parts database (Capture CIS).●Customized Bill of Materials reportsPSpice Features●提供一个对电路进行仿真的环境●分析验证你的电路●对电路进行参数优化●对器件的模型参数进行提取Layout Features●提供对PCB板进行设计的环境●周到齐全的EDA软件接口●功能强大的机械设计环境(Visual CCAD)●与制作加工相结合的GerbTool工具●功能多样的策略与模板OrCAD的基础知识OrCAD常用文档类型✧*.opj—项目管理文件✧*.dsn—电路图文件✧*.olb—图形符号库文件✧*.lib—仿真模型描述库文件✧*.mnl—网络表文件✧*.max—电路板文件✧*.tch—技术档文件✧*.gbt—光绘文件✧*.llb—PCB封装库文件✧*.log *.lis—记录说明文件✧*.tpl—板框文件✧*.sf—策略档文件OrCAD软件包含的库1、*.olb-Capture专用的图形符号库只有电气特性，没有仿真特性的库。
此类库没有相应的*.lib库，且器件属性中没有PspiceTemplate属性。
能够利用PSpice进行仿真的库。
此类库有相应的*.lib库，且器件属性中有PspiceTemplate属性。
2、*.lib-PSpice仿真库，利用Spice语言对Capture中的图形符号进行功能定义与描述，可以编辑。
3、*.llb-PCB Layout器件封装库。
OrCAD Layout提供3000多个国际标准的器件封装。
OrCAD Capture培训教材深圳光映计算机软件有限公司——洪永思培训目标：熟悉OrCAD—Capture设计环境，熟练掌握Capture的操作方法及环境参数的设置，最终完全掌握Capture。
一、Capture设计过程二、Capture操作环境Capture有三个主要工作窗口：专案管理视窗：管理与原理图相关的一系列文件，相当于资源管理器。
Schematic窗口：原理图窗口，相当于一张图纸。
信息查看窗口（Session Log）：用于显示相关操作的提示或出错信息。
专案管理视窗Schematic窗口信息查看窗口三、 Capture 设计参数设置Capture 的环境参数包括：系统属性及设计模板两大类。
系统属性包括(Options>Preferences)：系统设计模板参数包括(Options>Design Template)：四、 新建Project(create a design project)Capture 的Project 是用来管理相关文件及属性的。
新建Project 的同时，Capture 会自动创建相关的文件，如DSN 、OPJ 文件等，根据创建的Project 类型的不同，生成的文件也不尽相同。
根据不同后续处理的要求，新建Project 时必须选择相应的类型。
Capture 支持四种不同的Project 类型。
在菜单栏中选择file>new>Project ：五、 开始绘制电路图新建project 后，进入Schematic 窗口，则在窗口右边会出现下图的工具栏：1、 Place part （放置器件）在Capture 中，调用器件非常方便，即使您不清楚器件在库中的名称，也可以很容易查找并调出使用。
使用Capture CIS 还可以让您通过Internet 到Cadence 的数据库（包含1万多个器件信息）里查找器件。
点击Place part 快捷按钮或点击place>part 将调出如下对话框：点击part search…按钮，调出下面的器件搜索对话框：2、连线及放置数据总线(Place wire or bus)点击Place wire(或place bus)按钮进入连线（或放置数据总线）状态，此时鼠标变成十字形，移动鼠标，点击左键即可开始连线（或放置数据总线）。
连线时，在交叉而且连接的地方会有一个红点提示，如果你需要在交叉的地方添加连接关系，点击place junction，把鼠标移动到交叉点并点击左键即可。
放置数据总线后，点击place bus entry按钮放置数据总线引出管脚，管脚的一端要放在数据总线上。
3、放置网络名称(place net name)点击place net alias按钮，调出place net alias对话框，在alias 对话框中输入要定义的名称，然后点击OK退出对话框，把鼠标移动到你要命名的连线上，点击鼠标左键即可。
注意：数据总线与数据总线的引出线一定要定义网络名称。
4、放置电源和地(place power or GND)点击Place power（或Place GND），调出如下对话框：图形符号5、放置阶层及阶层管脚对于一张大的原理图来说，通常都是把它分割成多个模块，再对子模块进行。
Capture支持采用阶层的方式来设计，即用一个方块来代替一个功能模块，进入阶层时，Capture会自动把阶层的管脚关系引入到阶层原理图里。
点击Place Hierarchical Block ，调出如下对话框：放置好阶层后，接下来就是放置阶层的管脚。
放置阶层管脚时，必须保证阶层被选中。
点击Place Pin ，调出下示对话框：6、 放置端口与分页图纸间的接口点击Place Hierarchical Port(或placeOff-page connector)放置端口(或分页图纸间的接口)，调出如下对话框：与PCB 相关，即是否当成一个器件图形符号对于端口，不同端口之间的区别在于其类型的不同，它的类型可以从它的TYPE属性中得知，双击端口或选中端口并点击右键在弹出菜单中选择Edit Properties，调出如下窗口：7、添加文字(place text)点击place text…按钮，系统弹出如下对话框：文本内容六、原理图绘制后续处理原理图绘制好之后，接下来就是对电路图进行DRC检测，生成网表及材料清单。
下面，我们将逐一讨论。
注意：对原理图进行后续处理，在Capture中必须切换到专案管理窗口下，并且选中*.DSN文件。
1、DRC检测(Design Rules Check)点击按钮或(Tools>Design Rules Check)，调出如下设置对话框：Scope：Check entire design：DRC检查整个原理图Check Selection：DRC只检查你选择的部分Mode：Use instances(preferred)：使用当前属性（建议）Action：Check design rules：进行DRC检测Delete existing DRC marker：删除DRC检测标志Report：DRC检测的内容Create DRC markers for warnings：在警告的地方放置标志Check hierarchical port connection：检测阶层端口的连接性Check off-page connector connection：检测分页图纸间接口的连接性Report identical part references：报告同样的器件序号Report invalid packaging：报告无效的封装Report hierarchical ports and off-page connection：报告阶层端口和分页图纸间接口的连接Check unconnected net：检测未连接的网络Check SDT compatibility：检测对于SDT文件的兼容性Report all net name：报告所有网络名称2、与DRC检测相对应的自动排序功能通常，一名设计者都需要对自己设计的原理图中的器件编号进行从新排序。
Capture提供自动排序功能，允许你对原理图重新排序。
点击(或Tools>Annotate)，调出如下对话框：3、Capture另一个重要的功能是自动更新器件或网络的属性对于使用特殊封装或拥有自己封装库的公司，此项是一项特别有用功能。
首先定义好自己的属性文件（格式后面祥述），点击Tools>Update Properties，调出如下对话框：属性文件的格式如下(可以用记事本编辑，存为文本文件即可)："{Value}" "PCB Footprint""74LS00" "14DIP300""74LS163" "16DIP300""8259A" "28DIP600"4、生成网络表对于Capture来说，生成网络表是它的另一项特殊功能。
在Capture中，可以生成多种格式的网络表（共39种），以满足各种不同EDA软件的要求。
点击或To ols>Create Netlist…，调出如下对话框：应的网络表。
5、生成材料清单对于原理图来说，最后的一个步骤应该是产生材料清单。
点击或Tools>Cross Reference…，产生交互参考报表，调出如下对话框：对话框：Line Item Definition：定义材料清单的内容Place each part entry on a separate：材料清单中每个器件信息占一行Include File：在材料清单中是否加入其他文件6、建立器件图形符号库用户另一个关心的问题是有关图形符号库的新建问题。
新建图形符号，先新建图形符号库，在菜单中选择File>new>library，然后在专案管理视窗中选中库，点击右键，选择New part，即可。
Name：器件的名称Part reference：器件在原理图中编号的首字母PCB Footprint：器件相对应的封装Part per：一个器件封装中包含多少个器件Homogeneous：封装中的器件都一样Heterogeneous：封装中的器件不一样Alphabetic：以字母区别封装中的多个器件Numeric：以数字区别封装中的多个器件7、Part manage (Capture CIS)对于涉及生产的厂家，对材料清单的内容就要求更多一些，如物料编号，提供的厂家等。