s3c2416核心板原理图

3
VCC3P3
DWG. NO.
SH.
REV
1
DATE APPROVED
REV
DESCRIPTION
REVISIONS
VCC3P3
VCC3P3
D
SDDAT2 SDDAT3 SDDAT0 SDDAT1 SDCMD SDCLK
D
1K 1K 1K
A
LVDS_EN LED
CF2
C
C LED-0603 LED-0603
5M
2
Y4
48M
Y2
B
GND
CRYSTAL32.768 CRYSTAL32.768
TOU3 TOUT2 TPOU1 TOU0 TCLK
1K
LCD_PWR EINT0 nSD_CS EINT2 EINT3 E_INT EINT5 EINT6 EINT7 EINT8 EINT9 EINT10 EINT11 EINT12 LRCLK MIC MIC BCLK I2C_SDA DACDAT ADCDAT AC97LPOUT LPOUT MCLK I2C_SCL RPOUT RPOUT RIN LIN LIN RIN
F14 C14 D14 B16 C13 A16
B15 F13
DDRBUS
NAND_FLASH
LDATA_BUS DDRBUS
nSCS1 nSCS0
E4
B1 C2
G4 D2 H6 D1 H4 E3
FCLE FALE nFWE nFRE nFCE FRnB
DQS1 DQS0 DQM3 DQM2 DQM1 DQM0
DDRBUS
U4
nBATT_FLT nRESET nRESETOUT PWR_EN nXBACK/GPB5 nXBREQ/RTCK/GPB6 nXDACK0/IS0_SDO1/GPB9 nXDREQ0/I2S0_SDO2/GPB10 CLKOUT0 CLKOUT1 OM1 OM2 OM3 OM4 OM5 nRCS0 nRCS1 nRCS2 nRCS3 nRCS4 nRCS5 nRBE0 nRBE1 nROE nRWE nWAIT
8
7
6
5
4
3
DWG. NO.
SH.
REV
1
DATE APPROVED
REV
DESCRIPTION
REVISIONS
D
D
LADDR[0] LADDR[1] LADDR[2] LADDR[3] LADDR[4] LADDR[5] LADDR[6] LADDR[7] LADDR[8] LADDR[9] LADDR[10] LADDR[11] LADDR[12] LADDR[13] LADDR[14] LADDR[15] LADDR[16] LADDR[17] LADDR[18] LADDR[19] LADDR[20] LADDR[21] LADDR[22] LADDR[23] LADDR[24] LADDR[25]
LDATA[0] LDATA[1] LDATA[2] LDATA[3] LDATA[4] LDATA[5] LDATA[6] LDATA[7] LDATA[8] LDATA[9] LDATA[10] LDATA[11] LDATA[12] LDATA[13] LDATA[14] LDATA[15]
VCC3P3
RADD0 B3 RADD1 D7 RADD2 A3 RADD3 H8 RADD4 C4 RADD5 G8 RADD6 B4 RADD7 F8 RADD8 A4 RADD9 D8 A5 RADD10 H9 RADD11 C6 RADD12 G9 RADD13 B6 RADD14 F9 RADD15 A6 RADD16 D9 RADD17 C7 RADD18 C9 RADD19 B7 RADD20 H10 RADD21 A7 RADD22 G10 RADD23 C8 RADD24 F10 RADD25 SADDR[0] SADDR[1] SADDR[2] SADDR[3] SADDR[4] SADDR[5] SADDR[6] SADDR[7] SADDR[8] SADDR[9] SADDR[10] SADDR[11] SADDR[12] SADDR[13] SADDR[14] SADDR[15] SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6] SDATA[7] SDATA[8] SDATA[9] SDATA[10] SDATA[11] SDATA[12] SDATA[13] SDATA[14] SDATA[15] C12 B13 D12 A13 H12 B12 C11 A11 D11 A10 F11 B10 C10 A9 D10 B9 A17 D15 B17 G14 C17 D16 A18 D17 B18 B20 A19 C20 B19 C19 C18 E17 D20 F17 E18 G15 E19 G17 E20 H15 F18 H17 F19 J14 F20 J15 G20 J18 SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15 SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 RDATA14 RDATA15 RDATA8 RDATA9 RDATA10 RDATA11 RDATA12 RDATA13 RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 H2 K6 H3 L7 G1 K7 G2 K8 G3 K4 F1 J6 F2 J4 E1 H7
OM1 OM2 OM3
1K
D5 B2 D4 F4 C1 G6 C3 F7 D6 A2 D3
1K
1K
GND
nCS1 nCS2 nCS3
nOE nWE
VCC3P3
LDATA[7] LDATA[0] LDATA[1] LDATA[2] LDATA[3] LDATA[4] LDATA[5] LDATA[6]
SIZE FSCM NO.
D
DWG. NO. SHEET
REV
SCALE
H=8ND; V=4LA
8
7
6
5
4
3
2
1
E:\design_\som2416\SOB2472\design_definition\graphics\S3C2416.sbk(_1;17)
Mon Aug 31 11:54:18 2009
TXD1 RXD1 nCTS1 nRTS1 TXD0 RXD0 nCTS0 nRTS0
V7 W6 R8 Y5 P8 V6 W5 R7
TXD1 RXD1 nCTS1 nRTS1 TXD0 RXD0 nCTS0 nRTS0
XTIPLL XTOPLL XTIRTC XTORTC EPLLCAP
V20 U18 W20 T17 V16
GND
GND
B
nRST I2S0_SDO I2S0_SDI I2S0_LCLK I2SO_LRCK I2S0_CDCLK IISSDA IISSCL EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 TMS TDO TDI TCK nTRST
P18 M14 N18 M15 U6 V4RTCK W4 U5 V8 CLKOUT Y7 R17 U17 V19 U16 V18
nRST
VCC3P3
C
8 1
7 2
6 3
5TP1 4 10K
C
GND
OM[0]=0:XTI OM[1]= OM[0]=0:XTI OM[0]=0:XTI OM[0]=0:XTI
7 2
LED-0603 LED-0603
V12 W13 U12 Y14
SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3
SD1_CMD Y12 SD1_CLK U11
RGB_LEDN RGB_VCLK RGB_HSYNC RGB_VSYNC RGB_VDEN GPC5 GPC6 GPC7
VCC3P3
RN35 5 6 6 7 7 8 8 nTRST 2 GND 4 VDD 6 NC 8 SOC_JTAG 4 43 3 2 2 1 1 10K
VCC3P3
LRCLK
J2 1 3 5 7 TDI TDO TCK TMS
VCC3P3
LDATA_BUS
DDR2&FLASH
nSWE nSRAS nSCAS nSCLK
DDR2_CS
FCLE FALE nFWE nFRE nFCE RnB
BA2
SCKE SCLK
ຫໍສະໝຸດ Baidu
A
DQM1 DQM0
DQS1 DQS0
CONTRACT NO.
NAND_FLASH
A
DATE
BUS_CLK
APPROVALS DRAWN CHECKED ISSUED
8
7
6
5
4
VD VD[0] VD[1] VD[2] VD[3] VD[4] VD[5] VD[6] VD[7] VD[8] VD[9] VD[10] VD[11] VD[12] VD[13] VD[14] VD[15] VD[16] VD[17] VD[18] VD[19] VD[20] VD[21] VD[22] VD[23]
AIN0 AIN1
GND
TOUCH
VCC3P3
YM YP XM XP
GND
C
A D3
TXD3 RXD3 TXD2 RXD2
Y4 U10 W11 R11 Y11
UCLK TXD3 RXD3 TXD2 RXD2
C
DM_UDEV DN0 DP0 DP_UDEV REXT XIN_UDEV XO_UDEV J20 DN1 L13 DN0 L14 DP0 H19 DP1 H20 K19 K18 44.2 1M 22pF XTAL_DSX321G C73 22pF C72 Y3 12M 1M XTAL_DSX321G 22pF C74 EXTCLK P15 1.8nF C76 22pF C75 22pF C79 1 22pF C78
LOCAL_BUS
1K
B
B
LOCAL_BUS E_INT E_nRST ETH LAN E_INT ETH
nWAIT nRST S3C2416FBGA330 RSMVAD RSMCLK RSMBWAIT
D13 nSWE G12 nSRAS A14 nSCAS F12 nSCCLK
B14 SCKE A15 SCLK
1K LED
D4
6 3 5RN1 4 10K 1K
8 J1 BUZZER L4 PCLK K1 HSYNC L2 VSYNC M4 VDEN M6 LED L1 CF2 N4LVDS_EN 1 U4 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 M3 N7 M2 N8 M1 N6 N1 P6 N2 P7 R4 P1 T3 P2 W2 R1 Y2 R2 W3 T1 V3 U2 U3 V1
V11 SS0 W10 R10 V10 SPIMISO0 SPIMOSI0 SPICLK0
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6/YM AIN7/YP AIN8/XM AIN9/XP VREF
Y19 U14 W18 N11 Y18 P12 V17 V14 W17 R13 U15
SD0DAT3 SD0DAT2 SD0DAT1 SD0DAT0 SD0CMD SD0CLK nSS SPIMISO SPIMOSI SPICLK
W15 R12 Y15 U13 W14 V13
SD0_DATA3 SD0_DATA2 SD0_DATA1 SD0_DATA0 SD0_CMD SD0_CLK