vhdl实例
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第4章典型数字系统的设计
例1、四位十进制频率计的VHDL设计
底层文件一、十进制计数模块CNT10.VHD
Library ieee;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_1164.all;
Entity cnt10 is
Port (clk,clr,ena: in std_logic;
cq: out std_logic_vector(3 downto 0); cout: out std_logic);
end cnt10;
architecture behav of cnt10 is
begin
process(clk,clr,ena)
variable cqi: std_logic_vector(3 downto 0);
begin
if clr='1' then cqi:=(others=>'0');
elsif clk'event and clk='1' then
if ena='1' then
if cqi<9 then cqi:=cqi+1;
else cqi:=(others=>'0');
end if;
end if;
end if;
if cqi=9 then cout<='1';
else cout<='0';
end if;
cq<=cqi;
end process;
end behav;
底层文件二、 16位寄存器REG16
Library ieee;
Use ieee.std_logic_1164.all;
Entity reg16 is
Port (load: in std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0)); end reg16;
architecture behav of reg16 is
begin
process(load,din)
begin
if load'event and load='1' then
dout<=din;
end if;
end process;
end behav;
底层文件三、时序控制模块TEST—CTL Library ieee;
Use ieee.std_logic_unsigned.all; Use ieee.std_logic_1164.all;
Entity test_ctl is
Port ( clkk: in std_logic;
test_en: out std_logic;
load: out std_logic;
clr_cnt: out std_logic); end test_ctl;
architecture behav of test_ctl is signal div2clk :std_logic;
begin
process(clkk)
begin
if clkk'event and clkk='1' then div2clk<=not div2clk;
end if;
end process;
process(clkk,div2clk)
begin
if clkk='0' and div2clk='0' then clr_cnt<='1';
else clr_cnt<='0';
end if;
end process;
load<=not div2clk;
test_en<=div2clk;
end behav;
顶层文件：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequence is
port( f_in : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(15 downto 0); carry_out : out std_logic );
end frequence;
architecture behav of frequence is
component cnt10
port(clk,clr,ena : in std_logic;
cq : out std_logic_vector(3 downto 0);
cout : out std_logic);
end component;
component test_ctl
port( clkk : in std_logic;
test_en : out std_logic;
clr_cnt : out std_logic;
load : out std_logic);
end component;
component reg16
port( load : in std_logic;
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0));
end component;
signal cq1,cq2,cq3,cq4 : std_logic_vector(3 downto 0); signal cq5 : std_logic_vector(15 downto 0);
signal ena1 : std_logic;
signal clr1 : std_logic;
signal cout1,cout2,cout3 : std_logic;
signal load1 : std_logic;