spartan6 核心板原理图
spartan6_MCB使用详解
XILINX MCB使用详解说明：本文档将详细讲述赛灵思的DDR2 IP 核的使用流程，目标芯片为Sparten6系列芯片xc6slx25-2fgg484，ISE版本为12.4，MCB版本为3.5。
应用案例为FPGA芯片外带载两片DDR2芯片进行乒乓操作，目的是用一个PLL驱动两个MCB。
术语：ug382，Xilinx的User Guide，Sparten-6 FPGA Clocking ResourcesUG382(v1.4)August24,2010本人技术有限，不足之处请指正，请发到19861011lsf@，也欢迎讨论，QQ383997593，谢谢！一、核的生成1、打开Xilinx CORE Generator工具，找到MCB核（MIG），2、选择版本，这里以3.5为例（尽量选择最新版本），进入Xilinx Memory Interface Generator界面，单击Next，进入下一步；3、选择输出项，输入自定义模块名；单击Next，注意：如果你是修改一个核而不是第一次生成核，会出现如下对话框，单击Yes,这时会覆盖掉一些文件，因此无论你在接下来的步骤中有没有对核的选项进行修改，最后必须点击Generator；4、单击Next，选择Memory Type；注意到图中有个C1、C3，这是因为Xilinx的MCB有部分是属于硬核，引脚是固定的，分别存在于FPGA芯片的BANK1和BANK3，在代码中将看到很多的信号名是以C1_XXX和C3_XXX开头的，这很容易区分是哪个DDR芯片对应的信号名，注意与后面的端口（Port）混淆；5、单击Next，进入DDR2芯片选项模块，先选择存储器，再输入时钟；这里的Memory Part 选择的是自定义的芯片，单击，输入一个自定义的DDR2芯片名，尽量输入芯片的实名而不是自定义名，这样有利于重复使用，不至于将来使用时不知所云，下面的参数可以在你所选的DDR2芯片DATASHEET中找到，输入参数值，保存，这样就可以在找到自定义的存储器了，单击Next；6、选择同上，单击Next；7、Next；8、Next；9、进入端口配置，（1）选择配置模式，单向与双向的意思是指端口是可读、可写，还是既可读又可写，将端口配置成一个读一个写，其他不用；（2）选择存储器的地址映射方式，可根据自己程序设计方便选择，这里默认；10、Next，这里由于对两个DDR2的操作是相同的，配置同上；Next11、Next；12、Next；13、进入FPGA选项，这里注意系统时钟的方式，根据实际情况选择单端还是差分，这里选择单端其他默认；14、Next，同上；15、Next；16、选择Next；17、Next；18、二、IP核内部文件详解该部分主要尝试描述MCB的时钟部分。
Spartan-6管脚定义及作用
Spartan6系列之器件引脚功能详述由技术编辑于星期四, 09/25/2014 - 14:48 发表1. Spartan-6系列封装概述Spartan-6系列具有低成本、省空间的封装形式，能使用户引脚密度最大化。
所有Spartan-6 LX器件之间的引脚分配是兼容的，所有Spartan-6 LXT器件之间的引脚分配是兼容的，但是Spartan-6 LX和Spartan-6 LXT器件之间的引脚分配是不兼容的。
表格 1Spartan-6系列FPGA封装2. Spartan-6系列引脚分配及功能详述Spartan-6系列有自己的专用引脚，这些引脚是不能作为Select IO使用的，这些专用引脚包括：专用配置引脚，表格2所示，GTP高速串行收发器引脚，表格3所示表格 2Spartan-6 FPGA专用配置引脚注意：只有LX75, LX75T, LX100, LX100T, LX150, and LX150T器件才有VFS、VBATT、RFUSE引脚。
表格 3Spartan-6器件GTP通道数目注意：LX75T在FG(G)484 和 CS(G)484中封装4个GTP通道，而在FG(G)676中封装了8个GTP通道；LX100T在FG(G)484 和 CS(G)484中封装4个GTP通道，而在FG(G)676 和 FG(G)900中封装了8个GTP通道。
如表4，每一种型号、每一种封装的器件的可用IO引脚数目不尽相同，例如对于LX4 TQG144器件，它总共有引脚144个，其中可作为单端IO引脚使用的IO个数为102个，这102个单端引脚可作为51对差分IO使用，另外的32个引脚为电源或特殊功能如配置引脚。
表格 4Spartan6系列各型号封装可用的IO资源汇总表格 5引脚功能详述3. Spartan-6系列GTP Transceiver引脚如表6所示，对LX25T，LX45T而言，只有一个GTP Transceiver通道，它的位置是X0Y0，所再Bank号为101；其他信号GTP Transceiver的解释类似。
Spartan-6datasheetSpartan系列FPGA芯片
DC Commercial 20% overshoot duration 8% overshoot duration(5) DC All user and dedicated Industrial I/Os 20% overshoot duration 4% overshoot duration(5) DC Expanded (Q) 20% overshoot duration VIN and VTS(3) I/O input voltage or voltage applied to 3-state output, relative to GND(4) Commercial 4% overshoot duration(5) 20% overshoot duration 10% overshoot duration Restricted to maximum of 100 user I/Os 20% overshoot duration Industrial 10% overshoot duration 8% overshoot duration(5) 20% overshoot duration Expanded (Q) 10% overshoot duration 8% overshoot duration(5) TSTG Storage temperature (ambient) Maximum soldering temperature(6) (TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256) TSOL Maximum soldering temperature(6) (Pb-free packages: FGG484, FGG676, and FGG900) Maximum soldering temperature(6) (Pb packages: CS484, FT256, FG484, FG676, and FG900) Tj Notes:
xinlinx-Spartan6开发板原理图详解
SP601 Hardware User GuideUG518 (v1.7) September 26, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. Y ou may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at /warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:/warranty.htm#critapps.Revision HistoryThe following table shows the revision history for this document.Date Version Revision07/15/09 1.0Initial Xilinx release.08/19/09 1.1•Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.•Updated Figure1-17.•Updated Table1-4, Table1-19, and Table1-22.•Added introductory paragraph to Appendix C, SP601 Master UCF.•Miscellaneous typographical edits and new user guide template.05/17/10 1.2•Updated Figure1-1, Figure1-2, Figure1-14, Figure1-18, Table1-9, Table1-1,Table1-11, and Table1-16.•Added Figure1-7, Figure1-8, and Table1-13.•Updated 9. VITA 57.1 FMC-LPC Connector, page25, Appendix B, VITA 57.1 FMCLPC Connector Pinout, and Appendix C, SP601 Master UCF.06/16/10 1.3Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. AddedTable1-26. Added UG394, Spartan-6 FPGA Power Management User Guide to Appendix D,References.09/24/10 1.4Added Power System Test Points, including Table1-25.02/16/11 1.5Added note and revised header description to indicate the I/Os support LVCMOS25signaling on page34. Revised oscillator manufacturer information from Epson to SiTimeon page page23 and page51.07/18/11 1.6Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in sectionOscillator (Differential), page23. Added Table1-15, page27.09/26/12 1.7Added Regulatory and Compliance Information, page53.SP601 Hardware User Guide UG518 (v1.7) September 26, 2012SP601 Hardware User Guide 3UG518 (v1.7) September 26, 2012Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1: SP601 Evaluation BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SMA Connectors (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510. Status LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811. FPGA Awake LED and Suspend Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912. FPGA INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3013. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3114. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Power System Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table of ContentsAppendix A: Default Jumper and Switch SettingsAppendix B: VITA 57.1 FMC LPC Connector PinoutAppendix C: SP601 Master UCFAppendix D: ReferencesAppendix E: Regulatory and Compliance InformationDirectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SP601 Hardware User GuideUG518 (v1.7) September 26, 2012SP601 Hardware User Guide 5UG518 (v1.7) September 26, 2012PrefaceAbout This GuideThis manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.Guide ContentsThis manual contains the following chapters:•Chapter 1, SP601 Evaluation Board , provides an overview of the SP601 evaluation board and details the components and features of the SP601 board.•Appendix A, Default Jumper and Switch Settings .•Appendix B, VITA 57.1 FMC LPC Connector Pinout .•Appendix C, SP601 Master UCF .•Appendix D, References .Additional DocumentationThe following documents are available for download at /products/spartan6.•Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family.•Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.•Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.•Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.•Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO™ resources available in all Spartan-6 devices.•Spartan-6 FPG A Clocking Resources User GuidePreface:About This GuideThis guide describes the clocking resources available in all Spartan-6 devices,including the DCMs and PLLs.•Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device block RAM capabilities.•Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6FPGAs andprovides configuration examples.•Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller block, a dedicatedembedded multi-port memory controller that greatly simplifies interfacingSpartan-6FPGAs to the most popular memory standards.•Spartan-6 FPGA PCB Designer’s GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus onstrategies for making design decisions at the PCB and interface level.Additional Support ResourcesTo search the database of silicon and software questions and answers or to create atechnical support case in WebCase, see the Xilinx website at:/support. SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter1 SP601 Evaluation BoardOverviewThe SP601 board enables hardware and software developers to create or evaluate designstargeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.The SP601 provides board features for evaluating the Spartan-6 family that are common tomost entry-level development environments. Some commonly used features include aDDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purposeI/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1expansion connector. Features, page8 provides a general listing of the board features withdetails provided in Detailed Description, page10.Additional InformationAdditional information and support material is located at:•/sp601This information includes:•Current version of this user guide in PDF format•Example design files for demonstration of Spartan-6 FPGA features and technology•Demonstration hardware and software configuration files for the SP601 linear and SPImemory devices•Reference Design Files•Schematics in PDF format and DxDesigner schematic format•Bill of materials (BOM)•Printed-circuit board (PCB) layout in Allegro PCB format•Gerber files for the PCB (Many free or shareware Gerber file viewers are available onthe internet for viewing and printing these files.)•Additional documentation, errata, frequently asked questions, and the latest newsFor information about the Spartan-6 family of FPGA devices, including product highlights,data sheets, user guides, and application notes, see the Spartan-6 FPGA website at/support/documentation/spartan-6.htm.SP601 Hardware User Guide 7 UG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardFeaturesThe SP601 board provides the following features (see Figure1-2 and Table1-1):• 1. Spartan-6 XC6SLX16-2CSG324 FPGA• 2. 128 MB DDR2 Component Memory• 3. SPI x4 Flash• 4. Linear Flash BPI• 5. 10/100/1000 Tri-Speed Ethernet PHY•7. IIC Bus•8Kb NV memory•External access 2-pin header•VITA 57.1 FMC-LPC connector•8. Clock Generation•Oscillator (Differential)•Oscillator Socket (Single-Ended, 2.5V or 3.3V)•SMA Connectors (Differential)•9. VITA 57.1 FMC-LPC Connector•10. Status LEDs•FPGA_AWAKE•INIT•DONE•13. User I/O•User LEDs•User DIP switch•User pushbuttons•GPIO male pin header•14. FPGA_PROG_B Pushbutton Switch•15. Configuration Options• 3. SPI x4 Flash (both onboard and off-board)• 4. Linear Flash BPI•JTAG Configuration•16. Power Management•AC Adapter and 5V Input Power Jack/Switch•Onboard Power Supplies SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Related Xilinx DocumentsBlock DiagramFigure1-1 shows a high-level block diagram of the SP601 and its peripherals.Figure 1-1:SP601 Features and BankingRelated Xilinx DocumentsPrior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.See the following locations for additional documentation on Xilinx tools and solutions:•ISE: /ise•Answer Browser: /support•Intellectual Property: /ipcenterSP601 Hardware User Guide 9 UG518 (v1.7) September 26, 2012SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardDetailed DescriptionFigure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.Figure 1-2:SP601 Board PhotoUG518_02_09100912843126137115109141581316Table 1-1:SP601 FeaturesNumberFeatureNotesSchematic Page1 Spartan-6 FP G A XC6SLX16-2CS G 3242DDR2 Component Elpida EDE1116ACBG 1Gb DDR2SDRAM53SPI x4 Flash and Headers SPI select and External Headers 84Linear Flash BPIStrataFlash 8-bit (J3 device), 3 pins shared w/ SPI x481. Spartan-6 XC6SLX16-2CSG 324 FPGAA Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.ReferencesSee the Spartan-6 FPGA Data Sheet . [Ref 1]ConfigurationThe SP601 supports configuration in the following modes:•Master SPI x4•Master SPI x4 with off-board device •BPI•JTAG (using the included USB-A to Mini-B cable)For details on configuring the FPGA, see 15. Configuration Options .The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.ReferencesSee the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]510/100/1000 Ethernet PHY GMII Marvell Alaska PHY76RS232 UART (USB Bridge)Uses CP2103 Serial-to-USB connection 107IICGoes to Header and VITA 57.1 FMC 108Clock, socket, SMA Differential, Single-Ended, Differential 99VITA 57.1 FMC-LPC connector LVDS signals, clocks, PRSNT 610LEDs Ethernet PHY Status711LED, Header FPGA Awake LED, Suspend Header 812LEDs FPGA INIT, DONE 913LED User I/O (active-High)9DIP SwitchUser I/O (active-High)9PushbuttonUser I/O, CPU_RESET (active-High)912-pin (8 I/O) Header6 pins x 2 male header with 8 I/Os (active-High)1014Pushbutton FPGA_PROG_B915USB JTAG Cypress USB to JTAG download cable logic14, 1516Onboard PowerPower Management11,12,13Table 1-1:SP601 Features (Cont’d)NumberFeatureNotesSchematic PageSP601 Hardware User Guide I/O Voltage RailsThere are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Table 1-2.ReferencesSee the Spartan-6 FPGA documentation for more information at /support/documentation/spartan-6.htm .2. 128 MB DDR2 Component MemoryThere are 128MB of DDR2 memory available on the SP601 board. A 1-Gb ElpidaEDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface’s 16-bit data path using SSTL18 signaling. The SP601 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 625Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4.Table 1-2:I/O Voltage Rail of FPGA BanksFPGA BankI/O Voltage Rail0 2.5V 1 2.5V 2 2.5V 31.8VTable 1-3:Termination Resistor RequirementsSignal NameBoard TerminationOn-Die TerminationDDR2_A[14:0]49.9Ω to V TT DDR2_BA[2:0]49.9Ω to V TT DDR2_RAS_N 49.9Ω to V TT DDR2_CAS_N 49.9Ω to V TT DDR2_WE_N 49.9Ω to V TT DDR2_CS_N 100Ω to GND DDR2_CKE 4.7K Ω to GND DDR2_ODT 4.7K Ω to GNDDDR2_DQ[15:0]ODT DDR2_UDQS[P ,N], DDR2_LDQS[P ,N]ODT DDR2_UDM, DDR2_LDMODTTable 1-5 shows the connections and pin numbers for the DDR2 Component Memory.DDR2_CK[P ,N]100Ω differential at memorycomponentNotes:1.Nominal value of V TT for DDR2 interface is 0.9V .Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements FPGA U1 PinFPGA Pin NumberBoard Connection for OCTZIO L6No Connect RZQC2100Ω to GROUNDTable 1-5:DDR2 Component Memory ConnectionsFPGA U1 PinSchematic Net Name Memory U2Pin NumberPin NameJ7DDR2_A0M8A0J6DDR2_A1M3A1H5DDR2_A2M7A2L7DDR2_A3N2A3F3DDR2_A4N8A4H4DDR2_A5N3A5H3DDR2_A6N7A6H6DDR2_A7P2A7D2DDR2_A8P8A8D1DDR2_A9P3A9F4DDR2_A10M2A10D3DDR2_A11P7A11G6DDR2_A12R2A12L2DDR2_DQ0G8DQ0L1DDR2_DQ1G2DQ1K2DDR2_DQ2H7DQ2K1DDR2_DQ3H3DQ3H2DDR2_DQ4H1DQ4H1DDR2_DQ5H9DQ5J3DDR2_DQ6F1DQ6Table 1-3:Termination Resistor Requirements (Cont’d)Signal NameBoard Termination On-Die TerminationSP601 Hardware User Guide ReferencesSee the Elpida DDR2 SDRAM Specifications for more information. [Ref 11]Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3]J1DDR2_DQ7F9DQ7M3DDR2_DQ8C8DQ8M1DDR2_DQ9C2DQ9N2DDR2_DQ10D7DQ10N1DDR2_DQ11D3DQ11T2DDR2_DQ12D1DQ12T1DDR2_DQ13D9DQ13U2DDR2_DQ14B1DQ14U1DDR2_DQ15B9DQ15F2DDR2_BA0L2BA0F1DDR2_BA1L3BA1E1DDR2_BA2L1BA2E3DDR2_WE_B K3WE L5DDR2_RAS_B K7RAS K5DDR2_CAS_B L7CAS K6DDR2_ODT K9ODT G3DDR2_CLK_P J8CK G1DDR2_CLK_N K8CK H7DDR2_CKE K2CKE L4DDR2_LDQS_P F7LDQS L3DDR2_LDQS_N E8LDQS P2DDR2_UDQS_P B7UDQS P1DDR2_UDQS_N A8UDQS K3DDR2_LDM F3LDM K4DDR2_UDMB3UDMTable 1-5:DDR2 Component Memory Connections (Cont’d)FPGA U1 PinSchematic Net Name Memory U2Pin NumberPin Name3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing anexternal SPI flash memory device.The SP601 SPI interface has two parallel connected configuration options (see Figure1-4):an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flashprogramming header (J12). J12 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J15. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-3:J12 SPI Flash Programming HeaderSP601 Hardware User Guide ReferencesSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12]See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsFPGA U1 PinSchematic Net Name SPI MEM U17SPI HDR J12Pin #Pin NamePinNumberPin NameV2FPGA_PROG_B 1V14FPGA_D2_MISO31IO3_HOLD_B 2T14FPGA_D1_MISO2_R 9IO2_WP_B3V3SPI_CS_B4TMS T13FPGA_MOSI_CSI_B_MISO015DIN 5TDI R13FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO R15FPGA_CCLK16CLK7TCK 8GND 9VCC3V3J15.2SPIX4_CS_B 7CS_B4. Linear Flash BPIAn 8-bit (16MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used toprovide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; theSpartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels todirectly access the linear flash BPI through a 2.5V bank. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-5:Linear Flash BPI InterfaceTable 1-7:BPI Memory ConnectionsFPGA U1 Pin Schematic Net Name BPI Memory U10Pin Number Pin Name K18FLASH_A032A0K17FLASH_A128A1J18FLASH_A227A2J16FLASH_A326A3G18FLASH_A425A4G16FLASH_A524A5H16FLASH_A623A6H15FLASH_A722A7H14FLASH_A820A8H13FLASH_A919A9F18FLASH_A1018A10F17FLASH_A1117A11K13FLASH_A1213A12K12FLASH_A1312A13E18FLASH_A1411A14E16FLASH_A1510A15G13FLASH_A168A16SP601 Hardware User Guide Note:Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made availablefor larger density devices.ReferencesSee the Numonyx Embedded Flash Memory Data Sheet for more information. [Ref 13]In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]H12FLASH_A177A17D18FLASH_A186A18D17FLASH_A195A19G14FLASH_A204A20F14FLASH_A213A21C18FLASH_A221A22C17FLASH_A2330A23F16FLASH_A2456A24R13FPGA_D0_DIN_MISO_MISO133DQ0T14FPGA_D1_MISO235DQ1V14FPGA_D2_MISO338DQ2U5FLASH_D340DQ3V5FLASH_D444DQ4R3FLASH_D546DQ5T3FLASH_D649DQ6R5FLASH_D751DQ7M16FLASH_WE_B 55WE_B L18FLASH_OE_B 54OE_B L17FLASH_CE_B14CE0B3FMC_PWR_GOOD_FLASH_RST_B16RP_BTable 1-7:BPI Memory Connections (Cont’d)FPGA U1 PinSchematic Net NameBPI Memory U10Pin NumberPin Name5. 10/100/1000 T ri-Speed Ethernet PHYThe SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface fromthe FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through aHalo HFJ11-1G01E RJ-45 connector with built-in magnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table1-8. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-8:PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0V CC 2.5V PHYADR[2] = 1PHYADR[1] = 1PHYADR[0] = 1 CFG1Ground ENA_PAUSE = 0PHYADR[4] = 0PHYADR[3] = 0 CFG2V CC 2.5V ANEG[3] = 1ANEG[2] = 1ANEG[1] = 1 CFG3V CC 2.5V ANEG[0] = 1ENA_XC = 1DIS_125 = 1 CFG4V CC 2.5V HWCFG_MD[2] = 1HWCFG_MD[1] = 1HWCFG_MD[0] = 1 CFG5V CC 2.5V DIS_FC = 1DIS_SLEEP = 1HWCFG_MD[3] = 1 CFG6PHY_LED_RX SEL_BDT = 0INT_POL = 175/50Ω = 0 Table 1-9:Ethernet PHY ConnectionsFPGA U1 Pin Schematic Net NameU3 M88E111Pin Number Pin NameP16PHY_MDIO33MDIO N14PHY_MDC35MDC J13PHY_INT32INT_B L13PHY_RESET36RESET_B M13PHY_CRS115CRS L14PHY_COL114COL L16PHY_RXCLK7RXCLK P17PHY_RXER8RXER N18PHY_RXCTL_RXDV4RXDV M14PHY_RXD03RXD0 U18PHY_RXD1128RXD1 U17PHY_RXD2126RXD2 T18PHY_RXD3125RXD3 T17PHY_RXD4124RXD4 N16PHY_RXD5123RXD5SP601 Hardware User GuideReferencesSee the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.[Ref 16]Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide . [Ref 5]N15PHY_RXD6121RXD6P18PHY_RXD7120RXD7A9 PHY_TXC_G TPCLK 14G TXCLKB9 PHY_TXCLK 10TXCLK A8 PHY_TXER 13TXER B8 PHY_TXCTL_TXEN 16TXEN F8 PHY_TXD018TXD0G 8 PHY_TXD119TXD1A6 PHY_TXD220TXD2B6 PHY_TXD324TXD3E6 PHY_TXD425TXD4F7 PHY_TXD526TXD5A5 PHY_TXD628TXD6C5 PHY_TXD729TXD7Table 1-9:Ethernet PHY Connections (Cont’d)FPGA U1 PinSchematic Net NameU3 M88E111Pin NumberPin Name6. USB-to-UART BridgeThe SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10 details the SP601 J9 pinout.Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS).Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computercommunications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.ReferencesRefer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.In addition, see some of the Xilinx UART IP specifications at:•/support/documentation/ip_documentation/xps_uartlite.pdf •/support/documentation/ip_documentation/xps_uart16550.pdfTable 1-10:USB Type B Pin Assignments and Signal DefinitionsUSB ConnectorPinSignal NameDescription1VBUS +5V from host system (not used)2USB_DATA_N Bidirectional differential serial data (N-side)3USB_DATA_P Bidirectional differential serial data (P-side)4GROUNDSignal groundTable 1-11:CP2103GM ConnectionsFPGA U1 PinUART Functionin FPGA Schematic Net Name U4 CP2103GMPinUART Function in CP2103GM U10RTS, output USB_1_CTS 22CTS, input T5CTS, input USB_1_RTS 23RTS, output L12TX, data out USB_1_RX 24RXD, data in K14RX, data inUSB_1_TX25TXD, data out。
Ompal138+Spartan-6FPGA核心板规格软硬件资料数据手册
Ompal138+Spartan-6FPGA核心板规格软硬件资料数据手册核心板简介创龙科技SOM-TL138F是一款基于TI OMAP-L138（定点/浮点DSP C674x + ARM9) + 紫光同创Logos/Xilinx Spartan-6低功耗FPGA处理器设计的工业级核心板。
核心板内部OMAP-L138与Logos/Spartan-6通过uPP、EMIFA、I2C通信总线连接，并通过工业级B2B连接器引出网口、EMIFA、SATA、USB、LCD等接口。
核心板经过专业的PCB Layout和高低温测试验证，稳定可靠，可满足各种工业应用环境。
用户使用核心板进行二次开发时，仅需专注上层运用，降低了开发难度和时间成本，可快速进行产品方案评估与技术预研。
图 1 核心板正面图图 2 核心板背面图图 3 核心板斜视图图 4 核心板侧视图典型应用领域•运动控制•电力设备•仪器仪表•医疗设备•通信探测•惯性导航软硬件参数硬件框图图 5 核心板硬件框图图 6 OMAP-L138资源框图图 7 Logos特性图 8 Spartan-6特性硬件参数表 1 OMAP-L138端硬件参数CPU CPU型号：TI OMAP-L1381x ARM9，主频456MHz1x DSP C674x，主频456MHz，支持浮点运算1x PRU-ICSS，含2个PRU(Programmable Real-time Unit)核心ROM512MByte NAND FLASH RAM128/256MByte DDR2LED 1x 电源指示灯2x 用户可编程指示灯B2B Connector 2x 80pin公座B2B连接器，2x 80pin母座B2B连接器，间距0.5mm，共320pin硬件资源1x VPIF Video OUT（支持SDTV和HDTV），ITU-BT.656 Format，ITU-BT.1120 and SMTPE296 Formats1x VPIF Video IN（支持SDTV，HDTV和Raw Capture Mode），ITU-BT.656 Format，ITU-BT.1120 and SMTPE296 Formats1x LCD Controller1x USB 1.1 HOST1x USB 2.0 OTG1x 10/100M Ethernet1x SATA2x MMC/SD/SDIO3x UART2x eHRPWM1x EMIFA，在核心板内部与FPGA通过普通IO连接3x eCAP2x I2C1x HPI1x uPP，在核心板内部与FPGA通过普通IO连接，可配置为1x 16bit或2x 8bit2x McBSP1x McASP2x SPI备注：B2B、电源、指示灯等部分硬件资源，OMAP-L138与FPGA共用。
108991-创龙Spartan-6平台资料-SOM-TLS6核心板功耗测试
功耗。
ห้องสมุดไป่ตู้
23 潘敏如 底板加核心板（跑程序）上电时的核心板最大稳定功耗 4.99
0.121
0.60379
SOM-TLS6-A1核心板功耗测试
底板加核心板（不跑程序）上电功耗 4.94 0.143 0.70642
A2底板+核心板方式进行。 即所有外设都工作的情况。 的底板最大稳定功耗是指直流电机转动到最大速率时的功耗。 况下测试数据，非满负荷情况下功耗
2017.08.23
M-TLS6-A1核心板功耗测试
SOM-TLS6-A
名称 底板上电（无核心板）功耗 电压(V) 4.95 电流(mA) 0.129 功耗(W) 0.63855
备注：1.功耗测试采用广州创龙TLS6Box-A2底板+核心板方式进行。 2.测试程序领用综合例程来测试，即所有外设都工作的情况。 3.底板加核心板（跑程序）上电时的底板最大稳定功耗是指直流电机转动到最大速率时的功耗。 4.以上测试功耗为软件正常运行情况下测试数据，非满负荷情况下功耗
TMS320C6748 + Spartan-6工业核心板规格书
Revision HistoryDraft Date Revision No. Description2017/12/18 V1.2 1.排版修改。
2.更新为A2版，替换封面、产品图，新增硬件框图。
3.修改附录A例程。
4.修改产品订购型号及替换产品参数解释图。
5.修改硬件参数命名及区分DSP端和FPGA端参数。
2016/2/4 V1.1 1.排版修改。
2014/12/24 V1.0 1.初始版本。
目录1 核心板简介 (4)2 典型运用领域 (5)3 软硬件参数 (6)4 开发资料 (8)5 电气特性 (8)6 机械尺寸图 (9)7 产品认证 (9)8 产品订购型号 (10)9 技术支持 (11)10 增值服务 (11)更多帮助....................................................................................................... 错误!未定义书签。
附录A 开发例程.. (13)1TMS320C6748核心板简介基于TI TMS320C6748（定点/浮点DSP C674x）+ Xilinx Spartan-6 FPGA处理器；TMS320C6748与FPGA通过uPP、EMIFA、I2C总线连接，通信速度可高达228MByte/s； TMS320C6748主频456MHz，高达3648MIPS和2746MFLOPS的运算能力；FPGA兼容Xilinx Spartan-6 XC6SLX9/16/25/45，平台升级能力强；DSP+FPGA双核核心板，尺寸为66mm*38.6mm，采用工业级B2B连接器，保证信号完整性；支持裸机、SYS/BIOS操作系统。
图 1 核心板正面图图 2 核心板背面图图 3 核心板斜视图由广州创龙自主研发的SOM-TL6748F核心板是一款定点/浮点DSP C674x + Xilinx Sp artan-6 FPGA工业级双核核心板，66mm*38.6mm，功耗小、成本低、性价比高。
108992-创龙Spartan-6平台资料-SOM-TLS6核心板引脚说明20170526
说明：I =Input, O=Output,I/O =Bidirec
设计注意提示
1.CPU外部晶振频率为24MHz。
2.核心板的I2C总线已用2.2K电阻上拉至
3.3V。
3.利用核心板进行设计底板时，请认真核对自己底板的核心板B2B连接器的信号引脚线序是否正确，连接样的B2B物料,可以联系我司采购。
4.有关信号详细功能，请查看芯片datasheet。
5.FPGA端管脚名中带前缀“n”的，在LX9/LX25/LX45中可能悬空
SOM-TLS6-A1核心板B2
directional,Z=Highimpedance, PWR=Supply voltage,GND=Ground
自己底板的核心板B2B连接器的信号引脚线序是否正确，连接器的摆放位置是否正确，请务必参考我司提供的底板PC 能悬空；具体请参考Xilinx用户指导文档：UG385
心板B2B信号列表
，请务必参考我司提供的底板PCB图进行核对。
核心板同
SOM-TLS6-A1核心板B2B信
B2B信号列表。
Spartan6系列之器件引脚功能详述
1.Spartan-6系列封装概述Spartan-6系列具有低成本、省空间的封装形式，能使用户引脚密度最大化。
所有Spartan-6LX器件之间的引脚分配是兼容的，所有Spartan-6LXT 器件之间的引脚分配是兼容的，但是Spartan-6LX和Spartan-6LXT器件之间的引脚分配是不兼容的。
表格1Spartan-6系列FPGA封装2.Spartan-6系列引脚分配及功能详述Spartan-6系列有自己的专用引脚，这些引脚是不能作为Select IO使用的，这些专用引脚包括：∙专用配置引脚，表格2所示∙GTP高速串行收发器引脚，表格3所示表格2Spartan-6FPGA专用配置引脚注意：只有LX75,LX75T,LX100,LX100T,LX150,and LX150T器件才有VFS、VBATT、RFUSE引脚。
表格3Spartan-6器件GTP通道数目注意：LX75T在FG(G)484和CS(G)484中封装4个GTP通道，而在FG(G)676中封装了8个GTP通道；LX100T在FG(G)484和CS(G)484中封装4个GTP通道，而在FG(G)676和FG(G)900中封装了8个GTP通道。
如表4，每一种型号、每一种封装的器件的可用IO引脚数目不尽相同，例如对于LX4TQG144器件，它总共有引脚144个，其中可作为单端IO引脚使用的IO个数为102个，这102个单端引脚可作为51对差分IO使用，另外的32个引脚为电源或特殊功能如配置引脚。
表格4Spartan6系列各型号封装可用的IO资源汇总表格5引脚功能详述引脚名方向描述User I/O PinsIO_LXXY_#Input/Output IO表示这是一个具有输入输出功能的引脚，XX表示该引脚在其Bank内的惟一标识，Y表示是差分引脚的P还是N引脚Multi-Function PinsIO_LXXY_ZZZ_#Zzz代表该引脚除IO功能之外的其他功能，Dn Input/Output(duringreadback)在SelectMAP/BPI模式中，D0—D15是用于配置操作的数据引脚，在从SelectMAP的回读阶段，当RDWR_B为低电平时，Dn为输出引脚，在配置过程结束后，该引脚可作为通用IO口使用D0_DIN_MISO_MISO1Input在Bit-serial模式中，DIN是惟一的数据输入引脚；在SPI模式中，MISO是主输入从输出引脚；在SPI x2or x4模式中，MISO1是SPI总线的第二根数据线；D1_MISO2, D2_MISO3Input在SelectMAP/BPI模式中，D1、D2是配置数据线的低2bit；在SPIx4模式中，MISO2和MISO3是SPI总线的数据线的高2bitAn Output在BPI模式中A0—A25是输出地址线，配置完成后，它们可作为普通IO使用AWAKE Output挂起模式中的状态输出引脚，如果没有使能挂起模式，该引脚可作为普通IO引脚MOSI_CSI_B_MISO0Input/Output 在SPI配置模式中的主输出从输入引脚；在SelectMAP模式中，CSI_B是低有效的Flash片选信号；在SPI x2or x4模式中，这是最低数据线FCS_B Output在BPI模式中，BPI flash的片选信号FOE_B Output在BPI模式中，BPI flash的输出使能FWE_B Output在BPI模式中，BPI flash写使能LDC Output在BPI模式中，在配置阶段LDC保持低电平HDC Output在BPI模式中，在配置阶段HDC保持低电平CSO_B Output在SelectMAP/BPI模式中，菊花链片选信号；在SPI模式中，是SPI Flash的片选信号；IRDY1/2,TRDY1/2Output使用PCI的IP Core时，它们作为IRDY和TRDY信号DOUT_BUSY Output在SelectMAP模式中，BUSY表示设备状态；在Bit-serial模式中，DOUT输出数据给菊花链下游的设备RDWR_B_VREF Input在SelectMAP模式中，RDWR_B是低有效的写使能信号；配置完成后，可当做普通IO使用HSWAPEN Input当是低电平时，在配置之前将所有IO上拉INIT_B Bidirectional(open-drain)低电平表示配置存储器是空的；当被拉低时，配置将被延时；如果在配置过程中变低，表示在配置过程中出现了错误；当配置结束后，这个引脚表示POST_CRC错误；SCPn Input SCP0-SCP7是挂起控制引脚CMPMOSI,CMPMISO,CMPCLKN/A保留为将来使用，可用作普通IOM0,M1Input配置模式，M0=0表示并行配置模式，M0=1表示串行配置模式；M1=0表示主模式，M1=1表示从模式CCLK Input/Output配置时钟，主模式下是输出时钟，从模式下是输入时钟USERCCLK Input主模式下可选的的用户输入配置时钟GCLK Input全局时钟引脚，它们可当做普通IO使用VREF_#N/A参考门限时钟引脚，当不用时可作为普通IO使用Multi-Function Memory Controller PinsM#DQn Input/Output#Bank的存储控制器数据线M#LDQS Input/Output#Bank的存储控制器数据使能引脚M#LDQSN Input/Output#Bank的存储控制器数据使能引脚NM#UDQS Input/Output#Bank的存储控制器高位数据使能M#UDQSN Input/Output#Bank的存储控制器高位数据使能NM#An Output#Bank的存储控制器地址线A[0:14]M#BAn Output#Bank的存储控制器块地址线BA[0:2]M#LDM Output#Bank的存储控制器低数据屏蔽M#UDM Output#Bank的存储控制器高数据屏蔽M#CLK Output#Bank的存储控制器时钟M#CLKN Output#Bank的存储控制器时钟NM#CASN Output#Bank的存储控制器列地址使能M#RASN Output#Bank的存储控制器行地址使能M#ODT Output#Bank的存储控制器终端电阻控制M#WE Output#Bank的存储控制器写使能M#CKE Output#Bank的存储控制器时钟使能M#RESET Output#Bank的存储控制器复位Dedicated PinsDONE_2Input/Output 带可选上拉电阻的双向信号，作为输出，它代表配置过程的完成；作为输入，拉低可用来延迟启动PROGRAM_B_2Input异步复位配置逻辑SUSPEND Input高电平使芯片进入挂起模式TCK Input JTAG边界扫描时钟TDI Input JTAG边界扫描数据输入TDO Output JTAG边界扫描数据输出TMS Input JTAG边界扫描模式Reserved PinsNC N/A未连接引脚CMPCS_B_2Input保留引脚，不连接或接VCCO_2Other PinsGND N/A地VBATT N/A只存在于LX75,LX75T,LX100,LX100T,LX150和LX150T芯片，解码关键存储器备用电源；若不使用关键存储器，则可将之连接VCCAUX、GND或者直接不连接VCCAUX N/A辅助电路的供电电源VCCINT N/A内部核逻辑资源VCCO_#N/A#Bank的输出驱动器供电电源VFS Input只存在于LX75,LX75T,LX100,LX100T,LX150,和LX150T芯片；解码器key EFUSE编程过程使用的供电电源，若不使用关键熔丝，则将该引脚连接到VCCAUX、GND或者直接不连接RFUSE Input只存在于LX75,LX75T,LX100,LX100T,LX150和LX150T；用于编程的解码器key EFUSE电阻，如果不编程或者不使用key EFUSE，则将该引脚连接到VCCAUX、GND或者直接不连接3.Spartan-6系列GTP Transceiver引脚引脚名方向描述GTP Transceiver PinsMGTAVCCN/A 收发器混合电路供电电源MGTAVTTTX,MGTAVTTRXN/A TX 、RX 电路供电电源MGTAVTTRCALN/A 电阻校准电路供电电源MGTAVCCPLL0MGTAVCCPLL1N/A PLL 供电电源MGTREFCLK0/1PInput 正极参考时钟MGTREFCLK0/1NInput负极参考时钟MGTRREFInput 内部校准电路的精密参考电阻MGTRXP[0:1]Input 收发器接收端正极MGTRXN[0:1]Input 收发器接收端负极MGTTXP[0:1]Output 收发器发送端正极MGTTXN[0:1]Output 收发器发送端负极如表6所示，对LX25T，LX45T 而言，只有一个GTP Transceiver 通道，它的位置是X0Y0，所再Bank 号为101；其他信号GTP Transceiver 的解释类似。
Spartan-6系列FPGA UART数据接收模块总结
Spartan-6系列FPGA 的UART 数据接收模块总结一、准备工作：1. UART 通信协议（关键）；2. 开始的第一步，检测到RX 数据线上下降沿（起始位）；3. 调试助手发送数据的波特率设置，进而设计采样频率；4. 对接收的数据进行处理，去头去尾只留中间数据位（8位）；5. 对接收到的数据通过LED 灯进行验证。
UART 通信协议（一帧11位）：二、功能框图：LED 灯图1- 1 UART 通信协议原理示意图图1- 2 各模块信息传输示意图Detect_module检测RX 下降沿RXH2L_SigBPS_module数据采集脉冲模块BPS_CLKrx_control _module数据接收控制模块Count_SigRX_Datacontrol _module总控制模块RX_Done_SigRX_En_Sigrx_module1. 详细过程说明：● 瞭望员（detect_module ）：正在安逸的晒太阳，突然警报拉响（detect_module 检测到下降沿），瞭望员马上升旗放狼烟（输出H2L_Sig （High to Low 下降沿）为高），告诉后方人员有数据来袭（数据采取单个有序的进攻战法），准备好作战（数据接受工作）。
● 战地指挥中心（rx_control_module ）：一旦看到升旗放狼烟，指挥中心马上给第一团发指令（Count_Sig ），● 情报中心（数据采集脉冲模块BPS_module ）：接收到指令后立即侦查敌情（数据传输波特率），并开始固定周期的不间断扫描，以匹配对方来袭速度（波特率），一旦发现目标，就给战地指挥中心发信号（BPS_CLK ），然后战地指挥中心指挥狙击手逐个歼灭，并把歼灭和捕获的数据记录下来（存入RX_Data 中）。
● 总指挥（control_module ）：战争结束后，战地指挥中心向总指挥汇报指令（RX_Done_Sig ），把歼灭和捕获的数据（RX_Data ）上报给总指挥，然后总指挥根据数据（RX_Data ）控制LED 灯，以表嘉奖。
Spartan-6 系列概述
注： 1. 这些封装中的器件上无存储器控制器。 2. 在 CSG225 封装的 XC6SLX9 和 XC6SLX16 器件上的存储器控制器模块支持为 x8。在 XC6SLX4 中无存储器控制器。 3. 在标准订购选项中，这些器件可提供含铅与不含铅（附加 G）的封装版本。 4. 这些封装均在 XC6SLX75、XC6SLX75T、XC6SLX100、XC6SLX100T、XC6SLX150 和 XC6SLX150T 器件中支持 4 个存储器控制器中的 2 个。
可配置逻辑模块 (CLB) 器件 逻辑 单元(1) 3,840 9,152 14,579 24,051 43,661 74,637 101,261 147,443 24,051 43,661 74,637 101,261 147,443 Slice(2) 600 1,430 2,278 3,758 6,822 11,662 15,822 23,038 3,758 6,822 11,662 15,822 23,038 触发器 4,800 11,440 18,224 30,064 54,576 93,296 126,576 184,304 30,064 54,576 93,296 126,576 184,304 最大分布 DSP48A1 Slice(3) 式 RAM (Kb) 75 90 136 229 401 692 976 1,355 229 401 692 976 1,355 8 16 32 38 58 132 180 180 38 58 132 180 180 Block RAM 模块 18 KB(4) 12 32 32 52 116 172 268 268 52 116 172 268 268 PCI 最大 存储器控制 总 I/O 最大用户 Express CMT 器模块 GTP 收 (5) 端点 bank 数 I/O 数 (6) 最大 (Kb) 数量 发器数 （最大） 模块数 216 576 576 936 2,088 3,096 4,824 4,824 936 2,088 3,096 4,824 4,824 2 2 2 2 4 6 6 6 2 4 6 6 6 0 2 2 2 2 4 4 4 2 2 4 4 4 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 2 4 8 8 8 4 4 4 4 4 6 6 6 4 4 6 6 6 132 200 232 266 358 408 480 576 250 296 348 498 540
Spartan-6时钟管理模块的介绍与使用
Spartan-6时钟管理模块的介绍与使用同步时序电路设计中最关键的是时钟设计，随着电路规模与速度的提高，对时钟的周期、占空比、延时和抖动等方面的要求也越来越高。
为了顺应这需求，Spartan-6系统器件在原有的ＤＣＭ模块基础引入了模拟ＰＬＬ模块构成了功能强大、控制灵活的时钟管理模块（ＣＭＴ）。
每个ＣＭＴ模块包含两个ＤＣＭ模块和一个ＰＬＬ模块。
Spartan-6系统器件有多至六个CMT模块。
一、器件组成与特性1．ＤＣＭ模块主要有以下功能模块组成：a.DLL模块, 主要由延时线和控制逻辑组成。
b.数字频率合成器，为系统产生丰富的频率合成信号输出到CLKFX和CLKFX180。
可以提供2~32的倍乘与1~32的分频系数。
c.数字移相器, 可提供粗调的0，90，180，270度移相和具有动态调节能力的相位细调。
d.数字频谱合成器，产生扩频时钟减少电磁干扰（EMI）。
Spartan-6 DCM模块提供给用户的设计原语有DCM_SP和DCM_CLKGEN，DCM_SP在Spartan-3E FPGA器件中也有，而DCM_CLKGEN是Spartan-6新增的，可以用产生动态的频率合成信号和扩频时钟。
2．PLL模块，有一400MHz~1000 MHz压控振荡器（VCO），可提供8种移相(0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)和6个可独立编程倍乘与分频系数的输出信号。
提供给用户的设计原语有PLL_BASE和PLL_ADV，PLL_BASE是单独使用PLL模块最常调用的原语，允许使用PLL的最常用特性，PLL_ADV包括PLL_BASE所有的特性之外，还提供时钟切换及与DCM的连接。
可用于以下工作模式：a. 时钟网络去歪斜b. 频率合成c. 抖动滤波d. 零延时的缓冲f. PLL与PLL、DCM的级联二、使用指南1．注意时钟的输入与输出范围,所有应用不能超过范围.。
[笔记]Spartan6和Spartan3A
![[笔记]Spartan6和Spartan3A](https://img.taocdn.com/s3/m/01a86d3315791711cc7931b765ce05087632758e.png)
[笔记]Spartan6和Spartan3A来源：Spartan6时钟资源管理介绍1．注意时钟的输入与输出范围,所有应用不能超过范围.。
如Spartan-6 器件DCM的DLL模块的时钟输入范围如下（以下摘自Spartan-6 DATA SHEET）：速度等级为-1L的为器件5MHz~175MHz。
速度等级为2的为器件5MHz~250MHz。
速度等级为3和4的为器件5MHz~280MHz。
4．PLL与DCM的级联选择a. PLL输出驱动DCM模块，优点是在输入DCM模块前可减少输入时钟的抖动，同时又可以使用户能构访问所有DCM模块的输出信号，一个PLL可以驱动多个DCM模块，并不要求PLL与DCM都是在同一CMT模块内。
b. DCM模块输出驱动PLL模块，这种情况可以减少输入时钟和DCM时钟输出的总体抖动。
如果DCM输出直接连到PLL输入，要求PLL与DCM都是在同一CMT模块内，这种情况可减少的本地噪声与专用布线资源。
如果PLL与DCM不在同一CMT模块内，DCM输出必须经过BUFG缓冲后连到PLL。
由于PLL输入信号的限制, 最多只有两个DCM输出信号可以连到一个PLL模块.c. PLL与PLL的级联, 级联PLL可以产生更大范围的时钟, 两个PLL的级联也要通过BUFG缓冲, 此时器件通路的抖动最小。
Spartan3A型号是XC3S400A-5FG320 ，板子采用100MHZ的系统时钟，单端接口Spartan6型号是XC6SLX150T-3FGG900 ，板子采用74.25MHZ 的系统时钟，双端差分接口Spartan6型号是XC6SLX16-3CSG324 ，板子采用100MHZ的系统时钟，单端接口2013-04-03 11:00:14ISE工具下-->Edit-->Language T emplates...有许多源语可以参考，再详细的可以看资料手册。
Spartan 6中CLOCKSpartan-6 FPGA Clocking Resources UG382 (v1.6) May 12, 2011Chapter 1: Clock ResourcesClock ResourcesThe Spartan-6 FPGA clock resources consist of four types of connections:· Global clock input pads (GCLK)· Global clock multiplexers (BUFG, BUFGMUX)· I/O clock buffers (BUFIO2, BUFIO2_2CLK, BUFPLL)· Horizontal clock routing buffers (BUFH)Spartan 3A中ERROR解决：问题一：ERROR:Place:864 - Incompatible IOB's are locked to the same bank 0Conflicting IO Standards are:IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR = OUTPUT, DRIVE_STR = 12List of locked IOB's:led10led7led8错误产生的原因是Bank0中VCCO 电压不一致，详细情况可以查看编译产生的文件（*.par）报告。
【精品博文】spartan6硬件设计笔记
【精品博文】spartan6硬件设计笔记1.用spartan6主要是想利用它的差分收发器做一些应用，那么这里就需要注意lvds引脚，任何io bank都可以用作lvds 输入，但是lvds 输出引脚只能从bank0 和bank2 中选择。
2.可选择的工作模式有：master serial ，jtag，slave serial，bpi等，都是通过引脚M0和M1的高低进行配置。
具体可以查看spartan6 ug380 23page 内容，有一些模块图和表格，一看就懂，这里就不粘贴了。
另外Jtag模式是只要一上电就存在的模式，不被M[1:0]高低影响，和其他模式共存，也能理解，要是上电后被配置成非JTAG模式，那最终的位流怎么烧写到芯片里呢，没其他途径，一般都得经过jtag口。
3.有四个引脚需要特别关注。
DONE，熟悉fpga的都知道，该引脚是位流烧写完成配置的指示引脚，当fpga configured，该引脚输出高电平，而且是OD门，最好上拉，否则输出电流很弱，不足以点亮led指示灯。
PROGRAM_B是用于异步复位的，该引脚是输入引脚。
INIT_B引脚有趣，在模式引脚M[1:0]被采集前，INIT_B是输入，可以设计RC延迟电路用于延迟配置。
4.如果被配置成masterserial SPI 模式，那么要记住从片FLASH 要先于FPGA达到稳定工作状态。
虽说像其他FPGA一样，Spartan6有POR，但为了提高可靠性，还是使用外部延迟来使得外部Flash先于FPGA稳定，UG380提到三种方式，其中一个就是利用INIT_B做延迟，先持续一段时间低电平，随后在释放，简单的RC电路即可满足。
5.电源引脚有Vccint，Vccaux，Vccio，Vref等。
Vccint是给内核供电，通常是1.2v；Vccaux是给辅助逻辑供电的，可根据具体需要设置为1.8，2.5，3.3。
但是我还是没弄清楚Vccaux 电压该怎么配置。
xilinx spartan6 lx150t dev schematic,Xilinx S6 150T开发板,评估板原理图
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This material is not designed, intended or authorized for use inFunction 1Cover Sheet649Sheet Number53Avnet Engineering Services810Spartan 6 LX150T Development Board271112Block Diagram FPGA Bank 0FPGA Power PCI Express x4 GTPs FMC, SATA, SFP GTPs DDR3Avnet Engineering ServicesTitle:Sheet 1 - Lead SheetFPGA Bank 1FPGA Bank 2FPGA Bank 3FPGA Bank 4FPGA Bank 5DDR3 TerminationFlash, RS232FMC LC Connector 110/100/1000 Ethernet PHY Ethernet Power Clock SourcesALI, Temp Sensor, RTCFMC LC Connector 2SD MMC, LEDs, Buttons, Switches 131415161718192021222324USB 2.0Board PowerMGT Power, DDR3 Term PowerSpartan 6 LX150T Development BoardREVISION DDDCCBBA AAvnet Engineering ServicesTitle:Sheet 2 - Block DiagramSpartan -6 LX150T FG676FMC LPC Slot (76 I /O , 1 GTP )R S 232 Port (2 I/O)DIP Switches (8 I /O)User LED s (8 I /O)10/100/1000 PH Y(30 I /O)USB-R S 232 Bridge(2 I/O)Communication Ports Push Switches(4 I/O)JTAG PortMiscellaneous I /O SD Card Connector(6 I /O)Memory Interfaces 128MB D D R 3 SD R A M(x16)GTP Interfaces SFP Connector (1 GTP, 7 I/O)PC I -Express x 4(1 I /O , 4 GTPs)FMC LPC Slot (73 I/O , 1 GTP )USB 2.0 PH Y (13 I /O)SATA Connector(1 GTP )ALI Serial Connector (Display, 20 I /O)32MB Flash (x16, 47 I /O)Temp SensorReal -Time Clock(3 I /O)Voltage Regulators3.3V and 5.0V Regulators 2.5V and 1.5V Regulators 1.2V Regulator 0.75V Regulator12.0V Regulator Clock Sources Programmable LVDS Clock SourceLVDS Clock Input (SMA Connectors)LVTTL OSC @ 100 MH z LVTTL OSC SocketXC F 32P and XC F 08PD DCCBBAAAvnet Engineering ServicesTitle:Sheet 3 - FPGA Bank 0FMC1-LA24_N FMC1-LA24_P FMC1-LA28_N FMC1-LA28_P FMC1-LA30_N FMC1-LA30_P FMC1-LA32_N FMC1-LA32_P FMC1-LA33_N FMC1-LA33_P FMC1-LA00-CC_P FMC1-LA00-CC_N FMC1-LA01-CC_N FMC1-LA01-CC_P FMC1-LA02_N FMC1-LA02_P FMC1-LA03_N FMC1-LA03_P FMC1-LA04_N FMC1-LA04_P FMC1-LA05_N FMC1-LA05_P FMC1-LA06_N FMC1-LA06_P FMC1-LA07_N FMC1-LA08_N FMC1-LA08_P FMC1-LA09_N FMC1-LA09_P FMC1-LA10_N FMC1-LA10_P FMC1-LA11_N FMC1-LA11_P FMC1-LA12_N FMC1-LA12_P FMC1-LA13_N FMC1-LA13_P FMC1-LA14_N FMC1-LA14_P FMC1-LA15_N FMC1-LA15_P FMC1-LA16_N FMC1-LA16_P FMC1-LA19_N FMC1-LA19_P FMC1-LA20_N FMC1-LA20_P FMC1-LA22_N FMC1-LA22_P FMC1-LA23_N FMC1-LA23_P FMC1-LA25_N FMC1-LA25_P FMC1-LA27_N FMC1-LA27_P FMC1-LA29_N FMC1-LA29_P FMC1-LA07_P FMC-LA00-CC_N FMC-LA00-CC_P FMC-LA01-CC_N FMC-LA01-CC_PFMC-LA17-CC_N FMC-LA17-CC_P FMC-LA18-CC_N FMC-LA18-CC_PFMC-LA02_N FMC-LA02_P FMC-LA03_N FMC-LA03_P FMC-LA04_N FMC-LA04_P FMC-LA05_N FMC-LA05_P FMC-LA06_N FMC-LA06_P FMC-LA07_N FMC-LA07_P FMC-LA08_N FMC-LA08_P FMC-LA09_N FMC-LA09_P FMC-LA10_N FMC-LA10_P FMC-LA11_N FMC-LA11_P FMC-LA12_N FMC-LA12_P FMC-LA13_N FMC-LA13_P FMC-LA14_N FMC-LA14_P FMC-LA15_N FMC-LA15_P FMC-LA16_N FMC-LA16_P FMC-LA19_N FMC-LA19_P FMC-LA20_N FMC-LA20_P FMC-LA21_N FMC-LA21_P FMC-LA22_N FMC-LA22_P FMC-LA23_N FMC-LA23_P FMC-LA25_N FMC-LA25_P FMC-LA26_N FMC-LA26_P FMC-LA31_P FMC-LA29_P FMC-LA31_N FMC-LA29_N FMC-LA27_P FMC-LA27_N FMC-LA24_N FMC-LA24_P FMC-LA28_N FMC-LA28_P FMC-LA30_N FMC-LA30_P FMC-LA32_N FMC-LA32_P FMC-LA33_N FMC-LA33_P FMC-CLK0-M2C_N FMC-CLK0-M2C_P FMC-CLK1-M2C_N FMC-CLK1-M2C_PFMC1_CLOCK_DATAFMC1-CLOCK_DATA_DIFF 16FMC1-LA21_P FMC1-LA21_N FMC1-LA31_P FMC1-LA31_N FMC1-LA26_P FMC1-LA26_N FMC1_VREF_A_M2C FMC1_VREF_A_M2CFMC1-CLK0-M2C_N FMC1-CLK0-M2C_P FMC1-CLK1-M2C_N FMC1-CLK1-M2C_PFMC1-CLK0-M2C_NFMC1-CLK0-M2C_P FMC1-CLK1-M2C_N FMC1-CLK1-M2C_P FMC1-LA00-CC_P FMC1-LA00-CC_NFMC1-LA01-CC_N FMC1-LA01-CC_P FMC1-LA24_N FMC1-LA24_P FMC1-LA28_N FMC1-LA28_P FMC1-LA30_N FMC1-LA30_P FMC1-LA32_N FMC1-LA32_P FMC1-LA33_NFMC1-LA33_P FMC1-LA02_N FMC1-LA02_P FMC1-LA03_N FMC1-LA03_P FMC1-LA04_N FMC1-LA04_P FMC1-LA05_N FMC1-LA05_P FMC1-LA06_N FMC1-LA06_P FMC1-LA07_N FMC1-LA08_N FMC1-LA08_P FMC1-LA09_N FMC1-LA09_P FMC1-LA10_N FMC1-LA10_P FMC1-LA11_N FMC1-LA11_P FMC1-LA12_N FMC1-LA12_P FMC1-LA13_N FMC1-LA13_P FMC1-LA14_N FMC1-LA14_P FMC1-LA15_N FMC1-LA15_P FMC1-LA16_N FMC1-LA16_P FMC1-LA19_N FMC1-LA19_P FMC1-LA20_N FMC1-LA20_P FMC1-LA22_N FMC1-LA22_P FMC1-LA23_N FMC1-LA23_P FMC1-LA25_N FMC1-LA25_P FMC1-LA27_N FMC1-LA27_P FMC1-LA29_N FMC1-LA29_P FMC1-LA07_P FMC1-LA21_P FMC1-LA21_N FMC1-LA31_P FMC1-LA31_N FMC1-LA26_P FMC1-LA26_N 12J4HEADER 2/THGNDR704K752.5VFMC1-LA17-CC_N FMC1-LA17-CC_P FMC1-LA18-CC_N FMC1-LA18-CC_P FMC1-LA17-CC_N FMC1-LA17-CC_P FMC1-LA18-CC_NFMC1-LA18-CC_P C2350.1uF 6.3VC4400.1uF 6.3VGNDGND2.5VBANK 0IO_L59P_0C21IO_L33P_0H12IO_L14p_0A3IO_L23P_0F10IO_L32N_0G11IO_L37N_GCLK12_0A14IO_L34N_GCLK18_0D13IO_L39N_0H13IO_L63P_SCP7_0B22IO_L66P_SCP1_0D21IO_L59N_0B21IO_L33N_0G13IO_L14n_0A2IO_L23N_0E10IO_L30P_0G12IO_L32P_0J11IO_L24n_0A5IO_L37P_GCLK13_0B14IO_L34P_GCLK19_0E13IO_L39P_0J13IO_L35N_GCLK16_0A13IO_L63N_SCP6_0A22IO_L66N_SCP0_0D22IO_L65P_SCP3_0B23IO_L1P_HSWAPEN_0H7IO_L38P_0K12IO_L31N_0E12IO_L30N_0F11IO_L3N_0F6IO_L15N_0E8IO_L24P_0B5IO_L36N_GCLK14_0A12IO_L56N_0F17IO_L65N_SCP2_0A23IO_L40N_0E14IO_L1N_VREF_0G7IO_L38N_VREF_0J12IO_L31P_0F12IO_L3P_0F7IO_L15P_0F9IO_L36P_GCLK15_0B12IO_L56P_0G16IO_L49N_0E16IO_L40P_0F14IO_L21P_0H10IO_L5P_0G6IO_L22n_0A4IO_L43N_0H15IO_L49P_0F16IO_L21N_0G10IO_L16P_0D5IO_L5N_0F5IO_L22P_0B4IO_L43P_0J15IO_L48P_0J16IO_L16N_0C5IO_L35P_GCLK17_0C13IO_L48N_0J17IO_L8P_0E6IO_L8N_VREF_0E5IO_L51N_0E18IO_L51P_0F18IO_L58N_0G17IO_L58P_0H17IO_L57N_0E20IO_L57P_0F20IO_L64N_SCP4_0F19IO_L64P_SCP5_0G19IO_L50N_0F15IO_L50P_0G15IO_L41N_0H14IO_L41P_0K14IO_L4N_0B3IO_L4P_0C3IO_L62N_VREF_0H19IO_L62P_0H18IO_L2N_0G8IO_L13N_0G9IO_L2P_0H8IO_L13P_0H9U11AXC6SLX150T-3FGG676D DCCBBAAAvnet Engineering ServicesTitle:Sheet 4 - FPGA Bank 1CLK_100MHZ 20CLK_SOCKET20FMC2-LA24_N FMC2-LA24_P FMC2-LA28_N FMC2-LA28_P FMC2-LA30_N FMC2-LA30_P FMC2-LA32_N FMC2-LA32_P FMC2-LA33_N FMC2-LA33_PFMC2-LA22_N FMC2-LA22_P FMC2-LA27_N FMC2-LA27_P FMC2-LA29_N FMC2-LA29_P FMC-LA00-CC_N FMC-LA00-CC_P FMC-LA01-CC_N FMC-LA01-CC_PFMC-LA17-CC_N FMC-LA17-CC_P FMC-LA18-CC_N FMC-LA18-CC_PFMC-LA02_N FMC-LA02_P FMC-LA03_N FMC-LA03_P FMC-LA04_N FMC-LA04_P FMC-LA05_N FMC-LA05_P FMC-LA06_N FMC-LA06_P FMC-LA07_N FMC-LA07_P FMC-LA08_N FMC-LA08_P FMC-LA09_N FMC-LA09_P FMC-LA10_N FMC-LA10_P FMC-LA11_N FMC-LA11_P FMC-LA12_N FMC-LA12_P FMC-LA13_N FMC-LA13_P FMC-LA14_N FMC-LA14_P FMC-LA15_N FMC-LA15_P FMC-LA16_N FMC-LA16_P FMC-LA19_N FMC-LA19_P FMC-LA20_N FMC-LA20_P FMC-LA21_N FMC-LA21_P FMC-LA22_N FMC-LA22_P FMC-LA23_N FMC-LA23_P FMC-LA25_N FMC-LA25_P FMC-LA26_N FMC-LA26_P FMC-LA31_P FMC-LA29_P FMC-LA31_N FMC-LA29_N FMC-LA27_P FMC-LA27_N FMC-LA24_N FMC-LA24_P FMC-LA28_N FMC-LA28_P FMC-LA30_N FMC-LA30_P FMC-LA32_N FMC-LA32_P FMC-LA33_N FMC-LA33_P FMC-CLK0-M2C_N FMC-CLK0-M2C_P FMC-CLK1-M2C_N FMC-CLK1-M2C_PFMC2_CLOCK_DATAFMC2-CLOCK_DATA_DIFF17, 5FMC2-LA21-P FMC2-LA21-N FMC2-LA31_P FMC2-LA31_N FMC2-LA26_P FMC2-LA26_N FMC2-LA24_NFMC2-LA24_P FMC2-LA28_N FMC2-LA28_P FMC2-LA30_N FMC2-LA30_P FMC2-LA32_N FMC2-LA32_P FMC2-LA33_N FMC2-LA33_P FMC2-LA22_N FMC2-LA22_P FMC2-LA27_N FMC2-LA27_P FMC2-LA29_N FMC2-LA29_P FMC2-LA21-PFMC2-LA21-NFMC2-LA31_P FMC2-LA31_N FMC2-LA26_P FMC2-LA26_N FLASH_OE#15FLASH_WE#15FLASH_BYTE#15FLASH_A[0..24]15FLASH_A1FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15FLASH_A16FLASH_A17FLASH_A18FLASH_A19FLASH_A20FLASH_A21FLASH_A22FLASH_A[0..24]FLASH_A23FLASH_A24FLASH_A0PCIe_PERST#10XFLASH_BUSY 5FMC2-LA20_N FMC2-LA20_NFLASH_D10FLASH_D15FLASH_D[0..15]15, 5FLASH_D[0..15]FMC2-LA18-CC_N FMC2-LA18-CC_P FMC2-LA18-CC_N FMC2-LA18-CC_P 2.5VBANK 1IO_L28P_1N17IO_L28N_VREF_1N18IO_L29P_A23_M1A13_1L23IO_L29N_A22_M1A14_1L24IO_L30P_A21_M1RESET_1N19IO_L30N_A20_M1A11_1N20IO_L31P_A19_M1CKE_1N21IO_L31N_A18_M1A12_1N22IO_L32P_A17_M1A8_1P17IO_L32N_A16_M1A9_1P19IO_L33P_A15_M1A10_1N23IO_L33N_A14_M1A4_1N24IO_L34P_A13_M1WE_1R18IO_L34N_A12_M1BA2_1R19IO_L35P_A11_M1A7_1P21IO_L35N_A10_M1A2_1P22IO_L36P_A9_M1BA0_1R20IO_L36N_A8_M1BA1_1R21IO_L37P_A7_M1A0_1P24IO_L37N_A6_M1A1_1P26IO_L38P_A5_M1CLK_1R23IO_L38N_A4_M1CLKN_1R24IO_L49P_M1DQ10_1AB24IO_L49N_M1DQ11_1AB26IO_L40P_GCLK11_M1A5_1U23IO_L40N_GCLK10_M1A6_1U24IO_L41P_GCLK9_IRDY1_M1RASN_1R25IO_L43N_GCLK4_M1DQ5_1U26IO_L43P_GCLK5_M1DQ4_1U25IO_L42N_GCLK6_TRDY1_M1LDM_1W24IO_L44P_A3_M1DQ6_1T24IO_L44N_A2_M1DQ7_1T26IO_L45P_A1_M1LDQS_1V24IO_L45N_A0_M1LDQSN_1V26IO_L46P_FCS_B_M1DQ2_1W25IO_L46N_FOE_B_M1DQ3_1W26IO_L68P_1U19IO_L68N_1U20IO_L53P_1U21IO_L53N_VREF_1U22IO_L48P_HDC_M1DQ8_1AD24IO_L48N_M1DQ9_1AD26IO_L67P_1AA23IO_L67N_1AA24IO_L66P_1T19IO_L66N_1T20IO_L74N_DOUT_BUSY_1AC24IO_L74P_AWAKE_1AC23IO_L47P_FWE_B_M1DQ0_1AA25IO_L47N_LDC_M1DQ1_1AA26IO_L42P_GCLK7_M1UDM_1V23IO_L41N_GCLK8_M1CASN_1R26IO_L39P_M1A3_1T22IO_L39N_M1ODT_1T23IO_L50N_M1UDQSN_1AC26IO_L50P_M1UDQS_1AC25IO_L51N_M1DQ13_1Y26IO_L51P_M1DQ12_1Y24IO_L52N_M1DQ15_1AE26IO_L52P_M1DQ14_1AE25IO_L69N_VREF_1V21IO_L69P_1V20U11BXC6SLX150T-3FGG676FMC2-LA25_N FMC2-LA25_P FMC2-LA25_NFMC2-LA25_PDESIGN NOTE:Differential signals connected to Bank 1 are INPUT ONLYD DCCBBAAAvnet Engineering ServicesTitle:Sheet 6 - FPGA Bank 3SCL_016, 17SDA_016, 17FMC1-PRSNT-M2C_L16FMC2-PRSNT-M2C_L 17FMC_TRST_L16, 17GMII_FP_TX_CLK 18GMII_FP_RX_CLK 18GMII_FP_GBE_MCLK 18USB_CLKOUT 12SD1_D022SD1_D122SD1_D222SD1_D322SD1_CMD 22SD1_CLK 22RS232_TXD15RS232_RXD 15USB_RS232_RXD 12USB_RS232_TXD 12GMII_FP_RXD018GMII_FP_RXD118GMII_FP_RXD218GMII_FP_RXD318GMII_FP_RXD418GMII_FP_RXD518GMII_FP_RXD618GMII_FP_RXD718GMII_FP_TXD018GMII_FP_TXD118GMII_FP_TXD218GMII_FP_TXD318GMII_FP_TXD418GMII_FP_TXD518GMII_FP_TXD618GMII_FP_TXD718GMII_FP_TX_ER 18GMII_FP_TX_EN 18GMII_FP_GTC_CLK 18GMII_FP_RX_DV 18GMII_FP_RX_ER 18GMII_FP_CRS 18GMII_FP_COL18GMII_FP_GBE_MDC 18GMII_FP_GBE_MDIO 18GMII_FP_GBE_INT#18GMII_FP_GBE_RST#18USB_DATA_[0..7]12USB_DATA_[0..7]USB_STP 12USB_NXT 12USB_DIR 12USB_RESET 12ALI_PWR21ALI_DIM21ALI_RST#21ALI_IRQ#21ALI_SPI_CLK 21ALI_SPI_MOSI 21ALI_SPI_MISO 21ALI_SPI_SEL21USB_DATA_1USB_DATA_2USB_DATA_3USB_DATA_4USB_DATA_5USB_DATA_6USB_DATA_7USB_DATA_0SCL_0SDA_0SCL_0123JP5HEADER 3123JP6HEADER 3SDA_1SCL_1SCL_1SCL_AUX21SDA_AUX213.3V3.3VR1414K75R1364K75R1404K75R1354K75SDA_1SDA_03.3VBANK 3IO_L1P_3AB5IO_L1N_VREF_3AC4IO_L02p_3AA4IO_L02n_3AA3IO_L32P_M3DQ14_3AB3IO_L32N_M3DQ15_3AB1IO_L34P_M3UDQS_3AC2IO_L34N_M3UDQSN_3AC1IO_L35P_M3DQ10_3AE2IO_L35N_M3DQ11_3AE1IO_L37P_M3DQ0_3Y3IO_L37N_M3DQ1_3Y1IO_L38P_M3DQ2_3W2IO_L38N_M3DQ3_3W1IO_L39P_M3LDQS_3V3IO_L39N_M3LDQSN_3V1IO_L41P_GCLK27_M3DQ4_3T3IO_L41N_GCLK26_M3DQ5_3T1IO_L42P_GCLK25_TRDY2_M3UDM_3V4IO_L42N_GCLK24_M3LDM_3W3IO_L43P_GCLK23_M3RASN_3R7IO_L43N_GCLK22_IRDY2_M3CASN_3R6IO_L45P_M3A3_3R8IO_L45N_M3ODT_3T8IO_L46P_M3CLK_3U5IO_L46N_M3CLKN_3T4IO_L47P_M3A0_3R10IO_L47N_M3A1_3T9IO_L49P_M3A7_3N6IO_L49N_M3A2_3P6IO_L50P_M3WE_3P5IO_L50N_M3BA2_3R5IO_L51P_M3A10_3N8IO_L51N_M3A4_3N7IO_L53P_M3CKE_3R9IO_L53N_M3A12_3P8IO_L54P_M3RESET_3N5IO_L54N_M3A11_3N4IO_L55P_M3A13_3P10IO_L55N_M3A14_3N9IO_L57P_3M10IO_L57N_VREF_3M9IO_L33P_M3DQ12_3AD3IO_L33N_M3DQ13_3AD1IO_L36P_M3DQ8_3AA2IO_L36N_M3DQ9_3AA1IO_L40P_M3DQ6_3U2IO_L40N_M3DQ7_3U1IO_L44P_GCLK21_M3A5_3R2IO_L44N_GCLK20_M3A6_3R1IO_L48P_M3BA0_3P3IO_L48N_M3BA1_3P1IO_L52P_M3A8_3R4IO_L52N_M3A9_3R3IO_L7P_3Y6IO_L7N_3Y5IO_L8P_3AB4IO_L8N_3AC3IO_L9P_3V7IO_L9N_3V6IO_L10P_3U4IO_L10N_3U3IO_L17P_3V5IO_L17N_VREF_3W5IO_L18P_3U9IO_L18N_3U8IO_L31P_3U7IO_L31N_VREF_3T6U11DXC6SLX150T-3FGG676D DC CBBA AAvnet Engineering ServicesTitle:Sheet 7 - FPGA Bank 4DDR3-DQ[0..15]13DDR3-DQ[0..15]DDR3-DQ0DDR3-DQ1DDR3-DQ2DDR3-DQ3DDR3-DQ4DDR3-DQ5DDR3-DQ6DDR3-DQ7DDR3-DQ8DDR3-DQ9DDR3-DQ10DDR3-DQ11DDR3-DQ12DDR3-DQ13DDR3-DQ14DDR3-DQ15DDR3-A[0..12]13DDR3-A[0..12]DDR3-A0DDR3-A1DDR3-A2DDR3-A3DDR3-A4DDR3-A5DDR3-A6DDR3-A7DDR3-A8DDR3-A9DDR3-A10DDR3-A11DDR3-A12DDR3-BA013DDR3-BA113DDR3-LDQS0_n13DDR3-LDQS0_p 13DDR3-UDQS0_p 13DDR3-UDQS0_n13DDR3-LDM013DDR3-UDM013DDR3-CLK0_n 13DDR3-CLK0_p 13DDR3-CAS#13DDR3-RAS#13DDR3-WE#13DDR3-ODT 13DDR3-CKE 13DDR3-RST#13DDR_REF DDR3-BA213C3120.1uF 6.3VGNDC1980.1uF 6.3VGNDDDR_REF1.5VBANK 4IO_L58P_4M4IO_L58N_VREF_4N3IO_L59P_M4DQ14_4N2IO_L59N_M4DQ15_4N1IO_L61P_M4UDQS_4L2IO_L61N_M4UDQSN_4L1IO_L62P_M4DQ10_4K3IO_L62N_M4DQ11_4K1IO_L64P_M4DQ0_4H3IO_L64N_M4DQ1_4H1IO_L65P_M4DQ2_4G2IO_L65N_M4DQ3_4G1IO_L66P_M4LDQS_4F3IO_L66N_M4LDQSN_4F1IO_L68P_M4DQ4_4D3IO_L68N_M4DQ5_4D1IO_L69P_M4UDM_4J4IO_L69N_M4LDM_4J3IO_L70P_M4RASN_4L9IO_L70N_M4CASN_4L8IO_L72P_M4A3_4M8IO_L72N_M4ODT_4M6IO_L73P_M4CLK_4K5IO_L73N_M4CLKN_4J5IO_L74P_M4A0_4L7IO_L74N_M4A1_4L6IO_L76P_M4A7_4L10IO_L76N_M4A2_4K10IO_L77P_M4WE_4G4IO_L77N_M4BA2_4G3IO_L78P_M4A10_4J9IO_L78N_M4A4_4J7IO_L80P_M4CKE_4K9IO_L80N_M4A12_4K8IO_L81P_M4RESET_4E4IO_L81N_M4A11_4E3IO_L82P_M4A13_4K7IO_L82N_M4A14_4K6IO_L83P_4H6IO_L83N_VREF_4H5IO_L60P_M4DQ12_4M3IO_L60N_M4DQ13_4M1IO_L63P_M4DQ8_4J2IO_L63N_M4DQ9_4J1IO_L67P_M4DQ6_4E2IO_L67N_M4DQ7_4E1IO_L71P_M4A5_4L4IO_L71N_M4A6_4L3IO_L75P_M4BA0_4B2IO_L75N_M4BA1_4B1IO_L79P_M4A8_4C2IO_L79N_M4A9_4C1U11EXC6SLX150T-3FGG676R2100RGNDD DCCBBA AAvnet Engineering ServicesTitle:Sheet 8 - FPGA Bank 5SFP0_TX_FAULT 11SFP0_TX_DISABLE 11SFP0_MOD211SFP0_MOD011SFP0_MOD111SFP0_LOS11SWITCH[0..7]22SWITCH[0..7]SWITCH_PB122SWITCH_PB222SWITCH_PB322SWITCH_PB422LED[0..7]22LED[0..7]SWITCH0SWITCH1SWITCH2SWITCH3SWITCH4SWITCH5SWITCH6LED0LED1LED2LED3LED4LED5LED6LED7SWITCH7RTC_INT#21RTC_RST#21RTC_32KHz 21SFP0_RSEL 113.3VBANK 5IO_L1P_A25_5H20IO_L1N_A24_VREF_5G20IO_L2P_M5A13_5B24IO_L2N_M5A14_5A25IO_L3P_M5RESET_5K18IO_L3N_M5A11_5K19IO_L4P_M5CKE_5D23IO_L4N_M5A12_5C24IO_L5P_M5A8_5H21IO_L12P_M5A3_5K21IO_L6N_M5A4_5G23IO_L14N_M5CASN_5G24IO_L7P_M5WE_5J20IO_L7N_M5BA2_5J22IO_L8N_M5A2_5E24IO_L8P_M5A7_5E23IO_L12N_M5ODT_5K22IO_L9N_M5BA1_5K20IO_L10N_M5A1_5C26IO_L14P_M5RASN_5F23IO_L11P_M5CLK_5B25IO_L11N_M5CLKN_5B26IO_L13P_M5A5_5M18IO_L9P_M5BA0_5L19IO_L26P_5M21IO_L6P_M5A10_5F22IO_L5N_M5A9_5H22IO_L10P_M5A0_5C25IO_L15P_M5UDM_5J23IO_L15N_M5LDM_5J24IO_L16P_M5DQ4_5E25IO_L16N_M5DQ5_5E26IO_L17P_M5DQ6_5D24IO_L17N_M5DQ7_5D26IO_L18P_M5LDQS_5F24IO_L18N_M5LDQSN_5F26IO_L19P_M5DQ2_5H24IO_L19N_M5DQ3_5H26IO_L20P_M5DQ0_5G25IO_L20N_M5DQ1_5G26IO_L21P_M5DQ8_5K24IO_L21N_M5DQ9_5K26IO_L22P_M5DQ10_5J25IO_L22N_M5DQ11_5J26IO_L23P_M5UDQS_5M24IO_L23N_M5UDQSN_5M26IO_L24P_M5DQ12_5L25IO_L24N_M5DQ13_5L26IO_L25P_M5DQ14_5N25IO_L25N_M5DQ15_5N26IO_L13N_M5A6_5M19IO_L26N_VREF_5M23IO_L27P_5L20IO_L27N_5L21U11FXC6SLX150T-2FGG676112233445566DDCCBBAAAvnet Engineering ServicesTitle:Sheet 14 - DDR3 TerminationSize:Rev:BDocument Number:Date:Sheetof9/7/20101424DDR_TTD D R 3T -A 0D D R 3T -A 1D D R 3T -A 2D D R 3T -A 3D D R 3T -A 4D D R 3T -A 5D D R 3T -A 6D D R 3T -A 7D D R 3T -A 8D D R 3T -A 9D D R 3T -A 10D D R 3T -A 11D D R 3T -A 12D D R 3T -R A S #D D R 3T -C A S #Example Address/Control0.75V TerminationFPGAMemoryDDR_TTR9149R9R8949R9DDR_TTC760.01uF+12C7547uF 6.3VC2970.01uF C2160.01uF C1820.01uFC2670.1uF C2410.1uF C2580.1uF C2570.1uF C130.1uFC810.1uF DDR_TTC2310.01uF +12C1047uF 6.3VC2980.01uF C2990.01uF C2870.01uF C3000.01uF C3230.01uF C3220.01uFC2080.1uF C110.1uF C1770.1uF C2090.1uFSP6DEV-LX150T-SCH-A DDR3T-A[0..12]13DDR3T-BA[0..2]13DDR3T-BA[0..2]DDR3T-BA0DDR3T-BA1DDR3T-BA2DDR3T-CAS#13DDR3T-RAS#13DDR3T-WE#13DDR3T-WE#DDR3T-RAS#DDR3T-CAS#DDR3T-CLK0_n13DDR3T-CLK0_p 13DDR3T-A[0..12]R149R9R449R9R549R9R349R918273645RP2049R918273645RP1949R918273645RP1849R918273645RP1749R9i DDR3T i DDR3T i DDR3TiDDR3T iDDR3T iDDR3T i DDR3TDLAYOUT NOTE:Install resistors at the BUS TERMINATION following DDR3 SDRAM CHIP #1LAYOUT NOTE:Install resistors at the BUS TERMINATION followingDDR3 SDRAM CHIP #1LAYOUT NOTE:Install resistors at the BUS TERMINATION following DDR3 SDRAM CHIPS112233445566DDCCBBAAAvnet Engineering ServicesTitle:Sheet 15 - Flash, RS232Size:Rev:BDocument Number:Date:Sheetof9/7/20101524FLASH_WP#594837261P3DB9FLASH_OE#4FLASH_WE#4FLASH_BYTE#4FLASH_RST#5RS232_TXD6RS232_RXD 6FLASH_D[0..15]4, 5FLASH_A0FLASH_A1FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15FLASH_A16FLASH_A17FLASH_A18FLASH_A19FLASH_A20FLASH_A21FLASH_A22C3560.1uF 6.3V C3440.1uF 6.3VC3490.1uF 6.3VC3540.1uF 6.3VC1280.1uF 6.3VC1410.1uF 6.3VC1290.1uF 6.3VC1230.1uF 6.3VFLASH_D0FLASH_D1FLASH_D2FLASH_D3FLASH_D4FLASH_D5FLASH_D6FLASH_D7FLASH_D8FLASH_D9FLASH_D10FLASH_D11FLASH_D12FLASH_D13FLASH_D14FLASH_D15FLASH_CE#512C35910uF 16VR1241K0R1211K0FLASH_A[0..24]4FLASH_A[0..24]FLASH_D[0..15]FLASH_A23FLASH_A24EN 1C1+2V+3C1-4C2+5C2-6V-7RIN 8ROUT 9INVALID 10DIN11F_ON 12DOUT13GND 14VCC 15F_OFF 16U2MAX3221EC1360.1uF 6.3V2.5V2.5V2.5V3.3V2.5V3.3V3.3Vn/c A1n/c B1n/c C1n/c D1n/c E1n/c G1n/c H1n/c A8n/cH8A0E2A1D2A2C2A3A2A4B2A5D3A6C3A7A3A8B6A9A6A10C6A11D6A12B7A13A7A14C7A15D7A16E7A17B3A18C4A19D5A20D4A21C5A22B8A23C8A24/nc F8A25/ncG8CE F2OE G2WE A5RY/BY A4WP/ACC B4BYTE F7RESETB5DQ0E3DQ1H3DQ2E4DQ3H4DQ4H5DQ5E5DQ6H6DQ7E6DQ8F3DQ9G3DQ10F4DQ11G4DQ12F5DQ13G6DQ14F6DQ15/A1G7V S S E 8V S S H 7V S SH 2V I OF 1V I O D 8V C CG 5U14S29GL256P11FFIV103.3VR1261K0R1221K0TP7TEST PADSP6DEV-LX150T-SCH-A R1161K0123JP3HEADER 3D112233445566D DCCBBAAAvnet Engineering ServicesTitle:Sheet 16 - FMC LC Connector 1Size:Rev:BDocument Number:Date:Sheetof9/7/20101624GNDGND GND12VFMC1-LA06_N FMC1-LA06_P FMC1-LA10_N FMC1-LA10_P FMC1-LA14_N FMC1-LA14_P FMC1-LA18-CC_N FMC1-LA18-CC_P FMC1-LA27_P FMC1-LA01-CC_N FMC1-LA01-CC_P FMC1-LA05_N FMC1-LA05_P FMC1-LA09_N FMC1-LA09_P FMC1-LA13_N FMC1-LA13_P FMC1-LA17-CC_N FMC1-LA17-CC_P FMC1-LA23_N FMC1-LA23_P FMC1-LA27_N FMC1-LA26_N FMC1-LA26_P FMC1-LA00-CC_P FMC1-LA00-CC_N FMC1-CLK0-M2C_N FMC1-CLK0-M2C_P FMC1-CLK1-M2C_N FMC1-CLK1-M2C_P FMC1-LA02_N FMC1-LA02_P FMC1-LA04_N FMC1-LA04_P FMC1-LA07_N FMC1-LA11_N FMC1-LA11_P FMC1-LA07_P FMC1-LA15_N FMC1-LA15_P FMC1-LA19_N FMC1-LA19_P FMC1-LA21_N FMC1-LA21_P FMC1-LA24_N FMC1-LA24_P FMC1-LA28_N FMC1-LA28_P FMC1-LA30_N FMC1-LA30_P FMC1-LA32_NFMC1-LA32_P FMC1-LA03_N FMC1-LA03_P FMC1-LA08_N FMC1-LA08_P FMC1-LA12_N FMC1-LA12_P FMC1-LA16_N FMC1-LA16_P FMC1-LA20_N FMC1-LA20_P FMC1-LA22_N FMC1-LA22_P FMC1-LA25_N FMC1-LA25_P FMC1-LA29_N FMC1-LA29_P FMC1-LA31_N FMC1-LA31_P FMC1-LA33_NFMC1-LA33_P SDA_0SCL_0FMC1-PRSNT-M2C_L 12P 0V C 3512P 0VC 373P 3V C 39SCL C30SDAC31GA0C343P 3V A U XD 323P 3V D 363P 3V D 383P 3VD 40PG_C2M D1T C K D 29T D I D 30T D O D 31T M S D 33T R S T _LD 34GA1D35VADJ G39VREF_A_M2CH1PRSNT_M2C_L H2VADJ H40JX1EFMC_CC_LPC_10FMC1-CLK0-M2C_N FMC1-CLK0-M2C_P FMC1-CLK1-M2C_N FMC1-CLK1-M2C_PFMC1-LA24_N FMC1-LA24_P FMC1-LA28_N FMC1-LA28_P FMC1-LA30_N FMC1-LA30_P FMC1-LA32_N FMC1-LA32_P FMC1-LA33_N FMC1-LA33_P FMC1-LA00-CC_P FMC1-LA00-CC_N FMC1-LA01-CC_N FMC1-LA01-CC_P FMC1-LA17-CC_N FMC1-LA17-CC_P FMC1-LA18-CC_N FMC1-LA18-CC_P FMC1-LA02_N FMC1-LA02_P FMC1-LA03_N FMC1-LA03_P FMC1-LA04_N FMC1-LA04_P FMC1-LA05_N FMC1-LA05_P FMC1-LA06_N FMC1-LA06_P FMC1-LA07_N FMC1-LA08_N FMC1-LA08_P FMC1-LA09_N FMC1-LA09_P FMC1-LA10_N FMC1-LA10_P FMC1-LA11_N FMC1-LA11_P FMC1-LA12_N FMC1-LA12_P FMC1-LA13_N FMC1-LA13_P FMC1-LA14_N FMC1-LA14_P FMC1-LA15_N FMC1-LA15_P FMC1-LA16_N FMC1-LA16_P FMC1-LA19_N FMC1-LA19_P FMC1-LA20_N FMC1-LA20_P FMC1-LA22_N FMC1-LA22_P FMC1-LA23_N FMC1-LA23_P FMC1-LA25_N FMC1-LA25_P FMC1-LA27_N FMC1-LA27_P FMC1-LA29_N FMC1-LA29_P FMC1-LA07_P FMC-LA00-CC_N FMC-LA00-CC_P FMC-LA01-CC_N FMC-LA01-CC_PFMC-LA17-CC_N FMC-LA17-CC_P FMC-LA18-CC_N FMC-LA18-CC_PFMC-LA02_N FMC-LA02_P FMC-LA03_N FMC-LA03_P FMC-LA04_N FMC-LA04_P FMC-LA05_N FMC-LA05_P FMC-LA06_N FMC-LA06_P FMC-LA07_N FMC-LA07_P FMC-LA08_N FMC-LA08_P FMC-LA09_N FMC-LA09_P FMC-LA10_N FMC-LA10_P FMC-LA11_N FMC-LA11_P FMC-LA12_N FMC-LA12_P FMC-LA13_N FMC-LA13_P FMC-LA14_N FMC-LA14_P FMC-LA15_N FMC-LA15_P FMC-LA16_N FMC-LA16_P FMC-LA19_N FMC-LA19_P FMC-LA20_N FMC-LA20_P FMC-LA21_N FMC-LA21_P FMC-LA22_N FMC-LA22_P FMC-LA23_N FMC-LA23_P FMC-LA25_N FMC-LA25_P FMC-LA26_N FMC-LA26_P FMC-LA31_P FMC-LA29_P FMC-LA31_N FMC-LA29_N FMC-LA27_P FMC-LA27_N FMC-LA24_N FMC-LA24_P FMC-LA28_N FMC-LA28_P FMC-LA30_N FMC-LA30_P FMC-LA32_N FMC-LA32_P FMC-LA33_N FMC-LA33_P FMC-CLK0-M2C_N FMC-CLK0-M2C_P FMC-CLK1-M2C_N FMC-CLK1-M2C_PFMC1_CLOCK_DATAFMC1-CLOCK_DATA_DIFF3FMC1-LA21_P FMC1-LA21_N FMC1-LA31_P FMC1-LA31_N FMC1-LA26_P FMC1-LA26_N SCL_017, 6SDA_017, 6FMC1-PRSNT-M2C_L 6FMC1-GBTCLK0-M2C_p FMC1-GBTCLK0-M2C_nFMC1-GBTCLK0-M2C_p11FMC1-GBTCLK0-M2C_n 11FMC1-DP0-C2M_p FMC1-DP0-C2M_n FMC1-DP0-M2C_p FMC1-DP0-M2C_nFMC1-DP0-C2M_p 11FMC1-DP0-C2M_n 11FMC1-DP0-M2C_p 11FMC1-DP0-M2C_n11FMC1_VREF_A_M2CR1664K75FMC_TRST_L17, 6FPGA_TDO 9FMC1_TD09+12C9047uF 6.3VC3840.01uF C3700.01uF C3870.01uF C3650.01uF C3640.01uFGND12VGNDJTAG_TCK 17, 5, 9JTAG_TMS 17, 5, 9HCLK0_M2C_p H4CLK0_M2C_nH5LA02_p H7LA02_n H8LA04_p H10LA04_n H11LA07_p H13LA07_n H14LA11_p H16LA11_n H17LA15_p H19LA15_n H20LA19_p H22LA19_n H23LA21_p H25LA21_n H26LA24_p H28LA24_n H29LA28_p H31LA28_n H32LA30_p H34LA30_n H35LA32_p H37LA32_nH38JX1DFMC_CC_LPC_10GND C1GND C4GND C5GND C8GND C9GND C12GND C13GND C16GND C17GND C20GND C21GND C24GND C25GND C28GND C29GND C32GND C33GND C36GND C38GND C40GND D2GND D3GND D6GND D7GND D10GND D13GND D16GND D19GND D22GND D25GNDD28GNDD37GND D39GND G1GND G4GND G5GND G8GND G11GND G14GND G17GND G20GND G23GND G26GND G29GND G32GND G35GND G38GND G40GND H6GND H3GND H9GND H12GND H15GND H18GND H21GND H24GND H27GND H30GND H33GND H36GND H39JX1FFMC_CC_LPC_10CDP0_C2M_p C2DP0_C2M_n C3DP0_M2C_p C6DP0_M2C_nC7LA06_p C10LA06_n C11LA10_p C14LA10_n C15LA14_p C18LA14_n C19LA18_p_CC C22LA18_n_CCC23LA27_p C26LA27_n C27JX1AFMC_CC_LPC_10DGBTCLK0_M2C_p D4GBTCLK0_M2C_nD5LA01_p_CC D8LA01_n_CCD9LA05_p D11LA05_n D12LA09_p D14LA09_n D15LA13_p D17LA13_n D18LA17_p_CC D20LA17_n_CCD21LA23_p D23LA23_n D24LA26_p D26LA26_nD27JX1BFMC_CC_LPC_10GCLK1_M2C_p G2CLK1_M2C_n G3LA00_p_CC G6LA00_n_CCG7LA03_p G9LA03_n G10LA08_p G12LA08_n G13LA12_p G15LA12_n G16LA16_p G18LA16_n G19LA20_p G21LA20_n G22LA22_p G24LA22_n G25LA25_p G27LA25_n G28LA29_p G30LA29_n G31LA31_p G33LA31_n G34LA33_p G36LA33_nG37JX1CFMC_CC_LPC_10C3710.01uf 50V+C91100uF 20VR1391K0R1371K0SP6DEV-LX150T-SCH-A FMC_3.3VFMC_3.3VR1674K75FMC1_VIOFMC1_VIO+12C2147uF 6.3VC410.01uF C440.01uF C490.01uF C510.01uF C600.01uFGND FMC1_VIOD112233445566D DCCBBAAAvnet Engineering ServicesTitle:Sheet 17 - FMC LC Connector 2Size:Rev:BDocument Number:Date:Sheetof9/7/20101724GNDGND GND12V FMC2-LA06_N FMC2-LA06_P FMC2-LA10_N FMC2-LA10_P FMC2-LA14_N FMC2-LA14_P FMC2-LA18-CC_N FMC2-LA18-CC_P FMC2-LA27_P FMC2-LA01-CC_N FMC2-LA01-CC_P FMC2-LA05_N FMC2-LA05_P FMC2-LA09_N FMC2-LA09_P FMC2-LA13_N FMC2-LA13_P FMC2-LA17-CC_N FMC2-LA17-CC_P FMC2-LA23-N FMC2-LA23-P FMC2-LA27_N FMC2-LA26_NFMC2-LA26_P FMC2-LA00-CC_P FMC2-LA00-CC_N FMC2-CLK0-M2C_N FMC2-CLK0-M2C_P FMC2-CLK1-M2C_N FMC2-CLK1-M2C_P FMC2-LA02_N FMC2-LA02_P FMC2-LA04_N FMC2-LA04_P FMC2-LA07_N FMC2-LA11_N FMC2-LA11_P FMC2-LA07_P FMC2-LA15_N FMC2-LA15_P FMC2-LA19-N FMC2-LA19-P FMC2-LA21-N FMC2-LA21-P FMC2-LA24_N FMC2-LA24_P FMC2-LA28_N FMC2-LA28_P FMC2-LA30_N FMC2-LA30_P FMC2-LA32_NFMC2-LA32_P FMC2-LA03_N FMC2-LA03_P FMC2-LA08_N FMC2-LA08_P FMC2-LA12_N FMC2-LA12_P FMC2-LA16_N FMC2-LA16_P FMC2-LA20-N FMC2-LA20-P FMC2-LA22_N FMC2-LA22_P FMC2-LA25_N FMC2-LA25_P FMC2-LA29_N FMC2-LA29_P FMC2-LA31_N FMC2-LA31_P FMC2-LA33_NFMC2-LA33_P SDA_0SCL_0FMC2-PRSNT-M2C_L 12P 0V C 3512P 0VC 373P 3V C 39SCL C30SDAC31GA0C343P 3V A U XD 323P 3V D 363P 3V D 383P 3VD 40PG_C2M D1T C K D 29T D I D 30T D O D 31T M S D 33T R S T _LD 34GA1D35VADJ G39VREF_A_M2CH1PRSNT_M2C_LH2VADJ H40JX2EFMC_CC_LPC_10FMC2-CLK0-M2C_N FMC2-CLK0-M2C_P FMC2-CLK1-M2C_N FMC2-CLK1-M2C_PFMC2-LA24_N FMC2-LA24_P FMC2-LA28_N FMC2-LA28_P FMC2-LA30_N FMC2-LA30_P FMC2-LA32_N FMC2-LA32_P FMC2-LA33_N FMC2-LA33_P FMC2-LA00-CC_P FMC2-LA00-CC_N FMC2-LA01-CC_N FMC2-LA01-CC_P FMC2-LA17-CC_N FMC2-LA17-CC_P FMC2-LA18-CC_N FMC2-LA18-CC_P FMC2-LA02_N FMC2-LA02_P FMC2-LA03_N FMC2-LA03_P FMC2-LA04_N FMC2-LA04_P FMC2-LA05_N FMC2-LA05_P FMC2-LA06_N FMC2-LA06_P FMC2-LA07_N FMC2-LA08_N FMC2-LA08_P FMC2-LA09_N FMC2-LA09_P FMC2-LA10_N FMC2-LA10_P FMC2-LA11_N FMC2-LA11_P FMC2-LA12_N FMC2-LA12_P FMC2-LA13_N FMC2-LA13_P FMC2-LA14_N FMC2-LA14_P FMC2-LA15_N FMC2-LA15_P FMC2-LA16_N FMC2-LA16_P FMC2-LA19-N FMC2-LA19-P FMC2-LA20-N FMC2-LA20-P FMC2-LA22_N FMC2-LA22_P FMC2-LA23-N FMC2-LA23-P FMC2-LA25_N FMC2-LA25_P FMC2-LA27_N FMC2-LA27_P FMC2-LA29_N FMC2-LA29_P FMC2-LA07_P FMC-LA00-CC_N FMC-LA00-CC_P FMC-LA01-CC_N FMC-LA01-CC_PFMC-LA17-CC_N FMC-LA17-CC_P FMC-LA18-CC_N FMC-LA18-CC_PFMC-LA02_N FMC-LA02_P FMC-LA03_N FMC-LA03_P FMC-LA04_N FMC-LA04_P FMC-LA05_N FMC-LA05_P FMC-LA06_N FMC-LA06_P FMC-LA07_N FMC-LA07_P FMC-LA08_N FMC-LA08_P FMC-LA09_N FMC-LA09_P FMC-LA10_N FMC-LA10_P FMC-LA11_N FMC-LA11_P FMC-LA12_N FMC-LA12_P FMC-LA13_N FMC-LA13_P FMC-LA14_N FMC-LA14_P FMC-LA15_N FMC-LA15_P FMC-LA16_N FMC-LA16_P FMC-LA19_N FMC-LA19_P FMC-LA20_N FMC-LA20_P FMC-LA21_N FMC-LA21_P FMC-LA22_N FMC-LA22_P FMC-LA23_N FMC-LA23_P FMC-LA25_N FMC-LA25_P FMC-LA26_N FMC-LA26_P FMC-LA31_P FMC-LA29_P FMC-LA31_N FMC-LA29_N FMC-LA27_P FMC-LA27_N FMC-LA24_N FMC-LA24_P FMC-LA28_N FMC-LA28_P FMC-LA30_N FMC-LA30_P FMC-LA32_N FMC-LA32_P FMC-LA33_N FMC-LA33_P FMC-CLK0-M2C_N FMC-CLK0-M2C_P FMC-CLK1-M2C_N FMC-CLK1-M2C_PFMC2_CLOCK_DATAFMC2-CLOCK_DATA_DIFF4, 5FMC2-LA21-P FMC2-LA21-N FMC2-LA31_P FMC2-LA31_N FMC2-LA26_P FMC2-LA26_N SCL_016, 6SDA_016, 6FMC2-PRSNT-M2C_L 6FMC2-GBTCLK0-M2C_p FMC2-GBTCLK0-M2C_nFMC2-GBTCLK0-M2C_p11FMC2-GBTCLK0-M2C_n 11FMC2-DP0-C2M_p FMC2-DP0-C2M_n FMC2-DP0-M2C_p FMC2-DP0-M2C_nFMC2-DP0-M2C_p 11FMC2-DP0-M2C_n11FMC2-DP0-C2M_p 11FMC2-DP0-C2M_n11R2014K75FMC_TRST_L16, 6FMC2_TDI 9FMC2_TDO 9+12C9347uF 6.3VC4500.01uF C4450.01uF C4530.01uF C4550.01uF C4510.01uFGNDJTAG_TCK 16, 5, 9JTAG_TMS 16, 5, 9CDP0_C2M_p C2DP0_C2M_n C3DP0_M2C_p C6DP0_M2C_nC7LA06_p C10LA06_n C11LA10_p C14LA10_n C15LA14_p C18LA14_n C19LA18_p_CC C22LA18_n_CCC23LA27_p C26LA27_n C27JX2AFMC_CC_LPC_10DGBTCLK0_M2C_p D4GBTCLK0_M2C_n D5LA01_p_CC D8LA01_n_CCD9LA05_p D11LA05_n D12LA09_p D14LA09_n D15LA13_p D17LA13_n D18LA17_p_CC D20LA17_n_CCD21LA23_p D23LA23_n D24LA26_p D26LA26_nD27JX2BFMC_CC_LPC_10HCLK0_M2C_p H4CLK0_M2C_nH5LA02_p H7LA02_n H8LA04_p H10LA04_n H11LA07_p H13LA07_n H14LA11_p H16LA11_n H17LA15_p H19LA15_n H20LA19_p H22LA19_n H23LA21_p H25LA21_n H26LA24_p H28LA24_n H29LA28_p H31LA28_n H32LA30_p H34LA30_n H35LA32_p H37LA32_nH38JX2DFMC_CC_LPC_10GCLK1_M2C_p G2CLK1_M2C_n G3LA00_p_CC G6LA00_n_CCG7LA03_p G9LA03_n G10LA08_p G12LA08_n G13LA12_p G15LA12_n G16LA16_p G18LA16_n G19LA20_p G21LA20_n G22LA22_p G24LA22_n G25LA25_p G27LA25_n G28LA29_p G30LA29_n G31LA31_p G33LA31_n G34LA33_p G36LA33_nG37JX2CFMC_CC_LPC_10GND C1GND C4GND C5GND C8GND C9GND C12GND C13GND C16GND C17GND C20GND C21GND C24GND C25GND C28GND C29GND C32GND C33GND C36GND C38GND C40GND D2GND D3GND D6GND D7GND D10GND D13GND D16GND D19GND D22GND D25GNDD28GNDD37GND D39GND G1GND G4GND G5GND G8GND G11GND G14GND G17GND G20GND G23GND G26GND G29GND G32GND G35GND G38GND G40GND H6GND H3GND H9GND H12GND H15GND H18GND H21GND H24GND H27GND H30GND H33GND H36GND H39JX2FFMC_CC_LPC_1012VGNDC4520.01uf 50V+C95100uF 20VR1801K0R1791K0SP6DEV-LX150T-SCH-A 3.3VFMC_3.3VFMC_3.3V2.5V2.5VR2024K75DDESIGN NOTE:Differential signal pairs FMC2_LA19,FMC2_LA21, FMC2_LA20, and FMC2_LA23are implemented as single ended signals and are not not routed differential.。