数字逻辑电路实验--基于有限状态机的密码锁

数电实验三报告姓名：xxx班级：xxx 学号：xxxx实验：基于有限状态机的密码锁一、实验目的学习如何通过Verilog HDL 编程，利用Basys3板上的开关控制七段数码管实现四位密码锁。

二、实验要求使用有限状态机设计一个 4 位密码锁。

利用 Basys3 板上的滑动开关 sw[0]到sw[9]分别代表 0‐9 十个数字，依次输入 4 位不重复的密码。

如果密码输入顺序与设计设置的一致，则显示大写字母P，否则显示大写字母F。

注意，即使密码输入错误，也必须在输入完整的 4 位密码输入，才能显示大写字母 F。

三、实验设计及内容1.基础版实验代码module doorlock(input CLK,input clr,input [9:0] sw,output reg [10:0] display_out);reg[3:0] present_state,next_state;parameter S0=4'b0000,S1=4'b0001,S2=4'b0010,S3=4'b0011,S4=4'b0100,E1=4'b0101,E2=4'b0110,E3=4'b0111,E4=4'b1000;reg [29:0] count;reg [9:0] keys=0;always @(posedge CLK or posedge clr)beginif (clr) count<=0;else count<=count+1;endassign clk_3=count[24];// ~3Hzalways @(posedge clk_3 or posedge clr) // STATE TRANSITIONbeginif (keys!=sw) keys <= sw;if (clr) present_state <= S0;else present_state <= next_state;end// Demo for Finite State Machine// the correct password is 0->1->2->3 (Switch sw[0]->sw[1]->sw[2]->sw[3] in order. always @(*)begincase (present_state)S0: beginif (~|keys[9:0]) next_state <=S0; // no key pressedelse if (keys[2]) next_state <=S1; // first valid key pressedelse next_state <=E1; // first invalid key pressedendS1: beginif (~|keys[9:3]&&~|keys[1:0]) next_state <=S1; // no key pressedelse if (keys[1]) next_state <=S2;// second valid key pressedelse next_state <=E2;// second invalid key pressedendS2: beginif (~|keys[9:3]&&~|keys[0]) next_state <=S2; // no key pressedelse if (keys[7]) next_state <=S3; // third valid key pressedelse next_state <=E3;// third invalid key pressedendS3: beginif (~|keys[9:8]&&~|keys[6:3]&&~|keys[0]) next_state <=S3; // no key pressedelse if (keys[3]) next_state <=S4;// fourth vaild key pressedelse next_state <=E4;// fourth invalid key pressedendS4: beginif (~|keys[9:8]&&~|keys[6:4]&&~|keys[0]) next_state <=S4; // no keypressedelse next_state <=E1; // fifth key pressed, but ignored *** endE1:beginif (keys!=sw) next_state <=E2; // second invalid key pressedelse next_state <=E1; // no key pressedendE2:beginif (keys!=sw) next_state <=E3; // third invalid key pressedelse next_state <=E2; // no key pressedendE3:beginif (keys!=sw) next_state <=E4; // fourth invalid key pressedelse next_state <=E3; // no key pressedendE4: next_state <=E4; // the additional keys are ALL ignored ***default: next_state <=S0;endcaseendalways @(*) // indicate the number of inputs and display the tag begincase(present_state)S4: display_out<=11'b0111_0011000;// P in left-most segmentE4: display_out<=11'b1110_0111000;// F in right-most segmentS0: display_out<=11'b1001_0011100;// oo in the middle segmentsS1,E1: display_out<=11'b1001_0111111;// confirm first inputS2,E2: display_out<=11'b1001_0011111;// confirm second inputS3,E3: display_out<=11'b1001_0011110;// confirm third inputdefault:display_out<=11'b1111_1111111; // no displayendcaseendendmodule2.进阶版实验代码module doorlock2(input CLK,input clr,input [9:0] sw,output reg [10:0] display_out);reg[3:0] present_state,next_state;reg [19:0]count1=0;reg [2:0] sel=0;parameter S0= 4'b0000,S1=4'b0001,S2=4'b0010,S3=4'b0011,S4=4'b0100, S01=4'b1001,S02=4'b1010,S03=4'b1011,E1=4'b0101,E2=4'b0110,E3=4'b0111,E4=4'b1000;parameter T1MS=50000,T2MS=20000_0000;reg [29:0] count;reg [32:0] count2=0;reg [9:0] keys=0;reg flag;always @(posedge CLK or posedge clr)beginif (clr)begincount<=0;endelse count<=count+1;endwire clk_3;assign clk_3=count[24];// ~3Hzalways @(posedge clk_3 or posedge clr) // STATE TRANSITIONbeginif (keys!=sw) keys <= sw;if (clr) present_state <= S0;else present_state <= next_state;endalways@(posedge CLK or posedge clr)beginif(present_state == S4)beginif(count2<T2MS)begincount2<=count2+1;flag<=1'b0;endelsebeginflag<=1'b1;endendif(clr) count2<=0;end// Demo for Finite State Machine// the correct password is 0->1->2->3 (Switch sw[0]->sw[1]->sw[2]->sw[3] in order. always @(*)begincase (present_state)S0: beginif (~|keys[9:0]) next_state <=S0; // no key pressedelse if (keys[2]) next_state <=S1; // first valid key pressedelse next_state <=E1; // first invalid key pressedendS1: beginif (~|keys[9:3]&&~|keys[1:0]) next_state <=S1; // no key pressed//else if (!sw) next_state <=S01;// second valid key pressedelse if(keys[1]&&keys[2]) next_state<=S2;else next_state <=E2;// second invalid key pressedendS01:beginif(!sw) next_state<=S01;else if(sw[2]) next_state<=S2;else next_state<=E2;endS2: beginif (~|keys[9:3]&&~|keys[0]) next_state <=S2; // no key pressed//else if (!sw) next_state <=S02; // third valid key pressedelse if (keys[2]&&keys[1]&&keys[3]) next_state <=S3;else next_state<=E3;// third invalid key pressedendS02: beginif(!sw) next_state<=S02;else if(sw[1]) next_state<=S3;else next_state<=E3;endS3: beginif (keys[1]&&keys[2]&&keys[3]) next_state <=S3; // no key pressed else if (!sw[3]) next_state <=S03;// fourth vaild key pressedelse next_state <=E4;// fourth invalid key pressedendS03:beginif(~|keys[9:3]&&~|keys[0]) next_state<=S03;else if(keys[3]) next_state<=S4;else next_state<=E4;endS4: beginif (~|keys[9:4]&&~|keys[0]) next_state <=S4; // no key pressedelse next_state <=E1; // fifth key pressed, but ignored *** endE1:beginif (keys!=sw) next_state <=E2; // second invalid key pressedelse next_state <=E1; // no key pressedendE2:beginif (keys!=sw) next_state <=E3; // third invalid key pressedelse next_state <=E2; // no key pressedendE3:beginif (keys!=sw) next_state <=E4; // fourth invalid key pressedelse next_state <=E3; // no key pressedendE4: next_state <=E4; // the additional keys are ALL ignored ***default: next_state <=S0;endcaseendalways@(posedge CLK)begincount1<=count1+1;if(count1==T1MS)begincount1<=0;sel<=sel+1;if(sel==4)sel<=0;endendalways @(posedge CLK) // indicate the number of inputs and display the tagbegincase(present_state)S0: begincase(sel)0:display_out<=11'b0111_0101000;1:display_out<=11'b1011_0110000;2:display_out<=11'b1101_1000100;3:display_out<=11'b1110_0110110;default:display_out<=11'b1111_1111111;endcaseendS1: begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1110111;2:display_out<=11'b1101_1110111;3:display_out<=11'b1110_1110111;default:display_out<=11'b1111_1111111;endcaseend // confirm first inputS2: begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1001111;2:display_out<=11'b1101_1110111;3:display_out<=11'b1110_1110111;default:display_out<=11'b1111_1111111;endcaseend // confirm second inputS3: begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1001111;2:display_out<=11'b1101_0000110;3:display_out<=11'b1110_1110111;default:display_out<=11'b1111_1111111;endcaseend // confirm third inputS4: beginif(!flag)begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1001111;2:display_out<=11'b1101_0000110;3:display_out<=11'b1110_0000110;default:display_out<=11'b1111_1111111;endcaseendelse display_out<= 11'b0111_0011000 ;end // P in left-most segmentS01:begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1110111;2:display_out<=11'b1101_1110111;3:display_out<=11'b1110_1110111;default:display_out<=11'b1111_1111111;endcaseendS02:begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1001111;2:display_out<=11'b1101_1110111;3:display_out<=11'b1110_1110111; default:display_out<=11'b1111_1111111;endcaseendS03: begincase(sel)0:display_out<=11'b0111_0010010;1:display_out<=11'b1011_1001111;2:display_out<=11'b1101_0000110;3:display_out<=11'b1110_1110111;default:display_out<=11'b1111_1111111;endcaseendE1: display_out<=11'b0111_0111000;E2: display_out<=11'b1011_0111000;E3: display_out<=11'b1101_0111000;E4: display_out<=11'b1110_0111000;// F in right-most segment default:display_out<=11'b1111_1111111; // no displayendcaseendendmodule约束文件代码：## Clock signalset_property PACKAGE_PIN W5 [get_ports CLK]set_property IOSTANDARD LVCMOS33 [get_ports CLK]## Switchesset_property PACKAGE_PIN V17 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]set_property PACKAGE_PIN V16 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]set_property PACKAGE_PIN W16 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]set_property PACKAGE_PIN W17 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]set_property PACKAGE_PIN W15 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]set_property PACKAGE_PIN V15 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]set_property PACKAGE_PIN W14 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]set_property PACKAGE_PIN W13 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]set_property PACKAGE_PIN V2 [get_ports {sw[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]set_property PACKAGE_PIN T3 [get_ports {sw[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]## sw[15]set_property PACKAGE_PIN R2 [get_ports {clr}]set_property IOSTANDARD LVCMOS33 [get_ports {clr}]## 7-seg displayset_property PACKAGE_PIN W4 [get_ports {display_out[10]}]set_property PACKAGE_PIN V4 [get_ports {display_out[9]}]set_property PACKAGE_PIN U4 [get_ports {display_out[8]}]set_property PACKAGE_PIN U2 [get_ports {display_out[7]}]set_property PACKAGE_PIN W7 [get_ports {display_out[6]}]set_property PACKAGE_PIN W6 [get_ports {display_out[5]}]set_property PACKAGE_PIN U8 [get_ports {display_out[4]}]set_property PACKAGE_PIN V8 [get_ports {display_out[3]}]set_property PACKAGE_PIN U5 [get_ports {display_out[2]}]set_property PACKAGE_PIN V5 [get_ports {display_out[1]}]set_property PACKAGE_PIN U7 [get_ports {display_out[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[9]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[8]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[7]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[6]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[5]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[4]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[3]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[2]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {display_out[10]}]四、实验结果1基础结果图2.进阶结果图进阶实验成品效果说明：进阶视频演示：正确示范：密码输入错误示范：五、实验总结1.通过本次实验了解了时钟信号的作用原理以及对时序电路的控制机理。