飞思卡尔32位嵌入式CPU核心M310简介

Integration Guide - provides data required to integrate a VC into an SoC design. Test Guide - provides VC design-for-test data. Verification Guide - provides VC functional verification data. One Pager - provides VC brief technical summary oif features and implementation details.
» These instructions can execute in (N+1) clock cycles, where N represents the number of registers to transfer » Load/store quadrant is a special case operating on R4 - R7
» » » » Instruction fetch Instruction decode/register file read Execute Register writeback 32-bit arithmetic/logic unit (ALU) 32-bit barrel shifter Find-first-one unit (FFO) Result feed-forward hardware Support hardware for multiplication and multiple register loads and stores
2 Dec 01
M310S One Pager (3 of 4)
Features and Modes

32-bit load/store RISC architecture with fixed 16-bit instruction length 16-entry 32-bit general-purpose register file Efficient 4-stage execution pipeline, hidden from application software Single-cycle execution for many instructions. Two cycles for branches Branch-folding mode for eliminating short backward loops in the instruction stream Support for byte/halfword/word memory accesses Optimized interfacing to 16-bit memory systems and burst memory devices Fast interrupt support (vectored & autovectored) with 16-entry dedicated alternate register file 32 x 16 hardware multiplier Debug support via JTAG-based OnCE™ Design Dedicated test wrapper with safe-state capability that supports AC testing
2 Dec 01
Document Usage

Core Guide - describes a VC processor core and provides programming information.
» Referred to for features, signals and operation
» These instructions can execute in two clock cycles

Load (ldm) and store (stm) multiple register instructions allow low overhead context save and restore operations
2 Dec 01
Microarchitecture Summary (1 of 3) “M310S_CoreGuide”

4 Stage Pipeline operating in an overlapped fashion, allowing single clock execution for most instructions:
2 Dec 01
M310S One Pager (2 of 4)
Overview

The M•CORE™ M310S processor (M310S) is a fully synthesizable version of the semi-custom M310 processor. It has been designed for high-performance and cost-sensitive embedded control applications, with particular emphasis on reduced system power consumption, making it suitable for a number of battery-operated, portable products. M310S extends the original M•CORE M200 Family instruction I set and functionality by integrating an integer array multiplier, improved pipelining of load and store operations, and a deeper instruction buffer to improve memory bandwidth utilization.
» Branch target addresses calculated in parallel with branch instruction decode
• There is a single pipeline bubble for taken branches and jumps • Results in an execution time of two clocks
» Conditional branches (that are not taken) execute in a single clock
2 Dec 01 11 May 00
Microarchitecture Summary (2 of 3) “M310S_CoreGuide”

There are memory load and store operations for byte, halfword, and word (32-bit) data, with automatic zero extension of byte and halfword load data
2 Dec 01
Data Calculation
M310S One Pager (1 of 4)
GCR/GSR MUX
Address Generation
General-Purpose Register File 32 bits X 16
Alternate Register File 32 bits X 16
2 Dec 01
M310S One Pager (4 of 4)
Implementation

Bus Type : Modified MLB (all signals rising edge driven) Verilog HDL : Yes Synthesized RTL available : Yes GDSII available : Upon customer request Test Strategy : Full Scan with LBIST Scan Type : Mux D Scan-Flop Test Coverage : 97% DC ATPG Tool : Fastscan >80% of flops gated by Power Compiler Process synthesized : HiP7LP1 Standard Cell Library : SoCDT HiP7LP1 (WCS, 1.35V, 105C) Drawn Size : 3580 x 1400 µm Actual Size : 1074 x 420 µ-m (0.45 mm2) Transistor Count: 313,787 Maximum Frequency at the above PVT : 90MHz Power Dissipation : 0.416mW/MHz Functional AC Coverage : Critical Path .s File
2 Dec 01
Current IP Variances from SRS 3.0

The IP being Supplied is not fully compliant with SRS 3.0 SRS Standards Have evolved over last 2-3 Years Legacy IP Reused and not updated Due to Schedule/Resource Limitations, Some Cases M310S is Closer to SRS 3.0 than the M210S. Modules on the MMC2114 are Close to SRS 2.0 Highly Suggested to Consider Conversion to SRS 3.0 Before rolling out too Many Derivatives.
MUX
MUX
Instruction Buffer Adder/Logical Priority Encoder/ Zero Detect Result MUX Output Data Bus Input Data Bus
Instruction Pipeline
Instruction Decode
M•CORE M310S - Fully Synthesizable RISC CPU
Control Register File 32 bits X 16
Address MUX Address Bus
X Port Multiplier
Y Port
Immediate MUX Scale PC Increment/ Branch Folding
Branch Adder
MUX Barrel Shifter Sign Ext. Divider
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Execution unit consists of:
» » » » »

Program Counter (PC) has a dedicated incrementer and a dedicated branch address adder to minimize delays during change of flow
M•CORE Integration Training Course

Overview M•CORE Interface M•CORE Local Bus (MLB) Clock, Reset Bus Arbitration OnCE Debug Support Design For Test M•CORE M210S Reference Platform Testbench Example Summary, Q&A