锁相环英文文献翻译

锁相技术译文翻译

英文原名：High Speed Digital Hybrid PLL Frequency Synthesizer

译文：高速数字混合锁相环频率合成器

年纪专业：08级通信工程班

姓名：学号：

2011年 5月2日

To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design.

In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the high switching speed [2].

However, there is a problem that the speed of the whole system is limited by PLL.

Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage converter (FVC) [3].

It has a fast switching speed by the PD (phase detector), FVC using output signal of VCO and the proposed coarse tuning controller.

However, H/W complexity is increased for the high switching speed.

Also, it shows the fast switching characteristic only when the FVC works well.

Another method is pre-tuning one which is called DH-PLL in this study [4].

It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of

VCO(voltage controlled oscillator).

For this reason, this paper proposes a timing synchronization circuit for the rapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption. Also, the requisite condition is solved in the proposed method. The fast switching operation at every the frequency synthesis process is verified by the computer circuit simulation.

II.DH-PLL synthesizer

As shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO 要得到高运行速度,事先做好复杂设计的精确同步是必要的。

2001年,H.G.Ryu提出了一种简化结构的直接数字频率合成器(DDFS)驱动的高转换速度锁相环【2】。

但是,有一个问题,整个系统的速度是受锁相环限制的。

Y.Fouzar提出了一种使用频率—电压转换器(FVC)具有双重回路结构的锁相环频率合成器【3】。

因为鉴相器(PD)， FVC利用了压控振荡器的输出信号和我们提出的粗调控制器，所以它具有快速切换速度。

但是,因为有高速系统转换速度使得H / W的复杂性增加了。

另外，结果表明只有FVC工作状态良好时系统才有较高切换速度。

另一种方法是做预先调整也就是本项研究中的DH-PLL 【4】。

它具有高速切换的特性，但是因为数字查找表(DLT)的原因，H / W复杂度和功耗明显增大了，因为DLT 经常被ROM执行，DLT中包含压控振荡器(VCO)的传输特性。

介于以上原因, 为得到较高切换速度和低功耗，本文提出了一种新的快速定时同步频率合成电路，用一个非常简单的DLT替代数字逻辑块，而不用复杂的ROM型(DLT)。

同时,在该方法中所需必要条件也解决了，频率合成过程的高切换速度在计算机电路仿真中已经得到验证了。

2.DH-PLL合成器

图1中所示的开环频率合成技术是一种直接频率合成方式，在频率控

desired VCO frequency.

③is fixed until a new FCW is made.

Fig. 4. Operating signal of DH-PLL. 关系是固定的。

图4 DH-PLL工作信号