利用Trace32如何dump出调试信息

0 n
0 z
1 c
0 v
0 i
1 F
0 t
10011 svc
N : negative
Z : zero
ARM mode, IRQ mode, FIQ mode, supervisor (svc) mode
Exception & Interrupt
• • • • • • Reset Undefined instruction Abort (prefetch) Abort (data) IRQ FIQ svc und abt abt irq fiq
CPU inside
Registers ( r0 ~ r15, cpsr, spsr ) Control Unit Internal CPU Bus
ALU (Arithmetic Logic Unit)
ARM CPU < cpu mode >
Mode -----------------------------• Abort • Fast interrupt request • Interrupt request • Supervisor • System • Undefined • User for short abt fiq irq svc sys und usr
Exception Reset Data Abort FIQ IRQ Prefetch Abort SWI Undefined Instruction Exception when PC value lr – 8 lr – 4 lr – 4 lr – 4 lr lr
•
Function Call Stack
•
1. 2. 3.
Analysis Examples
Abort Exception Fatal Error Reset
Enter Upload Mode
• CPU violation (Exception) System can not run correctly • Reset (Unwanted case) • Hardware reset • Software reset (assert or watchdog reset) • Fatal error case
Dump File Debug Using TRACE32
Index
•
1. 2.
T32 Simulator for Dump File Debug
Enter Upload mode Get Dump File
•
1. 2. 3. 4. 5. 6.
Basic Concepts
Arm CPU Arch REX TCB Structure Task Switch Signal Transfer Software Arch ELF & SCL file Upload Mode
ARM CPU < register >
• 37 registers
User and System
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Fast Interrupt Request R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq Interrupt requeset R13_irq R14_irq Suervisor R13_svc R14_svc Undefined R13_undef R14_undef Abort R13_abt R14_abt
REX TCB Structure < Context frame >
Program Status Register Undefined Values ( four words)
Top of Stack (Stored in TCB) These adjustments are required to match the context frame with the interrupt frame
• Log History show the path of problem • Analysis the issue which is hard to reproduce • Global Var provide the system modules status and some hints for the issue
r4-r11
Undefined Values (two words) Return Address
Application Stack Frame
TASK Switching Signal Transfer
• Intertask communication mechanism
– high priority TASK is Active when low priority TASK is running – Sleep TASK : The TASK is ready( rex_wait ) When Sleep Task it will release the CPU – rex_set_sigs() and rex_wait() call rex_sched() to do the TASK switch
Dump File Components
• • • • • ROM ( Code ) + RAM Dump CPU Register Global Var Log history ( key_debug_buffer ) Code Area damage check
Why Dump File Debug is needed?
Function Call Stack cont’
• ui_free_nv() call ui_wait_nv() result judge handle stack review
REX TCB Structure < definition of rex_tcb_type >
typedef struct rex_tcb_struct { void *sp; /* Stack pointer */ void *stack_limit; /* Stack Limit */ unsigned long slices; /* Task slices */ rex_sigs_type sigs; /* Current signals */ rex_sigs_type wait; /* Wait signals */ rex_priority_type pri; /* Task's priority */ struct { struct rex_tcb_struct *next_ptr; struct rex_tcb_struct *prev_ptr; } link; } rex_tcb_type;
TASK Switching CPU Occupy
Dog Task TASK TASKpriority priority: : Dog Dog> > A A> >B B> >C C > >Sleep Sleep A Task B Task C Task
rex_set_sig to A Task dog_wakeup_timer Timer Interrupt happen
Link register Offset
• LR(Link register) BL(Branch Link) ASM record the address to it before execute and for next instruction excution – Return to Address+1 memory address value Exception current happened pc value decided by the CPU mode – exception handler return to current excution
Sleep Task
< ASM source > CODE32 __main _main
B B B B B B B B
ENTRY Reset_Handler Undefined_Handler SWI_Handler Prefetch_Handler Abort_Handler Reserved_Handler RAM_IRQ_VECTOR RAM_FIQ_VECTOR
Vector Table
; ADDRESS EXCEPTION MODE ON ENTRY ;-------------------------------------------------; 0x00000000 Reset Supervisor ;-------------------------------------------------; 0x00000004 Undefined instruction Undefined ;-------------------------------------------------; 0x00000008 Software Interrupt Supervisor ;-------------------------------------------------; 0x0000000C Abort (prefetch) Abort ;-------------------------------------------------; 0x00000010 Abort (data) Abort ;-------------------------------------------------; 0x00000014 Reserved Reserved ;-------------------------------------------------; 0x00000018 IRQ IRQ ;-------------------------------------------------; 0x0000001C FIQ FIQ ;--------------------------------------------------
Exception Priory
Exception Reset Data Abort Fast Interrupt Request Priory 1 2 3 I (irq mask) 1 1 1 1 1 1 1 F(fiq mask) 1 1 -
Interrupt Request 4 Prefetch Abort Software Interrupt Undefined Instruction 5 6 6
Function Call Stack cont’
Function Call Stack cont’
• •
ui_rex_wait() call rex_wait() from the stack review push {r3-r7, r14} at beginning r14(lr) , r3, r4, r5, r6, r7 (6 value dword) in stack consequence fiq R14_fiq
CPSR SPSR_fiq SPSR_irq SPSR_svc SPSR_undef SPSR_abt
Program Status Register
• • • Flags CPU Mode Set IRQ,FIQ switch
Flag 31 30 29 28 Reserved 7 6 Control 5 4 0
• R13(SP) : Stack top of current Frame • Stack bottom : Record Task TCB structure • Beginning or push and ending for pop of registers operation • R14(LR): push the pc and pop it after finishing BL