POC实验(VHDL)

Experiment Report

◆NAME: Jiang WuXi(姜武希）

◆NUMBER: 04008246

◆COURSE: COA Course Design

◆PROJECT: POC Design

◆DATE:MAR.102011

Purpose:

The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s MaxplusⅡEDA tool is recommended and provided for simulation. Please refer to William,Stallings. “Computer Organization and Architecture, Designing for Performance”, P.65~75; P.185~190.

Task:

POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices).

Figure 1 Printer Connection

Figure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in Figure 2.

Figure 2 The handshake-timing diagram between POC and the printer

The handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).

In order to ease your design work, the further explanations of the POC operations and some design hints are given as follows:

The buffer register BR is used to hold a character that has been sent via the system bus while that the character is being transferred to the printer. The status register SR

is used for two control functions: SR7serves as a ready flag for system bus transfers

to BR (like the printer RDY signal for transfers from POC to the printer), and SR0 is used to enable or disable interrupt requests from POC. If SR0=1, then POC will interrupt when it is ready to receive a character (i.e., when SR7=1). If SR0=0, then POC will not interrupt. The other bits of SR are not used and empty.

The transfer of a character to POC via the system bus proceeds as follows. POC indicates that it is ready by setting SR7.The processor reads SR (by executing a polling or interrupt service routine) and, finding SR7=1, writes a character to BR. The POC clears SR7 when it loads this character into BR to indicate that another character should not be sent for the moment. POC then proceeds to transfer the character in BR to the printer by generating a pulse at TR. The processor, in the meantime, continues to fetch and execute instructions .If it should happen to read SR, it will find SR7=0 and hence will not attempt to send another character to the printer. When the printer is ready to receive another character, POC sets SR7.The transfer cycle can now repeat.