eetop[1].cn_ISOCC04_tutorial_ckim

17
AISL
Delay Line Vernier
Can use two delay lines with switches to use part of one and remainder of the other with fractionally larger delays (1 + 1/N)
5
AISL
DLL Locking Process
6
AISL
Frequency Response
Open loop response
7
AISL
Frequency Response(cnt’d)
Closed loop response
where loop bandwidth is
8
AISL
Delay Cell
Capacitor-loaded inverter delay line
11
AISL
Single-Ended Delay Cell(cnt’d)
Inverters with regulated supply voltage
[S. Sidiropoulos, SOVC00]
12
AISL
Differential Delay Cell
Dead-Zone in PFD
“Dead-zone” occurs when the loop doesn’t respond to small phase errors - e.g. 10 ps phase error at PFD inputs:
-
Solution: delay reset to guarantee min. pulse width (typically > 100 ps)
-
Match currents IUP and IDN Reduce control voltage coupling Supply noise rejection, PVT insensitivity (Simple or bandgap biased)
22
AISL
Charge Pump: Better Switches
2
AISL
DLL vs PLL
PLL
DLL
+ VCDL
-
VCO jitter accumulation higher order system can be unstable slow locking time hard to integrate LF hard to design
no jitter accumulation
Single-ended delay cell
-
Simple Dynamic power only (no static current) Complex biasing Static power consumption Immune to supply noise and thus smaller jitter Current Capacitance Resistance Voltage swing Phase interpolation Vernier delay line
16
AISL
Phase Interpolation
Can interpolate between two edges through a weighted sum
-
Control over delay is guaranteed to be monotonic, but not necessarily linear Resolution can be arbitrarily high Precision is limited by linearity
30
AISL
Harmonic Lock Problem
Correct and false locking
Correct locking
False locking
31
AISL
DLL Locking Using Inversion
External clock
Initial internal clock Inversion of External clock Initial internal clock Internal clock after locking
AISL
I CH = x • (2 • I D )
Locking Range
Locking range
0.5 × TCLK < TVCDL min < TCLK TCLK < TVCDL max < 1.5 × TCLK
Max(TVCDL min , 2 / 3 × TVCDL max ) < TCLK < Min(2 × TVCDL min , TVCDL max )
Closed loop - jitter accumulation
Open loop - No jitter accumulation
4
AISL
Basic DLL Architectures
Delay-locked Loop (Delay line based first order PLL)
Phase-Locked Loop (VCO based second order)
- ref. signal dependent - no freq. multiplication - limited locking range
3
AISL
Jitter Accumulation Comparison
PLL-based clock generator DLL-based clock generator
9
Differential delay cell
Leabharlann Baidu
Variables for delay control
Fine delay generation
AISL
Single-Ended Delay Cell
Current-starved inverter delay line
10
AISL
Single-Ended Delay Cell(cnt’d)
14
AISL
Differential Delay Cell(cnt’d)
Replica-biased differential delay line circuitry
-
The low end of the signal swing can be set by controlling the bias current with a replica bias circuit
13
AISL
Differential Delay Cell(cnt’d)
Voltage-controlled two-element PFET “Resistor”
-
Adjustable load : Iload=Bp(Vc-Vtp)2 Resistive load : S-shaped, nearly resistive
Delayed Locked Loop Design Issues
Chulwoo Kim ckim@korea.ac.kr Advanced Integrated Systems Lab Korea University
Outline
Introduction DLL operation and control theory DLL building blocks DLL design issues Multiplying DLL
Differential delay element with resistive loads
-
High power supply rejection ratio Requirements Adjustable loads to control the delay and resistive loads to reject power supply noise
27
AISL
Bandwidth
Bandwidth
-
A wider loop bandwidth Fast acquisition time but degraded jitter performance [A. Chandrakasan, IEEE Press, 2001]
-
ICH, KDL, and C are process technology dependent. According to the design target, the loop bandwidth varies.
28
AISL
Adaptive Bandwidth
Self-biased DLL
FREF Phase Comp U D Charge Pump C1 VCTRL Bias Gen VBP VBN VCDL DO(S)
[J. Maneatis,JSSC 96]
DI(S)
Fo
Current and gain of VCDL
Unity-gain buffer controls the voltage over switches Current mirrored into Iup/Idn
23
AISL
Charge Pump: Zero-Offset
Up and down nodes track with each other thanks to the selfbias scheme.
+ 1st order system
always stable
+ fast locking time + easy to integrate LF + easier to design
+ less ref. signal dependent + freq. multiplication + no limited locking range
24
AISL
Charge Pump : Reversed Switches
25
AISL
2nd Order Charge-Pump Scheme : Mismatch Cancellation
[K. Kim, ISSCC 04]
26
AISL
Design Issues
Bandwidth Limited lock range Lock in time Static phase offset Power dissipation limits Area limits Peak output jitter
ID =
k • (VCTRL − VT ) 2 2
K DL
CB = 4 ID
ωN 1 1 = I CH K DL FREF ω REF ω REF C1
= = =
29
Current of Charge pump
1 1 I CH K DL FREF 2π C1 1 1 CB x (2 I D ) 2π 4 I D C1 1 CB 4π C 1
15
AISL
Differential Delay Cell(cnt’d)
Replica-biased delay line
(a) Delay adjustment range for replicabiased delay element
(b) Static supply sensitivity for replicabiased delay element
Remove dead zone
dead zone
21
AISL
Charge Pump
Converts PFD digital UP/DN signals into charge Charge is proportional to duration of UP/DN signals Qcp = IUP*tUP – IDN*tDN The LPF converts integrates currents Charge pump requirements:
-
may be analog or digital may linearly cover a wide range, or just a narrow phase difference “Dead zone” may occur
19
AISL
Phase-Frequency Detector
20
AISL
-
Delay resolution is a buffer delay / N Relative precision is limited by control over tx / ty
18
AISL
Phase Detector
Output describes phase difference between two inputs