移位寄存器产生序列号
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五、实验过程记录(数据、图表、计算等)
六、实验结果分析及问题讨论
VHDL 语言：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity step2 is
port(
r,cp:in std_logic;
d:in std_logic_vector(3 downto 0);
m:in std_logic_vector(1 downto 0);
f1,f2:out std_logic
);
end step2;
architecture beh of step2 is
signal zj,zj1:std_logic;
signal q:std_logic_vector(3 downto 0);
signal sr:std_logic_vector(2 downto 0); signal sc:std_logic_vector(7 downto 0);
begin
process(r,cp,m)
begin
if r='0' then
q<="0000";
else
if cp'event and cp='1' then
zj<= not q(2);
if m= "01"then q(0)<=q(1);
q(1)<=q(2);
q(2)<=q(3);
q(3)<=zj;
elsif m="10" then q(3)<=q(2);
q(2)<=q(1);
q(1)<=q(0);
q(0)<=zj;
elsif m= "11" then q<=d;
end if;
end if;
if m="00" then
q<=q;
end if;
end if;
sr(2)<=q(0);
sr(1)<=q(1);
sr(0)<=q(2);
case sr is
when "000"=>sc<="11111110";
when "001"=>sc<="11111101";
when "010"=>sc<="11111011";
when "011"=>sc<="11110111";
when "100"=>sc<="11101111";
when "101"=>sc<="11011111";
when "110"=>sc<="10111111";
when "111"=>sc<="01111111";
when others=>sc<="11111111";
end case;
f1<=sc(3) and sc(6);
f2<=sc(0)and sc(3)and sc(4);
end process;
end beh;