静态时序分析总结

Static Timing Analyzer Using

PrimeTime

Dec 23 2007

Presented by zhao

icdesign_zhao@

Agenda

)Basic Flow

Advanced Analysis Summary

Example

STA instruction

Static timing analysis concept

¾Verifies timing (setup, hold …)

¾Is exhaustive

¾Uses formal, mathematical techniques instead of vectors

¾Does not use dynamic logic simulation

STA : Easier, faster debugging of your design timing

Comprehensive Timing Checks

Many types of timing and design rule checks ¾Timing checks can be delay calculated or SDF annotated ¾Setup and hold check

¾Design rule checks consistent with DC, PC, Astro

Basic Timing Analysis Flow Using PrimeTime Setup Design Environment

¾Search path, link path

¾Read designs, libraries, then link

¾Read sdf and set operation condition, environment setting

Specify Timing Assertions

¾Clock period/waveform/uncertainty/latency

¾Input/output delays

Specify Timing Exceptions

¾Multi-cycle paths and False paths

¾Min/max delays, segmentation, disabled arcs

Perform Analysis, Create Reports

¾Check timing

¾Timing reports and constraint reports

¾Bottleneck and coverage analysis reports

Set Up Environment

Definitions

search_path:specifies where to search for design and library data

link_path:specifies which design and library data to be loaded

during linking (link_design)

link_design:command resolves all design references

Example:

pt_shell > set search_path “. ./syn/lib”

pt_shell > set link_path “* stdcell.db. IO.db memory.db”

pt_shell > read_verilog $project_dir/top.v

pt_shell > current_design top

pt_shell > link_design

pt_shell > read_sdf -type sdf_max $sdf_dir/top.sdf

Design tip

1. The setup is different with DC setup

2. Before new design was load, removed old design and constraint

3. report_annotated_delay: Report backannotated delays

4. report_annotated_check: Report backannotated timing checks

Operating condition and design environment Setting the operating conditions, wire-load models, input/output environment

Example

pt_shell > set_operating_conditions -library pt_lib \

-analysis_type on_chip_variation worst

pt_shell > set_wire_load_mode enclose (pre gate)

pt_shell > set_wire_load_model std_100k_w (pre gate)

pt_shell > remove_wire_load_model (post gate)

pt_shell > set_driving_cell -lib_cell OR2 [all_inputs] (core level)

pt_shell > set_driving_cell -lib_cell IO/PAD (chip level)

pt_shell > set_load -load_of [expr std/nd2/A*8] (core level)

pt_shell > set_load -load_of [expr IO_CELL1/A*8] (chip level) Design tip

1. Wire load model is different in pre-gate and post-gate

2. Load and drive are different between core level and chip level

3. report_design: report operation conditions