计算机设计与实践——32位先行进位加法器

测试代码：
module test; reg [32:1] x32; reg [32:1] y32; reg ciii; wire c2; wire [32:1] f3ቤተ መጻሕፍቲ ባይዱ; alu_32 uut ( .c2(c2), .f32(f32), .x32(x32), .y32(y32), .ciii(ciii) );
alu_16 alu_16_1(g[1],p[1],f32[16:1],x32[16:1],y32[16:1],ciii); alu_16 alu_16_2(g[2],p[2],f32[32:17],x32[32:17],y32[32:17],c1);
assign c1=g[1]|p[1]&ciii; assign c2=g[2]|p[2]&g[1]|p[2]&p[1]&ciii; endmodule
module alu_16(gmm,pmm,f16,x16,y16,cii);//16位加法器先行进位加法器 input [16:1]x16; input [16:1]y16; input cii; output [16:1]f16; output gmm,pmm; wire [4:1]c; wire [4:1]p; wire [4:1]g; jiafaqi_4 alu_4_1(g[1],p[1],f16[4:1],x16[4:1],y16[4:1],cii); jiafaqi_4 alu_4_2(g[2],p[2],f16[8:5],x16[8:5],y16[8:5],c[1]); jiafaqi_4 alu_4_3(g[3],p[3],f16[12:9],x16[12:9],y16[12:9],c[2]); jiafaqi_4 alu_4_4(g[4],p[4],f16[16:13],x16[16:13],y16[16:13],c[3]); cla_4 cl_4_1(c,p,g,cii); assign pmm=p[4]&p[3]&p[2]&p[1]; assign gmm=g[4]|p[4]&g[3]|p[4]&p[3]&g[2]|p[4]&p[3]&p[2]&g[1]; endmodule
32位先行进位加法器
——Verilog HDL语言
32位超前进位加法器的进位是并 行同时产生的，能够极大的减 少加法器由进位引起的延时。 增加了逻辑器件，但有效的减 少的延迟。进位是由cla部件超 前算出，本位是由不含进位的 加法器算出。
Verilog HDL代码如下： module alu_32(c2,f32,x32,y32,ciii);//32位加法器先行进位加法器 input [32:1]x32; input [32:1]y32; input ciii; output [32:1]f32; output c2; wire c1; wire [2:1]p; wire [2:1]g;
module jiafaqi_4(gm,pm,f,x,y,c0); //四位超前进位加法器 input [4:1]x; //四位x值 input [4:1]y; //四位y值 output [4:1]f; //四位加和f output gm,pm; input c0; //上一的级进位 wire [3:1]c; //超前进位 wire [4:1]p; wire [4:1]g; assign p=x|y; assign g=x&y; assign c[1]=g[1]|p[1]&c0; assign c[2]=g[2]|p[2]&g[1]|p[2]&p[1]&c0; assign c[3]=g[3]|p[3]&g[2]|p[2]&p[3]&g[1]|p[3]&p[2]&p[1]&c0; assign c4=g[4]|p[4]&g[3]|p[4]&p[3]&g[2]|p[4]&p[3]&p[2]&g[1]|p[4]&p[3]&p[2]&p[1]&c0; assign pm=p[4]&p[3]&p[2]&p[1]; assign gm=g[4]|p[4]&g[3]|p[4]&p[3]&g[2]|p[4]&p[3]&p[2]&g[1]; jiafaqi_1 jia1(x[1],y[1],c0,f[1]); jiafaqi_1 jia2(x[2],y[2],c[1],f[2]); jiafaqi_1 jia3(x[3],y[3],c[2],f[3]); jiafaqi_1 jia4(x[4],y[4],c[3],f[4]); endmodule
initial begin x32 = 0; y32 = 0; ciii = 0; #100; x32 = 32'haaaaaaaa; y32 = 32'h55555555; ciii = 0; #100; x32 = 32'haaaaaaaa; y32 = 32'h55555555; ciii = 1; #100; x32 = 32'h00000011; y32 = 32'h00000011; ciii = 0; #100; x32 = 32'h10000000; y32 = 32'h10000000; ciii = 1; end endmodule
module jiafaqi_1(x,y,c0,f); //一位加法器模块 input x; input y; input c0; output f; assign f=(x^y)^c0; endmodule module cla_4(c,p,g,c0);//4位CLA部件 input [4:1]p; input [4:1]g; input c0; output [4:1]c; assign c[1]=g[1]|p[1]&c0; assign c[2]=g[2]|p[2]&g[1]|p[2]&p[1]&c0; assign c[3]=g[3]|p[3]&g[2]|p[2]&p[3]&g[1]|p[3]&p[2]&p[1]&c0; assign c[4]=g[4]|p[4]&g[3]|p[4]&p[3]&g[2]|p[4]&p[3]&p[2]&g[1]|p[4]&p[3]&p[2]&p[1]& c0; endmodule