3位二进制优先编码器和译码器的Verilog HDL语言设计

一、3位二进制优先编码器

Module coder8_3(i,f);

Input [7:0]i;

Output [2:0]f;

Assign f=code(i);

Function [2:0] code

Input [7:0]i;

If(!i[7]) code=3’b111;

Else if(!i[6]) code=3’b110;

Else if(!i[5]) code=3’b101;

Else if(!i[4]) code=3’b100;

Else if(!i[3]) code=3’b011;

Else if(!i[2]) code=3’b010;

Else if(!i[1]) code=3’b001;

Else if(!i[0]) code=3’b000;

Endfunction

Endmodule

二、3位二进制译码器

Module decod3_8(a,f);

Input [2:0]a;

Output [7:0]f;

Always @(a)

Begin

Case(a)

3’b000:f=8’b00000001;

3’b001:f=8’b00000010;

3’b010:f=8’b00000100;

3’b011:f=8’b00001000;

3’b100:f=8’b00010000;

3’b101:f=8’b00100000;

3’b110:f=8’b01000000;

3’b111:f=8’b10000000;

Endcase

End

endmodule