基于FPGA的六十进制计数器
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实验名称：六十进制计数器
6．出现的问题及解决方法
无
附件A
实验步骤或程序：
十进制计数器程序：
library ieee;
use ieee.std_logic_1164.all;
entity count10 is
port(ep,et,clk,nld,nrd: in std_logic;
d: in std_logic_vector(3 downto 0);
q:buffer std_logic_vector(3 downto 0);
c:buffer std_logic );
end count10;
architecture rtl of count10 is
begin
process(ep,et,clk,nld,nrd,d)
begin
if ep='1' and et='1' then
if nrd='0' then
q<="0000";
c<='0';
else if clk'event and clk='1' then
if nld='0' then
q<=d;
else
case q is
when"0000"=>q<="0001";c<='0';
when"0001"=>q<="0010";c<='0';
when"0010"=>q<="0011";c<='0';
when"0011"=>q<="0100";c<='0';
when"0100"=>q<="0101";c<='0';
when"0101"=>q<="0110";c<='0';
when"0110"=>q<="0111";c<='0';
when"0111"=>q<="1000";c<='0';
when"1000"=>q<="1001";c<='1';
when others=>q<="0000"; c<='0';
end case;
end if;
else q<=q;
c<=c;
end if;
end if;
else q<=q;
c<=c;
end process;
end rtl;
管脚设置：
六十进制计数器：
library ieee;
use ieee.std_logic_1164.all;
entity count60 is
port(CLK:in std_logic;
Q1,Q0:buffer std_logic_vector(3 downto 0);
C:buffer std_logic);
end count60;
architecture rtl of count60 is
signal S1,S2,S3,S4:std_logic;
component count10
port(EP,ET,CLK,nLd,nRd:in std_logic;
C:buffer std_logic;
D:in std_logic_vector(3 downto 0);
Q:buffer std_logic_vector(3 downto 0));
end component;
begin
A1:count10 port map('1','1',CLK,S1,'1',S3,"0000",Q0,); A0:count10 port map(S4,S4,CLK,S1,'1',S2,"0000",Q1,); S1<=not(Q1(2) and Q1(0) and Q0(0) and Q0(3));
C<=not S1;
S4<=S3 OR C;
end rtl;
管脚设置：