P10_Post-ADC Digital Filtering in the CIS with the Column Single Slope ADC
TLV2543CN;TLV2543CDBR;TLV2543CDW;TLV2543IDB;TLV2543IDW;中文规格书,Datasheet资料
Terminal Functions
TERMINAL NAME AIN0 – AIN10 NO. 1 – 9, 11, 12 15 I/O I DESCRIPTION Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a capacitance of 60 pF. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. Serial data output. This is the 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. Reference +. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF – terminal. Reference –. The lower reference voltage value (nominally ground) is applied to REF –. Positive supply voltage.
IP113 芯片资料
forwarding for low latency – Supports pure converter mode data
forwarding for extreme low latency – Supports flow control for full and half duplex
4/48
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02 May. 19, 2003
IP113M
7. PIN Description
Type I O
IPL IPH
Copyright © 2003, IC Plus Corp.
1/48
All rights reserved.
preliminary, Specification subject to change without notice.
IP113M-DS-R02 May. 19, 2003
3. Block Diagram
All rights reserved.
Preliminary, Specification subject to change without notice.
6. PIN Diagram
IP113M
LED_FX_FDX/ ADDR2
LED_FX_SD/ SPEED_MODE
SCL / ADDR0
25
LED_RMT_TP_SPD/ AUTO_SEND
AD9653 AD9253 AD9633 模数转换器用户指南说明书
One Technology Way · P.O. Box 9106 · Norwood, MA 02062-9106 · Tel: 781.329.4700 · Fax: 781.461.3113 · EVALUATING THE AD9653/AD9253/AD9633 ANALOG-TO-DIGITAL CONVERTERSPrefaceThis user guide describes the AD9653, AD9253 and AD9633 evaluation boards, AD9653-125EBZ,AD9253-125EBZ and AD9633-125EBZ, which provide all of the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.The AD9653AD9253 and AD9633 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at/hsadcevalboard. For additional information or questions, send an email to*******************************.Typical Measurement SetupFigure 1. Evaluation Board Connection—AD9653-125EBZ, AD9253-125EBZ or AD9633-125EBZ (on Left)and HSC-ADC-EVALCZ (on Right)FeaturesFull featured evaluation board for the AD9653/AD9253/AD9633qSPI interface for setup and controlqExternal, on-board oscillator, or AD9517 clocking optionqBalun/transformer or amplifier input drive optionqOn-board LDO regulator needing a single external 6 V, 2 A dc supplyqVisualAnalog® and SPI controller software interfacesqHelpful DocumentsAD9653, AD9253 or AD9633 data sheetqHigh speed ADC FIFO evaluation kit (HSC-ADC-EVALCZ)qAN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User ManualqAN-878 Application Note, High Speed ADC SPI Control SoftwareqAN-877 Application Note, Interfacing to High Speed ADCs via SPIqAN-835 Application Note, Understanding ADC Testing and EvaluationqDesign and Integration FilesSchematics, layout files, bill of materialsqEquipment NeededAnalog signal source and antialiasing filterqSample clock source (if not using the on-board oscillator)q2 switching power supplies (6.0 V, 2.5 A), CUI EPS060250UH-PHP-SZ providedqPC running Windows®qUSB 2.0 portqAD9653-125EBZ, AD9253-125EBZ or AD9633-125EBZ boardqHSC-ADC-EVALCZ FPGA-based data capture kitqGetting StartedThis section provides quick start procedures for using the AD9653-125EBZ, AD9253-125EBZ or AD9633-125EBZ board. Both the default and optional settings are described.Configuring the BoardBefore using the software for testing, configure the evaluation board as follows:1.Connect the evaluation board to the data capture board, as shown in Figure 1.2.Connect one 6 V, 2.5 A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to the AD9653-125EBZ, AD9253-125EBZ or AD9633-125EBZ.3.Connect one 6 V, 2.5 A switching power supply (such as the supplied CUI EPS060250UH-PHP-SZ) to the HSC-ADC-EVALCZ board.Connect the HSC-ADC-EVALCZ board (J6) to the PC using a USB cable.4.5.On the ADC evaluation board, confirm that the jumpers are installed as shown in Figure 2 and Table 1.On the ADC evaluation board, use a clean signal generator with low phase noise to provide an6.input signal to the desired A and/or B channel(s). Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band, band-pass filter with 50 Ωterminations and an appropriate center frequency. (Analog Devices, Inc., uses TTE, Allen Avionics, and K&L band-pass filters.)Evaluation Board HardwareThe evaluation board provides the support circuitry required to operate the AD9653, AD9253 andAD9633 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.See the Getting Started section to get started, and visit UG-328 Design Support for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.Power SuppliesThis evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E101, E102, E103 and E104 ferrite beads to disconnect the outputs from theon-board LDOs. This enables the user to bias each section of the board individually. Use P102 andP103 to connect a different supply for each section. A 1.8 V, 0.5 A supply is needed for 1.8V_AVDD and 1.8V_DRVDD. Although the power supply requirements are the same for AVDD and DRVDD, it is recommended that separate supplies be used for both analog and digital domains. The SPI and its level shifters and alternate clock options require a separate 3.3 V, 0.5 A analog supply.Two additional supplies, 5V_AVDD and 3V_AVDD, are used to bias the optional input path amplifiers and optional AD9517-3 clock chip. If used, these supplies should each have 0.5 A current capability. Input SignalsWhen connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or HP 8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ωterminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Analog Devices evaluation boards typically can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.Output SignalsThe default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The serial LVDS outputs from the ADC are routed to ConnectorP1002 using 100 Ω differential traces. For more information on the data capture board and its optional settings, visit /hsadcevalboard.Jumper SettingsSet the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.Table 1. Jumper SettingsJumperDescriptionJ202This jumper selects between internal V REF and external V REF .To choose the internal 1 V reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND).To use the on-board ADR130 1 V reference, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF).To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE)to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9653 canaccommodate reference voltages from 1.0 V to 1.3 V; the AD9253 and AD9633 referencevoltage is specified to be 1.0 V.J204Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to be STBY (standby).J302This jumper sets the ADC for SPI communications with the HSC-ADC-EVALCZ .Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, and Pin 8 to Pin 9 for CSB.J803This jumper enables the on-board crystal oscillator.Figure 2. Default Jumper Connections for AD9653-125EBZ /AD9253-125EBZ /AD9633-125EBZ Board Evaluation Board CircuitryThis section explains the default and optional settings or modes allowed on the AD9653-125EBZ ,AD9253-125EBZ and the AD9633-125EBZ boards.PowerPlug the switching power supply into a wall outlet rated at 100 V ac to 240 V ac, 47 Hz to 63 Hz. Connect the DC output connector to P101 on the evaluation board.Analog InputThe four channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50 Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz.VREFThe default VREF configuration is to connect the SENSE pin to AGND for internal VREF operation. This is done by connecting Pin 3 to Pin 5 on Header J202. An external reference voltage can be provided to the AD9653, AD9253 and AD9633. Connecting Pin 2 to Pin 1 on Header J202 puts the ADC in a mode where it requires a reference voltage from an external source. The external on-board 1.0 V reference is provided by the ADR130. This external reference can be connected to the ADC by connecting Pin 4 to Pin 6 on Header J202. Alternatively, if an external off-board reference is desired, connect Pin 2 to Pin1 on Header J202 and apply the reference voltage directly to Pin 4 of Header J202. The AD9653 can accommodate reference voltages from 1.0 V to 1.3 V; the AD9253 and AD9633 reference voltage is specified to be 1.0 V.RBIASRBIAS has a default setting of 10 kΩ (R205) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10 kΩ, 1% resistor for RBIAS may degrade the performance of the device.ClockThe default clock input circuit is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T801/T802) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped byCR801 before entering the ADC clock inputs. The AD9653, AD9253 and AD9633 ADCs are equipped with an internal 8:1 clock divider to facilitate usage with higher frequency clocks. When using the internal divider and a higher input clock frequency, remove CR801 to preserve the slew rate of the clock signal.The AD9653-125EBZ, AD9253-125EBZ and AD9633-125EBZ boards are set up to be clocked through the transformer-coupled input network from the crystal oscillator, Y801. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3-BHL-125MHz). If a different clock source is desired, remove C810 (optional) and Jumper J803 to disable the oscillator from running and connect the external clock source to the SMA connector, J802 (labeled CLK+).PDWNTo enable the power-down feature, add a shorting jumper across J204 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD.Modes of OperationStandalone (PIN) ModeThe AD9653/AD9253/AD9633 ADCs can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB pin is tied to AVDD, and the SDIO/OLM pin controls the output lane mode. Table 2 and Table 3 specify the settings for pin mode operation.Table 2. Output Lane Mode (OLM) Pin SettingsOLM Pin Voltage Output ModeAVDD (Default)Two-lane. 1× frame, 16-bit serial outputGND One-lane. 1× frame, 16-bit serial outputTable 3. Digital Test Pattern (DTP) Pin SettingsSeected DTP Output Mode Resulting D0±x and D1±xNormal Operation10 kΩ to AGND Normal operationDTP AVDD1000 0000 0000 0000Additional information on the lane modes is provided in the AD9653, AD9253 and AD9633 data sheets.Default ModeTo operate the device under test (DUT) using the SPI, follow the jumper settings for J302 as shown in Table 1.How To Use The Software For TestingSetting up the ADC Data CaptureAfter configuring the board, set up the ADC data capture using the following steps:1.Open VisualAnalog on the connected PC. The appropriate part type should be listed in the status bar of the VisualAnalog – New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 3, where the AD9253 is shown as an example).Figure 3. VisualAnalog, New Canvas Window2.After the template is selected, a message appears asking if the default configuration can be used to program the FPGA (see Figure 4). Click Yes, and the window closes.Figure 4. VisualAnalog Default Configuration Message3.To change features to settings other than the default settings, click the Expand Display button,located on the bottom right corner of the window (see Figure 5), to see what is shown in Figure 6. 4.Change the features and capture settings by consulting the detailed instructions in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual. After the changes are made to the capture settings, click the Collapse Display button.Figure 5. VisualAnalog Window Toolbar, Collapsed DisplayFigure 6. VisualAnalog, Main Window Expanded DisplayEvaluation And TestSetting up the SPI Controller SoftwareAfter the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:1.Open the SPI controller software by going to the Start menu or by double-clicking theSPIController software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. Ifnecessary, choose Cfg Open from the File menu and select the appropriate file based on your part type. Note that the CHIP ID(1) box should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 7).Figure 7. SPI Controller, CHIP ID(1) BoxClick the New DUT button in the SPIController window (see Figure 8)2.Figure 8. SPI Controller, New DUT Button3.In the ADCBase 0 tab of the SPIController window, find the CLOCK DIVIDE(B) box (see Figure9). If using the clock divider, use the drop-down box to select the correct clock divide ratio, ifnecessary. For additional information, refer to the data sheet, the AN-878 Application Note, High Speed ADC SPI Control Software, and the AN-877 Application Note, Interfacing to High Speed ADCsvia SPI.Figure 9. SPI Controller, CLOCK DIVIDE(B) Box4.Note that other settings can be changed on the ADCBase 0 tab (see Figure 9) and the ADC A, ADC B, ADC C, and ADC D tabs (see Figure 10) to set up the part in the desired mode. TheADCBase 0 tab settings affect the entire part, whereas the settings on the ADC A, ADC B, ADC C, and ADC D tabs affect the selected channel only. See the appropriate part data sheet, the AN-878 Application Note, High Speed ADC SPI Control Software, and the AN-877 Application Note,Interfacing to High Speed ADCs via SPI, for additional information on the available settings.Figure 10. SPI Controller, Example ADC A Page5.Click the Run button in the VisualAnalog toolbar (see Figure 11).Figure 11. Run Button (Encircled in Red) in VisualAnalog Toolbar, Collapsed DisplayAdjusting the Amplitude of the Input SignalThe next step is to adjust the amplitude of the input signal for each channel as follows:Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine 1.the Fund Power reading in the left panel of the VisualAnalog Graph - AD9253 FFT window(see Figure 12).Figure 12. Graph Window of VisualAnalogRepeat this procedure for Channel B, Channel C, and Channel D.2.3.Click the disk icon within the VisualAnalog Graph - AD9253 FFT window to save theperformance plot data as a .csv formatted file. See Figure 13 for an example.Figure 13. Typical FFT, AD9253Troubleshooting TipsIf the FFT plot appears abnormal, do the following:If you see an abnormal noise floor, go to the ADCBase0 tab of the SPIController window andqtoggle the Chip Power Mode in MODES(8) from Chip Run to Reset and back.If you see a normal noise floor when you disconnect the signal generator from the analog input, be qsure that you are not overdriving the ADC. Reduce the input level if necessary.In VisualAnalog, click the Settings icon in the Input Formatter block. Check that NumberqFormat is set to the correct encoding (twos complement by default). Repeat for the other channels.If the FFT appears normal but the performance is poor, check the following:Make sure that an appropriate filter is used on the analog input.qMake sure that the signal generators for the clock and the analog input are clean (low phase noise). qChange the analog input frequency slightly if noncoherent sampling is being used.qMake sure that the SPI configuration file matches the product being evaluated.qIf the FFT window remains blank after Run in VisualAnalog (see Figure 11) is clicked, do the following:Make sure that the evaluation board is securely connected to the HSC-ADC-EVALCZ board.qMake sure that the FPGA has been programmed by verifying that the DONE LED is illuminated onqthe HSC-ADC-EVALCZ board. If this LED is not illuminated, make sure that the U4 switch on the board is in the correct position for USB CONFIG.Make sure that the correct FPGA program was installed by clicking the Settings icon in the ADCqData Capture block in VisualAnalog. Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part.If VisualAnalog indicates that the FIFO Capture timed out, do the following:Make sure that all power and USB connections are secure.qProbe the DCO signal at P1002 (Pin A10 and/or Pin B10) on the evaluation board, and confirm that a qclock signal is present at the ADC sampling rate.© Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective 。
SignalTEK 10G 10G Ethernet Troubleshooter and Band
Why do I need a10G Ethernet T ester?ProblemLAN networks are at risk Solution SignalTEK 10G willAvoid network downtimeTroubleshoot Ethernet connectivity issues faster using diagnostic tools.Pinpoint bottlenecks fasterDiscover which part of your network is causing the bottleneck.Validate network upgradesVerify Multi-Gigabit switch upgrades to 1/2.5/5 and 10Gb/s speeds.Prove the maximum bandwidthProvide “proof of performance” PDF reports to the client.The new SignalTEK 10G measures the maximum bandwidth of the network cabling up to 10 Gigabits per second. Bysimulating actual network traffic users can test, troubleshoot and document network and data cable performance up to 10 Gigabit Ethernet standards.SignalTEK 10G has built-in Wi-Fi connectivity to connect seamlessly to the free AnyWARE Cloud test management system. AnyWARE Cloud offers pre-configuration to eliminate errors on-site, label printer connectivity to save time and “proof of performance” PDF reports for the clients.SignalTEK 10G10G Ethernet Troubleshooter and Bandwidth TesterIncrease your network speedfrom 1Gb/s to 10Gb/sProblemThere are 111 billion metres of Cat5e/Cat6 cabling installed globally that is limited to 1Gb/s bandwidth speeds due to the current switches deployed. Upgrading to Multi-Gigabit switches could increase speed but it is unclear what bandwidth the existing cabling will support.SolutionUse SignalTEK 10G to verify what the data cabling will support (up to 10Gb/s) before spending moneyon new Multi-Gigabit switches delivering2.5/5/10Gb/s speeds. Use the SignalTEK 10G again following the upgrade to prove performance to the client with the “proof of performance” PDF reports.As simple as 1-2-3Easy to understand traffic light status - The simple traffic lightindicator displays Good, Marginal or Poor power level based onIEEE 802.3 1G/10G limits.Max throughput test - The SignalTEK 10G will prove the maximumavailable bandwidth over the fibre link up to 10Gb/s.Discover a faulty SFP – The SFP temperature is measured to helpunderstand if it has become faulty.Will my existing cablinginfrastructure supportMulti-Gigabit technology?10G/Multi-Gigabit Performance90W PoE for AV and Digital SignageTest copper and fibrevertical cablingVoIP testing and troubleshootingMeets your network needs today and tomorrow.The SignalTEK 10G will help to increase network bandwidth without replacing expensive cableinfrastructure, troubleshoot PoE and Ethernet issues and prove the maximum bandwidth up to 10 Gigabits per second.6Testing through Network testing andConduct preventative maintenance testing, audit network capabilities and Prove performance of new cableinstallations up to 10GNetwork T estingThe SignalTEK 10G is also a network tester for troubleshooting and maintenance of active and passive copper and fibre networks.Port & network summary info Press the Autotest button to display summary information and allow for detailed inspection of networkparameters.VLAN detection & operationAutomatic detection of VLAN IDsallows the user to configure SignalTEK10G for operation on a VLAN.Custom WiremapUse a list of wiremap templates forcommon Ethernet cable types aswell as non-Ethernet cables, such asProfinet and ISDN.CDP/LLDP/EDP port informationShow port information using Cisco Discovery Protocol (CPD). Link Layer Discovery Protocol (LLDP) and Extreme Discovery Protocol (EDP).NetscanDisplay list of IP and MAC addressesof every device connected tothe network.72-hour event logFind rogue devices and intermittentissues using the 72-hour event log.SignalTEK 10G logs all network eventsover a 72-hour period to help diagnose connectivity issues faster, reducing hours onsite and reducing trips to the site. Leave the tester onsite, connect remotely tomonitor network activity, view the event log and control all functions of the tester from the office.The SignalTEK 10G will log all network eventsover a 72-hour period to help diagnose connectivity issues faster, reducing hoursonsite and reducing trips to site.72-hour event log captures network events down to the second eliminatingguessworkNo more trial and errorAccurately measure the maximum power available Supports PoE up to 90W (PoE++)Test all PoE Classes (0-8) and Types (af/at/bt)Identifies the powered pairsDetermine whether power is from a switch or mid-span injectorVerify the PoE installationPass / Fail indication to IEEE standards Extended power testSome switches may provide power exceeding their IEEE Class rating. Measure the maximum available power up to 90 watts.PoE T esting.Eliminate GuessworkThe SignalTEK 10Geliminates guesswork when installing, maintaining and troubleshooting wherePoE is deployed up to 90W (PoE++).10Adoption of Power over Ethernet (PoE)In just a few short years we have seen many different applications increasing adopt PoE, such as monitors, digital signage, phones, security cameras, lighting and access control.Previously technicians had to understand all the various standards, device power outputs and cable lengths to be sure a device will operate successfully.The SignalTEK 10G identifies the Class of the PoEsource and power available up to 90W to a PoE device regardless of cable length, cable quality or other factors. A clear pass/fail is provided to IEEE 802.3af/at/bt standards.The SignalTEK 10G identifies the Class of the PoE source and power available up to 90W to a PoE deviceregardless of cable length, cablequality or other factors.11Proof of PerformanceCloud software• Operates anywhere with a web browser – AnyWARE Cloud operates on a PC, Mac and tablet devices (Android and iOS)• Free storage – No need for separate servers or backup systems.• Easy to find project files – Attach all project filesincluding cable layout drawings, videos, and photos into the AnyWARE Cloud. Everything you need in one place. • Share reports easier – Use AnyWARE Cloud to share links to the test reports eliminating the need to manually email large attachments.• Reduce training time with WalkMe – AnyWARE Cloud is embedded with the WalkMe digital adoption platform providing proactive, step-by-step guidance on all key tasks.Fleet management• Easily manage the certifier fleet – Fleet manager allows you to see who has the SignalTEK 10G when the software was last updated and when the results were last synced. Allowing you to manage tester downtime and ensuring results are transferred back to the office and not lost or deleted.Professional PDF reporting• Customer profiles – Create a profile for each of thecustomers with their company logo, address and contact details. This information is automatically pulled through to the reports, saving time.Report formats• Summary report – This is a report showing multiple tests per page.• Detailed report – This is a comprehensive report with all the measurement results with one page per test. Reports can be generated on the SignalTEK 10G or on the free IDEAL AnyWARE Cloud.The AnyWARE Cloudmanagement system allows real time collaboration between Project Managers and Field Technicians. There is no need for Field Technicians to setup the SignalTEK 10G, Project Managers pre-configure thejobs and tests in the AnyWARE Cloud, eliminating potential mistakes and compressing the time taken to prepare reports for customers.Test Management SoftwareIDEAL AnyWARE Cloud Jobs screenIDEAL AnyWARE Cloud Test Result report12ax throughput test up to 10GComplete ConnectivityWi-Fi connectivity to the AnyWARE Cloud management system. USB connection for transferring test dataBuilt-in PDF ReportingReports can be generated directly from the SignalTEK 10G as well as the CloudPartner FinderProvides audible tone and visible indicator when connected tothe remote unitTouchscreenHigh resolution impact resistant touchscreenfor ease of useInternal LoadspeakerAudible tones assist theuser when testingIntuitive UserInterfaceSimplified user interfacefor easy setup andoperationRugged DesignRubberised housing, protected screenand protected measurement portLabel Printer ConnectivityEasily send label IDs to printers for fast and accurate labellingSignalTEK 10GPart NoDescriptionUPGRADE10GFIB UPGRADE SignalTEK 10G - Fibre testing option UPGRADE10GNETUPGRADE SignalTEK 10G - Network testing optionSignalTEK 10G is a future-proof investment as additional features can be unlocked with a simple license key when required. There are two upgrade options to choose from: fibre testing and advanced network testing.Future-proof the investment14Who is SignalTEK 10G designed for?SolutionSignalTEK 10GCT R157000SignalTEK 10GFT R157001SignalTEK 10GNT R157002SignalTEK 10GPRO R157003CategoryDisplays voltage and which pairs have PoEPass / Fail to PoE IEEE standardsMax power available (up to 90 watts)Type (af/at/bt) and Class (1 to 8)P o EF i b r eo p t i o n a lC o p p e rUptime efficiency and 72 hour event log Switch Speed - 100M, 1G, 2.5G, 5G, 10G Testing with packet loss, jitter and delay VLAN, PING, TraceRoute, Hub blink, NetScanProve network performance up to 10GCDP/LLDP/EDP port information N e t w o r ko p t i o n a lPass / Fail to fibre IEEE standards Wiremap, distance to fault, length Optical Tx/Rx power indication Max bandwidth test up to 10Gb/s SFP temperature, vendor and model Cable tracing (with compatible probe)Max bandwidth test up to 10Gb/sData transmission test 1/2.5/5/10GbSupports SFP/SFP+ (MM&SM)Pass / Fail to copper IEEE standardsData transmission test 1/10Gb NbaseT/Multi-Gigabit test 1/2.5/5/10Gb 15Proof of PerformanceIDEAL NETWORKS, SignalTEK and the IDEAL AnyWARE logos are trademarks or registered trademarks of IDEAL INDUSTRIES NETWORKS LIMITED.IDEAL INDUSTRIES NETWORKS LIMITEDStokenchurch House, Oxford Road, Stokenchurch, High Wycombe, Buckinghamshire, HP14 3SX, UK.Tel. +44 (0)1925 428 380 | Fax. +44 (0)1925 428 381********************Specification subject to change without notice. E&OE© IDEAL INDUSTRIES NETWORKS LIMITED 2020Publication no.: 157805 Rev.1SignalTEK 10G10G Ethernet Troubleshooterand Bandwidth TesterOrdering informationOptional Accessories。
Honor Chemistry
1. Which one of the following is a pure substance?A) tap waterB) rockC) airD) elemental oxygenE) apple2. _______ do not have a fixed volume as they are able to be compressed.A) LiquidsB) GasesC) SolidsD) A and B3. Homogeneous mixtures are also known as ________.A) solidsB) compoundsC) elementsD) substancesE) solutions4. Which one of the following has the element name and symbol correctly matched?A) S, sodiumB) Tn, tinC) Pb, leadD) N, neonE) B, bromine5. Which one of the following is often easily separated into its components by simple techniques such as filtering?A) heterogeneous mixtureB) compoundsC) homogeneous mixtureD) elementsE) solutions6. In the following list, only ________ is not an example of a chemical reaction.A) dissolution of a penny in nitric acidB) the condensation of water vaporC) a burning candleD) the rusting of iron7. Which one of the following is not an intensive property?A) densityB) temperatureC) melting pointD) massE) boiling point8. The temperature of 25 °C is ________ in Kelvins.A) 103B) 138C) 166D) 248E) 2989. A common English set of units for expressing velocity is miles/hour. The SI unit for velocity is ________.A) km/hrB) km/sC) m/hrD) m/sE) cm/s10. The correct result (indicating the proper number of significant figures) of the following addition is ________.12 + 1.2 + 0.12 + 0.012 =A) 13B) 13.3C) 13.33D) 13.332E) none of the above11. The correct result (indicating the proper number of significant figures) of the following problem is ________.0.00032(12.80184)(0.002843)A) 113.73635B) 113.736C) 113.74D) 113.7E) 1.1 × 10212. Accuracy refers to ________.A) how close a measured number is to zeroB) how close a measured number is to the calculated valueC) how close a measured number is to other measured numbersD) how close a measured number is to the true valueE) how close a measured number is to infinity13. Which pair of substances could be used to illustrate the law of multiple proportions?A) SO 2, H 2SO 4B) CO, CO 2C) H 2O, O 2D) CH 4, C 6H 12O 6E) NaCl, KCl14. The charge on an electron was determined in the ________.A) cathode ray tube, by J. J. ThomsonB) Rutherford gold foil experimentC) Millikan oil drop experimentD) Dalton atomic theory15. Of the three types of radioactivity characterized by Rutherford, which is/are electrically charged?A) β-raysB) α-rays and β-raysC) α-rays, β-rays, and γ-raysD) α-raysE) α-rays and γ-rays16. Of the following, the smallest and lightest subatomic particle is the ________.A) neutronB) protonC) electronD) nucleusE) alpha particle17. Which atom has the smallest number of neutrons?A) carbon-14B) nitrogen-14C) oxygen-16D) fluorine-19E) neon-2018. Which combination of protons, neutrons, and electrons is correct for the isotope of copper, 63Cu29A) 29 p+, 34 n°, 29 e-B) 29 p+, 29 n°, 63 e-C) 63 p+, 29 n°, 63 e-D) 34 p+, 29 n°, 34 e-E) 34 p+, 34 n°, 29 e-19. Isotopes are atoms that have the same ________ but differing ________.A) atomic masses, chargesB) mass numbers, atomic numbersC) atomic numbers, mass numbersD) charges, atomic massesE) mass numbers, charges20. Elements ________ exhibit similar physical and chemical properties.A) with similar chemical symbolsB) with similar atomic massesC) in the same period of the periodic tableD) on opposite sides of the periodic tableE) in the same group of the periodic table21. An element in the upper right corner of the periodic table ________.A) is either a metal or metalloidB) is definitely a metalC) is either a metalloid or a nonmetalD) is definitely a nonmetal22. Which one of the following molecular formulas is also an empirical formula?A) C6H6O2B) C2H6SOC) H2O2D) C6H623. The elements in groups 1A, 6A, and 7A are called ________, respectively.A) alkaline earth metals, halogens, and chalcogensB) alkali metals, chalcogens, and halogensC) alkali metals, halogens, and noble gasesD) alkaline earth metals, transition metals, and halogensE) halogens, transition metals, and alkali metals24. Of the choices below, which one is not an ionic compound?A) PCl5B) MoCl6C) RbClD) PbCl2E) NaCl25 Formulas that show how atoms are attached in a molecule are called ________.A) molecular formulasB) structural formulasC) empirical formulasD) diatomic formulas26. Of the following, ________ contains the greatest number of electrons.A) P3+B) PC) P2-D) P3-E) P2+27. The formula for a salt is XBr. The X-ion in this salt has 46 electrons. The metal X is ________.A) AgB) PdC) CdD) CuE) Cs28. The correct name for Al2O3 is ________.A) aluminum oxideB) dialuminum oxideC) dialuminum trioxideD) aluminum hydroxideE) aluminum trioxide29. Which one of the following is the formula of hydrochloric acid?A) HClO3B) HClO4C) HClOD) HClE) HClO230. Which formula/name pair is incorrect?A) Mn(NO2)2 manganese(II) nitriteB) Mg(NO3)2 magnesium nitrateC) Mn(NO3)2 manganese(II) nitrateD) Mg3N2 magnesium nitriteE) Mg(MnO4)2 magnesium permanganate31. The correct name for N2O5 is ________.A) nitrous oxideB) nitrogen pentoxideC) dinitrogen pentoxideD) nitric oxideE) nitrogen oxide32. Of the following, ________ radiation has the shortest wavelength.A) X-rayB) radioC) microwaveD) ultravioletE) infrared33. All of the orbitals in a given electron shell have the same value as the ________ quantum number.A) principalB) angular momentumC) magneticD) spin34. There are ________ unpaired electrons in a ground state phosphorus atom.A) 4B) 3C) 2D) 1E) 035. The principal quantum number of the first d subshell is ________.A) 1B) 2C) 3D) 4E) 036. Which of the following is not a valid set of four quantum numbers? (n, l, m l, m s)A) 2, 0, 0, +1/2B) 2, 1, 0, -1/2C) 3, 1, -1, -1/2D) 1, 0, 0, +1/2E) 1, 1, 0, +1/237. The ________ quantum number defines the shape of an orbital.A) spinB) magneticC) principalD) angular momentum38. Which set of three quantum numbers (n, l, m l) corresponds to a 5p orbital?A) 5,2,1B) 5,0,2C) 4,1,1D) 5,1,0E) 5,1,239. Elements in group ________ have a np6 electron configuration in the outer shell.A) 4AB) 6AC) 7AD) 8AE) 5A40. The condensed electron configuration of argon, element 18, is ________.A) [Ne]3s4B) [Ar]3s23p2C) [Ne]3s23p6D) [He]2s42p10E) [He]3s441. Which one of the following substances is the product of this combination reaction?Al (s) + I2(s) → ________A) AlI2B) AlIC) AlI3D) Al2I3E) Al3I242. Which of the following are combination reactions?1) CH4 (g) + O2(g) → CO2 (g) + H2O (l)2) CaO (s) + CO2(g) → CaCO3 (s)3) Mg (s) + O2(g) → MgO (s)4) PbCO3(s) → PbO (s) + CO2 (g)A) 1, 2, and 3B) 2 and 3C) 1, 2, 3, and 4D) 4 onlyE) 2, 3, and 443. One mole of ________ contains the largest number of atoms.A) S8B) C10H8C) Al2(SO4)3D) Na3PO4E) Cl244. How many atoms of nitrogen are in 10 g of NH4NO3?A) 3.5B) 1.5 × 1023C) 3.0 × 1023D) 1.8E) 245. Which one of the following compounds is insoluble in water?A) Na2CO3B) K2SO4C) Fe(NO3)3D) FeSE) AgNO346. Which combination will produce a precipitate?A) NaCH3CO2 and HClB) NaOH (aq) and HCl (aq)C) AgNO3(aq) and Ca(CH3CO2)2 (aq)D) KOH and Mg(NO3)2E) NaF (aq) and HCl (aq)。
TLC5617中文资料
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Silicon Labs EFR32MG 2.4 GHz 19.5 dBm 无线模组板参考手册说明书
EFR32MG 2.4 GHz 19.5 dBm Radio BoardBRD4151A Reference Manualance, low energy wireless solution integrated into a small formfactor package.By combining a high performance 2.4 GHz RF transceiver with an energy efficient 32-bitMCU, the family provides designers the ultimate in flexibility with a family of pin-compati-ble devices that scale from 128/256 kB of flash and 16/32 kB of RAM. The ultra-lowpower operating modes and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, combined with the low transmit and receive power consumption of the 2.4GHz radio, result in a solution optimized for battery powered applications.To develop and/or evaluate the EFR32 Mighty Gecko, the EFR32MG Radio Board canbe connected to the Wireless Starter Kit Mainboard to get access to display, buttons andadditional features from Expansion Boards.Introduction 1. IntroductionThe EFR32 Mighty Gecko Radio Boards provide a development platform (together with the Wireless Starter Kit Mainboard) for the Silicon Labs EFR32 Mighty Gecko Wireless System on Chips and serve as reference designs for the matching network of the RF inter-face.The BRD4151A Radio Board is designed to operate in the 2400-2483.5 MHz band with the RF matching network optimized to operate with 19.5 dBm output power.To develop and/or evaluate the EFR32 Mighty Gecko, the BRD4151A Radio Board can be connected to the Wireless Starter Kit Main-board to get access to display, buttons and additional features from Expansion Boards and also to evaluate the performance of the RF interface.2. Radio Board Connector2.1 IntroductionThe board-to-board connector scheme allows access to all EFR32MG1 GPIO pins as well as the RESETn signal. For more information on the functions of the available pin functions, see the EFR32MG1 data sheet.2.2 Radio Board Connector Pin AssociationsThe figure below shows the pin mapping on the connector to the radio pins and their function on the Wireless Starter Kit Mainboard.GND F9 / PA3 / VCOM.#RTS_#CS 3v3UIF_BUTTON1 / PF7 / P36P200Upper RowNC / P38NC / P40NC / P42NC / P44DEBUG.TMS_SWDIO / PF1 / F0DISP_ENABLE / PD15 / F14UIF_BUTTON0 / PF6 / F12DISP_EXTCOMIN / PD13 / F10VCOM.#CTS_SCLK / PA2 / F8#RESET / F4DEBUG.TDO_SWO / PF2 / F2DISP_SI / PC6 / F16VCOM.TX_MOSI / PA0 / F6PTI.DATA / PB12 / F20DISP_EXTCOMIN / PD13 / F18USB_VBUS5VBoard ID SCLGND Board ID SDAUSB_VREG F7 / PA1 / VCOM.RX_MISO F5 / PA5 / VCOM_ENABLE F3 / PF3 / DEBUG.TDI F1 / PF0 / DEBUG.TCK_SWCLK P45 / NC P43 / NCP41 / NCP39 / NCP37 / High / SENSOR_ENABLEF11 / PF5 / UIF_LED1F13 / PF7 / UIF_BUTTON1F15 / PC8 / DISP_SCLK F17 / PD14 / DISP_SCS F19 / PB13 / PTI.SYNC F21 / PB11 / PTI.CLK GNDVMCU_INVCOM.#CTS_SCLK / PA2 / P0P201Lower RowVCOM.#RTS_#CS / PA3 / P2PD10 / P4PD11 / P6GND VRF_INP35 / PD15 / DISP_ENABLE P7 / PC9P5 / PC8 / DISP_SCLK P3 / PC7P1 / PC6 / DISP_SI P33 / PD14 / DISP_SCSP31 / PD13 / DISP_EXTCOMIN P29 / NCP27 / NC P25 / NC P23 / NC P21 / NC P19 / NC P17 / NC P15 / NC P13 / PC11P11 / PA1 / VCOM.RX_MISO P9 / PA0 / VCOM.TX_MOSI UIF_BUTTON0 / PF6 / P34UIF_LED1 / PF5 / P32UIF_LED0 / PF4 / P30DEBUG.TDO_SWO / PF2 / P28DEBUG.TMS_SWDIO / PF1 / P26DEBUG.TCK_SWCLK / PF0 / P24PTI.SYNC / PB13 / P22PTI.DATA / PB12 / P20PTI.CLK / PB11 / P18VCOM_ENABLE / PA5 / P16PA4 / P14PC10 / P12DEBUG.TDI / PF3 / P10PD12 / P8Figure 2.1. BRD4151A Radio Board Connector Pin MappingRadio Board Connector3. Radio Board Block Summary3.1 IntroductionThis section gives a short introduction to the blocks of the BRD4151A Radio Board.3.2 Radio Board Block DiagramThe block diagram of the EFR32MG Radio Board is shown in the figure below.Figure 3.1. BRD4151A Block Diagram3.3 Radio Board Block Description3.3.1 Wireless MCUThe BRD4151A EFR32 Mighty Gecko Radio Board incorporates an EFR32MG1P232F256GM48 Wireless System on Chip featuring 32-bit Cortex-M4 with FPU core, 256 kB of flash memory and 32 kB of RAM and a 2.4 GHz band transceiver with output power up to 19.5 dBm. For additional information on the EFR32MG1P232F256GM48, refer to the EFR32MG1 Data Sheet.3.3.2 LF Crystal Oscillator (LFXO)The BRD4151A Radio Board has a 32.768 kHz crystal mounted.3.3.3 HF Crystal Oscillator (HFXO)The BRD4151A Radio Board has a 38.4 MHz crystal mounted.3.3.4 Matching Network for 2.4 GHzThe BRD4151A Radio Board incorporates a 2.4 GHz matching network which connects the 2.4 GHz TRX pin of the EFR32MG1 to the one on-board printed Inverted-F antenna. The component values were optimized for the 2.4 GHz band RF performace and current con-sumption with 19.5 dBm output power.For detailed description of the matching network, see Chapter 4.2.1 Description of the 2.4 GHz RF Matching.| Smart. Connected. Energy-friendly.Rev. 1.7 | 33.3.5 Inverted-F AntennaThe BRD4151A Radio Board includes a printed Inverted-F antenna (IFA) tuned to have close to 50 Ohm impedance at the 2.4 GHz band.For detailed description of the antenna see Chapter 4.5 Inverted-F Antenna.3.3.6 UFL ConnectorTo be able to perform conducted measurements, Silicon Labs added an UFL connector to the Radio Board. The connector allows an external 50 Ohm cable or antenna to be connected during design verification or testing.Note: By default the output of the matching network is connected to the printed Inverted-F antenna by a series component. It can be connected to the UFL connector as well through a series 0 Ohm resistor which is not mounted by default. For conducted measurements through the UFL connector the series component to the antenna should be removed and the 0 Ohm resistor should be mounted (see Chapter 4.2 Schematic of the RF Matching Network for further details).3.3.7 Radio Board ConnectorsTwo dual-row, 0.05” pitch polarized connectors make up the EFR32MG Radio Board interface to the Wireless Starter Kit Mainboard. For more information on the pin mapping between the EFR32MG1P232F256GM48 and the Radio Board Connector, refer to Chapter 2.2 Radio Board Connector Pin Associations.4. RF Section4.1 IntroductionThis section gives a short introduction to the RF section of the BRD4151A.4.2 Schematic of the RF Matching NetworkThe schematic of the RF section of the BRD4151A Radio Board is shown in the following figure.U1BPath Inverted-F Antenna2.4 GHz Matching Figure 4.1. Schematic of the RF Section of the BRD4151A4.2.1 Description of the 2.4 GHz RF MatchingThe 2.4 GHz matching connects the 2G4RF_IOP pin to the on-board printed Inverted-F Antenna. The 2G4RF_ION pin is connected to ground. For higher output powers (13 dBm and above) beside the impedance matching circuitry it is recommended to use additional harmonic filtering as well at the RF output. The targeted output power of the BRD4151A board is 19.5 dBm. As a result, the RF output of the IC is connected to the antenna through a four-element impedance matching and harmonic filter circuitry.For conducted measurements the output of the matching network can also be connected to the UFL connector by relocating the series R1 resistor (0 Ohm) to the R2 resistor position between the output of the matching and the UFL connector.4.3 RF Section Power SupplyOn the BRD4151A Radio Board the supply pin of the RF Analog Power (RFVDD) is connected directly ot the output of the on-chip DC-DC converter while the supply for the 2.4 GHz PA (PAVDD) is provided directly by the mainboard. This way, by default, the DC-DC converter provides 1.8 V for the RF analog section, the mainboard provides 3.3 V for the PA (for details, see the schematic of the BRD4151A).4.4 Bill of Materials for the 2.4 GHz MatchingThe Bill of Materials of the 2.4 GHz matching network of the BRD4151A Radio Board is shown in the following table.Table 4.1. Bill of Materials for the BRD4151A 2.4 GHz 19.5 dBm RF Matching Network | Smart. Connected. Energy-friendly.Rev. 1.7 | 54.5 Inverted-F AntennaThe BRD4151A Radio Board includes an on-board printed Inverted-F Antenna tuned for the 2.4 GHz band. Due to the design restric-tions of the Radio Board the input of the antenna and the output of the matching network can't be placed directly next to each other. Therefore, a 50 Ohm transmission line was necessary to connect them. The resulting impedance and reflection measured at the output of the matcing network are shown in the following figure. As it can be observed the impedance is close to 50 Ohm (the reflection is better than -10 dB) for the entire 2.4 GHz band.Figure 4.2. Impedance and Reflection of the Inverted-F Antenna of the BRD4151A| Smart. Connected. Energy-friendly.Rev. 1.7 | 65. Mechanical DetailsThe BRD4151A EFR32 Mighty Gecko Radio Board is illustrated in the figures below.45 mmFigure 5.1. BRD4151A Top View5 mm ConnectorConnectorFigure 5.2. BRD4151A Bottom ViewMechanical DetailsRev. 1.7 | 7EMC Compliance 6. EMC Compliance6.1 IntroductionCompliance of the fundamental and harmonic levels is tested against the following standards:• 2.4 GHz:•ETSI EN 300-328•FCC 15.2476.2 EMC Regulations for 2.4 GHz6.2.1 ETSI EN 300-328 Emission Limits for the 2400-2483.5 MHz BandBased on ETSI EN 300-328 the allowed maximum fundamental power for the 2400-2483.5 MHz band is 20 dBm EIRP. For the unwan-ted emissions in the 1 GHz to 12.75 GHz domain the specified limit is -30 dBm EIRP.6.2.2 FCC15.247 Emission Limits for the 2400-2483.5 MHz BandFCC 15.247 allows conducted output power up to 1 Watt (30 dBm) in the 2400-2483.5 MHz band. For spurious emmissions the limit is -20 dBc based on either conducted or radiated measurement, if the emission is not in a restricted band. The restricted bands are speci-fied in FCC 15.205. In these bands the spurious emission levels must meet the levels set out in FCC 15.209. In the range from 960 MHz to the frequency of the 5th harmonic it is defined as 0.5 mV/m at 3 m distance (equals to -41.2 dBm in EIRP).Additionally, for spurious frequencies above 1 GHz, FCC 15.35 allows duty-cycle relaxation to the regulatory limits. For the EmberZNet PRO the relaxation is 3.6 dB. Therefore, the -41.2 dBm limit can be modified to -37.6 dBm.If operating in the 2400-2483.5 MHz band the 2nd, 3rd and 5th harmonics can fall into restricted bands. As a result, for those the -37.6 dBm limit should be applied. For the 4th harmonic the -20 dBc limit should be applied.6.2.3 Applied Emission Limits for the 2.4 GHz BandThe above ETSI limits are applied both for conducted and radiated measurements.The FCC restricted band limits are radiated limits only. Besides that, Silicon Labs applies those to the conducted spectrum i.e., it is assumed that, in case of a custom board, an antenna is used which has 0 dB gain at the fundamental and the harmonic frequencies. In that theoretical case, based on the conducted measurement, the compliance with the radiated limits can be estimated.The overall applied limits are shown in the table below.Table 6.1. Applied Limits for Spurious Emissions for the 2.4 GHz Band | Smart. Connected. Energy-friendly.Rev. 1.7 | 87. RF Performance7.1 Conducted Power MeasurementsDuring measurements, the EFR32MG Radio Board was attached to a Wireless Starter Kit Mainboard which was supplied by USB. The voltage supply for the Radio Board was 3.3 V.7.1.1 Conducted Measurements in the 2.4 GHz bandThe BRD4151A board was connected directly to a Spectrum Analyzer through its UFL connector (the R1 resistor (0 Ohm) was removed and a 0 Ohm resistor was soldered to the R2 resistor position). During measurements, the voltage supply for the board was 3.3 V provi-ded by the mainboard. The supply for the radio (RFVDD) was 1.8 V provided by the on-chip DC-DC converter, the supply for the power amplifier (PAVDD) was 3.3 V (for details, see the schematic of the BRD4151A). The transceiver was operated in continuous carrier transmission mode. The output power of the radio was set to the maximum level.The typical output spectrum is shown in the following figure.Figure 7.1. Typical Output Spectrum of the BRD4151AAs it can be observed, the fundamental is slightly lower than 19.5 dBm and the strongest unwanted emission is the double-frequency harmonic and it is under the -37.6 dBm applied limit.Note: The conducted measurement is performed by connecting the on-board UFL connector to a Spectrum Analyzer through an SMA Conversion Adapter (P/N: HRMJ-U.FLP(40)). This connection itself introduces approximately a 0.3 dB insertion loss.RF PerformanceRev. 1.7 | 97.2 Radiated Power MeasurementsDuring measurements, the EFR32MG Radio Board was attached to a Wireless Starter Kit Mainboard which was supplied by USB. The voltage supply for the Radio Board was 3.3 V. The radiated power was measured in an antenna chamber by rotating the DUT 360degrees with horizontal and vertical reference antenna polarizations in the XY , XZ and YZ cuts. The measurement axes are shown inthe figure below.Figure 7.2. DUT: Radio Board with the Wireless Starter Kit Mainboard (Illustration)Note: The radiated measurement results presented in this document were recorded in an unlicensed antenna chamber. Also the radi-ated power levels may change depending on the actual application (PCB size, used antenna, and so on). Therefore, the absolute levels and margins of the final application are recommended to be verified in a licensed EMC testhouse.7.2.1 Radiated Measurements in the 2.4 GHz bandFor the transmitter antenna, the on-board printed Inverted-F antenna of the BRD4151A board was used (the R1 resistor (0 Ohm) was mounted). During the measurements the board was attached to a Wireless Starter Kit Mainboard (BRD4001 (Rev. A02) ) which was supplied through USB. During measurements, the voltage supply for the board was 3.3 V provided by the mainboard. The supply for the radio (RFVDD) was 1.8 V provided by the on-chip DC-DC converter, the supply for the power amplifier (PAVDD) was 3.3 V (for details, see the schematic of the BRD4151A). The transceiver was operated in continuous carrier transmission mode. The output power of the radio was set to the maximum level.The results are shown in the table below.Table 7.1. Maximums of the Measured Radiated Powers of BRD4151AAs it can be observed, thanks to the high gain of the Inverted-F antenna, the level of the fundamental is higher than 19.5 dBm. The strongest harmonic is the double-frequency one but its level is under -45 dBm.RF PerformanceEMC Compliance Recommendations 8. EMC Compliance Recommendations8.1 Recommendations for 2.4 GHz ETSI EN 300-328 complianceAs it was shown in the previous chapter, the radiated power of the fundamental of the BRD4151A EFR32 Mighty Gecko Radio Board complies with the 20 dBm limit of the ETSI EN 300-328 in case of the conducted measurement but due to the high antenna gain the radiated power is higher than the limit by 2 dB. In order to comply, the output power should be reduced (with different antennas, de-pending on the gain of the used antenna, the necessary reduction can be different). The harmonic emissions are under the -30 dBm limit. Although the BRD4151A Radio Board has an option for mounting a shielding can, that is not required for the compliance.8.2 Recommendations for 2.4 GHz FCC 15.247 complianceAs it was shown in the previous chapter, the radiated power of the fundamental of the BRD4151A EFR32 Mighty Gecko Radio Board complies with the 30 dBm limit of the FCC 15.247. The harmonic emissions are under the -37.6 dBm applied limit both in case of the conducted and the radiated measurements. Although the BRD4151A Radio Board has an option for mounting a shielding can, that is not required for the compliance.Board Revisions 9. Board RevisionsTable 9.1. BRD4151A Radio Board RevisionsNote: The silkscreen marking on the board (e.g., PCBxxxx A00) denotes the revision of the PCB. The revision of the actual Radio Board can be read from the on-board EEPROM.Errata 10. ErrataTable 10.1. BRD4151A Radio Board ErrataDocument Revision History 11. Document Revision HistoryRevision 1.72016-11-20Minor editorial updates.Revision 1.62016-10-31Corrected error in radio board connector pinout diagram.Revision 1.52016-05-24Updating Board Revisions content. Fixing Errata description.Revision 1.42016-05-05Adding Introduction chapter; moving SoC Description chapter (short ver.) to Block Description chapter. Minor improvements.Revision 1.32016-02-11Addign RF Section Power Supply chapter. Minor improvements.Revision 1.22016-01-28Fixing image render problem.Revision 1.12015-25-25Updating Inverted-F Antenna Chapter and radiated measurement results based on board revision B02.Revision 1.02015-11-27Initial release.Table of Contents1. Introduction (1)2. Radio Board Connector (2)2.1 Introduction (2)2.2 Radio Board Connector Pin Associations (2)3. Radio Board Block Summary (3)3.1 Introduction (3)3.2 Radio Board Block Diagram (3)3.3 Radio Board Block Description (3)3.3.1 Wireless MCU (3)3.3.2 LF Crystal Oscillator (LFXO) (3)3.3.3 HF Crystal Oscillator (HFXO) (3)3.3.4 Matching Network for 2.4 GHz (3)3.3.5 Inverted-F Antenna (4)3.3.6 UFL Connector (4)3.3.7 Radio Board Connectors (4)4. RF Section (5)4.1 Introduction (5)4.2 Schematic of the RF Matching Network (5)4.2.1 Description of the 2.4 GHz RF Matching (5)4.3 RF Section Power Supply (5)4.4 Bill of Materials for the 2.4 GHz Matching (5)4.5 Inverted-F Antenna (6)5. Mechanical Details (7)6. EMC Compliance (8)6.1 Introduction (8)6.2 EMC Regulations for 2.4 GHz (8)6.2.1 ETSI EN 300-328 Emission Limits for the 2400-2483.5 MHz Band (8)6.2.2 FCC15.247 Emission Limits for the 2400-2483.5 MHz Band (8)6.2.3 Applied Emission Limits for the 2.4 GHz Band (8)7. RF Performance (9)7.1 Conducted Power Measurements (9)7.1.1 Conducted Measurements in the 2.4 GHz band (9)7.2 Radiated Power Measurements (10)7.2.1 Radiated Measurements in the 2.4 GHz band (10)8. EMC Compliance Recommendations (11)8.1 Recommendations for 2.4 GHz ETSI EN 300-328 compliance (11)8.2 Recommendations for 2.4 GHz FCC 15.247 compliance (11)9. Board Revisions (12)10. Errata (13)11. Document Revision History (14)Table of Contents (15)Silicon Laboratories Inc.400 West Cesar Chavez Austin, TX 78701USASimplicity StudioOne-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux!IoT Portfolio /IoTSW/HW/simplicityQuality/qualitySupport and CommunityDisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. 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微芯片 dsPIC30F 音频回声消除库文档说明书
DS70148B-14dsPIC30FAcoustic Echo Cancellation LibraryDevices SupporteddsPIC30F6014dsPIC30F6014A dsPIC30F6012dsPIC30F6012AdsPIC30F5013 (for a max. of 32 ms echo delay)dsPIC30F5011 (for a max. of 32 ms echo delay)SummaryThe dsPIC30F Acoustic Echo Cancellation (AEC) Library provides a function to eliminate echo generated in the acoustic path between a speaker and a microphone. This function is useful for speech and telephony applications in which a speaker and a microphone are located in close proximity to each other and are susceptible to signals propagating from the speaker to the microphone resulting in a perceptible and distracting echo effect at the far-end. It is especially suitable for these applications:• Hands-free cell phone kits • Speakerphones • Intercoms• Teleconferencing systemsFor hands-free phones intended to be used in compact environments, such as a car cabin, this library is fully compliant with the G.167 standard for acoustic echo cancellation.The AEC Library is written entirely in assembly language and is highly optimized to make extensive use of the dsPIC30F DSP instruction set and advanced addressing modes. The algorithm avoids data overflow. The AEC Library provides an “AcousticEchoCancellerInit ” function for initializing the various data structures required by the algorithm and an “AcousticEchoCanceller ” function to remove the echo component from a 10 ms block of sampled 16-bit speech data. The user can easily call both functions through a well-documented Application Programmer’s Interface (API).The “AcousticEchoCanceller ” function is primarily a Time Domain algorithm. The received far-end speech samples (typically received across a communication channel such as a telephone line) are filtered using an adaptive Finite Impulse Response (FIR) filter. The coefficients of this filter are adapted using the Normalized Least Mean Square (NLMS) algorithm, such that the filter closely models the acoustic path between the near-end speaker and the near-end microphone (i.e., the path traversed by the echo). Voice Activity Detection (VAD) and Double Talk Detection (DTD) algorithms are used to avoid updating the filter coefficients when there is no far-end speech and also when there is simultaneous speech from both ends of the communication link (double talk). As a consequence, the algorithm functions correctly even in the presence of full-duplex communication. A Non-Linear Processor (NLP) algorithm is used to eliminate residual echo.The dsPIC30F Acoustic Echo Cancellation Library uses an 8 kHz sampling rate. However, the library includes a sample rate conversion function that ensures interoperability with libraries designed for higher sampling rates (9.6 kHz, 11.025 kHz or 12 kHz). The conversion function allows incoming signals at higher sampling rates to be converted to a representative 8 kHz sample. Similarly, the conversion function allows the output signal to be converted upward from 8 kHz to match the user application.FeaturesKey features of the Acoustic Echo Cancellation Librar include:• All functions can be called from either a C or assembly applicationprogram• Five user functions:– AcousticEchoCancellerInit – AcousticEchoCanceller – InitRateConverter – SRC_upConvert – SRC_downConvert• Full compliance with the Microchip MPLAB® C30 C Compiler,assembler and linker• Simple user interface – one library file and one header file• Highly optimized assembly code, utilizing DSP instructions andadvanced addressing modes• Echo cancellation for 16, 32 or 64 ms echo delays or ‘tail lengths’(configurable)• Fully tested for compliance with G.167 specifications for in-carapplications• Audio bandwidth: 0-4 kHz at 8 kHz sampling rate• Convergence rate: Up to 43 dB/sec., typically > 30 dB/sec.• Echo cancellation: Up to 50 dB, typically > 40 dB• Can be used together with the Noise Suppression (NS) Library, sincethe same processing block size (10 ms) is used• dsPIC30F Acoustic Echo Cancellation Library User’s Guide is included • Demo application source code is provided with the library• Accessory Kit available for purchase includes an audio cable,headset, oscillators, microphone, speaker, DB9 M/F RS-232 cable, DB9M-DB9M null modem adapter and can be used for library evaluation64 16.5 6 5.7 32 10.5 6 3.4 16 7.5 6 2.6Sample Rate ConversionComputational requirements: 1 MIPS Program Flash memory: 2.6 KB RAM: 0.5 KBNote: The user application might require an additional 2 to 2.5 KB of RAM for data buffering (application-dependent)。
挤压机部件中英文对照
annex1EXTRUSION PRESSHYDRAULIC CIRCUITCONTROL SYSTEMCONTAINEREXIT HOLEDIE PACKMAIN PUMPSframeaccessoryLOW SPEED PUMPCONTAINER SEALING PUMPAUXILIARY PUMPFILTERING PUMPSOIL-TO-WATER HEAT EXCHANGERHYDRAULIC MANIFOLDSPRE-FILLING VALVEOIL TANKELETRIC MOTORP3/16billet loaderreaction beam DANIEL挤压机部件中英文对照P2/16cylindersDie cassettedummy blockCounter platenP5/16tie rodscasingsmain cylinder platendie platennutshydraulic jacksmain beamsVariable displacement main pumpsproportional valvehigh-pressure pumprelief valveSmall pumpsmain ramcontainer holderbutt shear/Discard shearP8/16Side cylinders Discard shear bladeP4/16P9/16Discard knocker P10/16DIE pack cylinder P11/16Variable Delivery pump Low speed pump Axial pump P12/16Filter mesh Oil tank Heater resistance Main Pump Motor Auxiliary Pump Motor Low speed pump motor Cooling pump Motor Sealing pump motor annex2 P2/76MOVABLE CROSSHEADCONTAINER SHIFTING CYLINDERSDIE STACK LOCKING DEVICESHEAR BLADE LUBRICATION SYSTEMDIE CHANGING SYSTEMDISCARD DETECTIONDUMMY BLOCK LUBRICATION SYSTEMLUBRICATION SYSTEMP13/16P9/16TOOLING SETPRESS EXIT MOUTH SAFETY SYSTEMWATER COOLING DEVICE (ENGINEERING ONLY)HIGH PRESSURE CIRCUITLOW PRESSURE CIRCUITCOOLING SYSTEMFILTERING SYSTEMHYDRAULIC CONTROL (MANIFOLDS)HIGH AND LOW PRESSURE PIPINGAC MOTORS ACINCOMING LINEMAIN MOTOR STARTERSAUXILIARY MOTOR STARTERHEATER CIRCUITDIE HEATER CIRCUITPLC SYSTEM FOR EXTRUSION CONTROLP3/76POWER SUPPLY FOR AUTOMATION COMPONENTSCONTROLS CARDS SENSORSMACHINE ACCESSORYEXTRUSION PRESS CONTROL DESKLOCAL CONTROL PULPITTERMINAL BOX (REMOTE I/O) AND SENSORDP/DP- TCP/IP INTERFACE DP/DP- TCP/IPHUMAN MACHINE INTERFACEMOTOR CABLESSAFETY RELAY (PILZ PNOZ MULTI)Extrusion PLC control systemP8/76stemtie rodsP10/76BedplateThe support framesStandard embedded partbolts and nutsTie rods housings and casingsP11/76Main cylinderlong bronze bushesmain ramP12/76side cylindersmoving crossheadSquare casingsP13/76flat guidesP14/76sliding blocksThe stem pressure ringslide shifting cylinderstem locking deviceconnection housingsStem locking ringP15/76double acting cylindersP16/76container centering keysheat insulationP17/76thermocouplesResistance heatingP19/76Double Channel Air Cooling SystemThe fixed vertical shearP20/76The tie rod housings and the casings bearing seats Die stack locking devicebladeScrew adjustment deviceAutomatic discard knockerpneumatic cylindernozzleslubrication tankDiscard detectionA photocell detectorbasketdie slideThe die carrierauxiliary shearP25/76robotized armhorizontally shifting saddleA mechanical stopa limit switchchainP26/76dummy blockmantlelinerP28/76container cleaning ringOne bushA safety mouthP29/76Fixed guiding systemthe safety Cover plateVideo camera systemManifold block and electrical system P30/76heat exchangershot water tankelectrical resistancesrollers with bearingsP32/76Axial piston pumpsClose loop controlProportional valveAmplifierelectronic control cardsP33/76safety valvesA high pressure pumpMain pumpsSlow speed pumpContainer sealing pumprespective coupling jointsInductive pump swivel angler transducer P34/76Damping bearings for shock absorption HP control valvesHP pumpsFilterning pumpoil cooling systemP35/76clogging gaugeOn/off valveP36/76Anti-dust filtersoil level indicatorOil level transducerTemperature transducerP37/76Manifold with circulating valves for the HP axial piston pumps change-over valvesOne manifold for stem movement controlOne manifold for main cylinders controlOne manifold for side cylinders controlOne Manifold for shear controlOne manifold for die slide controlOne manifolds for Container controlOne manifolds for the pre-filling valvesolenoid valvesLED indicatorP39/76Variable Delivery pumpOn board LP and HP pipingP40/76pipe clampsflangesjunction blocksP41/76three-pole circuit breakerVoltage and current measuring equipmentSingle-phase AC control transformer3-pole on-load isolator switchfuses/automatic circuit breakerSoft startercontactor with thermal relayP44/76Ampere meterP45/76I/O interfacenetwork interfaceSpare memoryP46/76Linear transducerProximity switchP47/76Photocelloptical sensorExtrusion press Control deskKey locksMushroom buttonKeyboardsHMI systemdedicated selector, andilluminated pushbuttonlamp indicationP48/76Local control pulpitmonitorHuman machine interfaceCPUHard diskCaseP50/76Special cablesCables trayEMERGENCY OFF Pushbuttons P51/76actuatorscontrol boxesP63/76CurvesInterlock挤压机液压回路控制系统挤压筒出料孔模具组件主泵框架附件低速泵挤压筒密封泵辅泵过滤泵油到水热交换器液压阀组预充阀油箱电机铝锭装载机前梁液压缸模座挤压垫前梁张立柱套筒后梁前梁螺母液压千斤顶主梁变量主泵比例阀高压泵安全阀低速泵主柱塞挤压筒支撑压余剪侧缸压余剪刀片压余锤模具组液压缸变量泵低速泵轴向泵滤网油箱加热电阻主泵电机辅泵电机低速泵电机冷却泵电机密封泵电机活动横梁挤压筒滑移液压缸模具锁紧装置刀片润滑系统模具更换站压余检测挤压垫润滑系统润滑系统工具挤压机出口保护系统水冷装置（仅提供设计）高压回路低压回路冷却系统过滤系统高压控制 （阀组）高低压管道电机进线主电机启动辅助电机启动加热器电路模具加热器电路挤压控制的PLC 系统自动化元件电源控制卡传感器设备配件挤压机操控台本地控制站接线盒（远程I/O)和传感器 接口人机界面电机电缆安全继电器挤压机PLC控制系统挤压杆张立柱挤压机机座支撑框架标准预埋件螺栓螺母有张力柱套筒主缸长青铜套主柱塞侧缸活动横梁方形衬套平板导位滑块挤压杆压力环滑动横移油缸挤压杆锁紧装置连接套挤压杆锁紧环双动侧液压缸挤压筒的中心销隔热材料热电偶电阻加热元件双通道空冷系统垂直布置的固定式剪张力柱套支撑座模座锁紧装置刀片螺栓调节装置自动压余打落器气动缸喷嘴润滑缸压余检测光电检测元件压余筐模具滑块模具套辅助剪机械手水平滑动鞍座机械挡块限位开关拖链挤压垫外套内衬挤压筒清洁环剔除套安全出口固定导向系统安全挡板视频导向系统阀块和电气系统热交换器热水箱电阻丝带轴承的辊道轴向柱塞泵闭环控制比例阀放大器电控卡安全阀高压泵主泵低速泵挤压筒密封泵联轴器电感式泵旋转角度传感器减震阻尼轴承高压控制阀高压泵过滤泵油冷系统堵塞测量仪表开关阀防尘过滤器油位指示器油位传感器温度传感器高压轴向柱塞泵循环阀块更换阀台挤压杆运动控制阀台主缸控制阀台侧缸控制阀台剪刀控制阀台模具移动控制阀台挤压筒控制阀台预充阀阀台电磁阀LED 指示灯变量泵随机高低压管线管夹法兰连接块三极断路开关电压和电流测量装置单相AC控制变压器三极带负荷隔离开关熔断器/自动断路器软启动带继电器的接触器电流表I/O 接口网络接口备用存储器线性传感器接近开关光电管光电传感器挤压机操控台键锁开关蘑菇头开关键盘HMI 系统专用选择器发光按钮指示灯本地控制站人机界面硬盘机箱特殊电缆电缆槽事故急停按钮执行器控制箱曲线图联锁。
ADC10154CIWM资料
ADC10154/ADC1015810-Bit Plus Sign 4µs ADCs with 4-or 8-Channel MUX,Track/Hold and ReferenceGeneral DescriptionThe ADC10154and ADC10158are CMOS 10-bit plus sign successive approximation A/D converters with versatile ana-log input multiplexers,track/hold function and a 2.5V band-gap reference.The 4-channel or 8-channel multiplex-ers can be software configured for single-ended,differential or pseudo-differential modes of operation.The input track/hold is implemented using a capacitive array and sampled-data comparator.Resolution can be programmed to be 8-bit,8-bit plus sign,10-bit or 10-bit plus sign.Lower-resolution conversions can be performed faster.The variable resolution output data word is read in two bytes,and can be formatted left justified or right justified,high byte first.Applicationsn Process control n Instrumentation n Test equipmentFeaturesn 4-or 8-channel configurable multiplexer n Analog input track/hold functionn 0V to 5V analog input range with single +5V power supplyn −5V to +5V analog input voltage range with ±5V suppliesn Fully tested in unipolar (single +5V supply)and bipolar (dual ±5V supplies)operationn Programmable resolution/speed and output data format n Ratiometric or Absolute voltage reference operation n No zero or full scale adjustment required n No missing codes over temperature n Easy microprocessor interfaceKey Specificationsn Resolution10-bit plus sign n Integral linearity error±1LSB (max)n Unipolar power dissipation33mW (max)n Conversion time (10-bit +sign) 4.4µs (max)n Conversion time (8-bit)3.2µs (max)n Sampling rate (10-bit +sign)166kHz n Sampling rate (8-bit)207kHznBand-gap reference2.5V ±2.0%(max)ADC10158Simplified Block DiagramTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS011225-1November 1999ADC10154/ADC1015810-Bit Plus Sign 4µs ADCs with 4-or 8-Channel MUX,Track/Hold and Reference©1999National Semiconductor Corporation Connection DiagramsPin DescriptionsAV +This is the positive analog supply.This pin should be bypassed with a 0.1µF ceramic ca-pacitor and a 10µF tantalum capacitor to the system analog ground.DV +This is the positive digital supply.This supply pin also needs to be bypassed with 0.1µF ce-ramic and 10µF tantalum capacitors to the system digital ground.AV +and DV +should be bypassed separately and tied to same power supply.DGND This is the digital ground.All logic levels are re-ferred to this ground.V −This is the negative analog supply.For unipolar operation this pin may be tied to the system analog ground or to a negative supply source.It should not go above DGND by more than 50mV.When bipolar operation is required,the voltage on this pin will limit the analog input’s negative voltage level.In bipolar operation this supply pin needs to be bypassed with 0.1µF ceramic and 10µF tantalum capacitors to the system analog ground.V REF +,V REF −These are the positive and negative reference inputs.The voltage difference between V REF +and V REF −will set the analog input voltage span.V REF OutThis is the internal band-gap voltage reference output.For proper operation of the voltage ref-erence,this pin needs to be bypassed with a 330µF tantalum or electrolytic capacitor.CSThis is the chip select input.When a logic low is applied to this pin the WR and RD pins are enabled.RDThis is the read control input.When a logic low is applied to this pin the digital outputs are en-abled and the INT output is reset high.WRThis is the write control input.The rising edge of the signal applied to this pin selects the mul-tiplexer channel and initiates a conversion.INTThis is the interrupt output.A logic low at this output indicates the completion of a conver-sion.CLK This is the clock input.The clock frequency di-rectly controls the duration of the conversiontime (for example,in the 10-bit bipolar mode t C =22/f CLK )and the acquisition time (t A =6/f CLK ).DB0(MA0)–DB7(L/R)These are the digital data inputs/outputs.DB0is the least significant bit of the digital outputword;DB7is the most significant bit in the digi-tal output word (see the Output Data Configu-ration table).MA0through MA4are the digital inputs for the multiplexer channel selection (see the Multiplexer Addressing tables).U/S (Unsigned/Signed),8/10,(8/10-bit resolution)and L/R (Left/Right justification)are the digital input bits that set the A/D’s output word format and resolution (see the Output Data Configura-tion table).The conversion time is modified by the chosen resolution (see Electrical AC Char-acteristics table).The lower the resolution,the faster the conversion will be.CH0–CH7These are the analog input multiplexer chan-nels.They can be configured as single-ended inputs,differential input pairs,or pseudo-differential inputs (see the Multiplexer Addressing tables for the input polarity assignments).Dual-in-Line and SO PackagesDS011225-2Top ViewOrder Number ADC10154NS Package Number M24BDual-in-Line and SO Packages 2Absolute Maximum Ratings(Notes1,3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Positive Supply Voltage(V+=AV+=DV+) 6.5V Negative Supply Voltage(V−)−6.5V Total Supply Voltage(V+−V−)13V Total Reference Voltage(V REF+−V REF−) 6.6V Voltage at Inputs andOutputs V−−0.3V to V++0.3V Input Current at Any Pin(Note4)±5mA Package Input Current(Note4)±20mA Package Dissipation atT A=25˚C(Note5)500mW ESD Susceptibility(Note6)2000V Soldering InformationN Packages(10Sec)260˚C J Packages(10Sec)300˚C SO Package(Note7):Vapor Phase(60Sec)215˚C Infrared(15Sec)220˚C Storage TemperatureCeramic DIP PackagesPlastic DIP and SO Packages−65˚C to+150˚C−40˚C to+150˚C Operating Ratings(Notes2,3)Temperature Range T MIN≤T A≤T MAX ADC10154CIWM,ADC10158CIN,ADC10158CIWM−40˚C≤T A≤+85˚C Positive SupplyVoltage(V+=AV+=DV+) 4.5V DC to5.5V DC Unipolar NegativeSupply Voltage(V−)DGND Bipolar NegativeSupply Voltage(V−)−4.5V to−5.5V V+−V−11V V REF+AV++0.05V DC to V−−0.05V DC V REF−AV++0.05V DC to V−−0.05V DC V REF(V REF+−V REF−)0.5V DC to V+Electrical CharacteristicsThe following specifications apply for V+=AV+=DV+=+5.0V DC,V REF+=5.000V DC,V REF−=GND,V−=GND for unipo-lar operation or V−=−5.0V DC for bipolar operation,and f CLK=5.0MHz unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes8,9,12)Symbol Parameter Conditions Typical(Note10)CIN and CIWM Units(Limit) SuffixesLimits(Note11)UNIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSResolution10+Sign BitsUnipolar Integral V REF+=2.5V±0.5LSBLinearity Error V REF+=5.0V±1LSB(Max)Unipolar Full-Scale Error V REF+=2.5V±0.5LSBV REF+=5.0V±1.5LSB(Max) Unipolar Offset Error V REF+=2.5V±1LSBV REF+=5.0V±2LSB(Max) Unipolar Total Unadjusted V REF+=2.5V±1.5LSBError(Note13)V REF+=5.0V±2.5LSB(Max)Unipolar Power Supply V+=+5V±10%Sensitivity V REF+=4.5VOffset Error±0.25±1LSB(Max)Full-Scale Error±0.25±1LSB(Max) Integral Linearity Error±0.25LSBBIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSResolution10+Sign BitsBipolar Integral V REF+=5.0V±1LSB(Max)Linearity ErrorBipolar Full-Scale Error V REF+=5.0V±1.25LSB(Max)ADC10154/ADC101583Electrical Characteristics(Continued)The following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipo-lar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical (Note 10)CIN and CIWMUnits (Limit)Suffixes Limits (Note 11)BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSBipolar Negative Full-Scale V REF +=5.0VError with Positive-Full ±1.25LSB (Max)Scale Adjusted Bipolar Offset Error V REF +=5.0V ±2.5LSB (Max)Bipolar Total Unadjusted V REF +=5.0V±3LSB (Max)Error (Note 13)Bipolar Power Supply SensitivityOffset Error V +=+5V ±10%±0.5±2.5LSB (Max)Full-Scale Error V REF +=4.5V ±0.5±1.5LSB (Max)Integral Linearity Error±0.25LSB Offset Error V −=−5V ±10%±0.25±0.75LSB (Max)Full-Scale Error V REF +=4.5V±0.25±0.75LSB (Max)Integral Linearity Error±0.25LSBUNIPOLAR AND BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSMissing Codes 0DC Common Mode V IN +=V IN −Error (Note 14)=V IN whereBipolar +5.0V ≥V IN ≥−5.0V ±0.25±0.75LSB (Max)Unipolar+5.0V ≥V IN ≥0V ±0.25±0.5LSB (Max)R REF Reference Input Resistance 7 4.5k Ω(Max)9.5k Ω(Max)C REF Reference Input Capacitance 70pF V AI Analog Input Voltage (V ++0.05)V (Max)(V −−0.05)V (Min)C AIAnalog Input Capacitance 30pF Off Channel Leakage On Channel =5V−400−1000nA (Max)Current Off Channel =0V (Note 15)On Channel =0V 4001000nA (Max)Off Channel =5VElectrical CharacteristicsThe following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS S/(N+D)Unipolar Signal-to-Noise+f IN =10kHz,V IN =4.85V p–p60dB Distortion Ratio f IN =150kHz,V IN =4.85V p-p 58dB S/(N+D)Bipolar Signal-to-Noise+f IN =10kHz,V IN =±4.85V60dB Distortion Ratiof IN =150kHz,V IN =±4.85V58dBA D C 10154/A D C 10158 4Electrical Characteristics(Continued)The following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS−3dB Unipolar Full V IN =4.85V p–p200kHz Power Bandwidth −3dB Bipolar Full V IN =±4.85V200kHzPower BandwidthREFERENCE CHARACTERISTICS (Unipolar Operation V −=GND Only)VREFOut Reference Output Voltage 2.5±1% 2.5±2%V (Max)∆V REF /∆t VREFOut Temperature Coefficient 40ppm/˚C ∆V REF /∆I LLoad Regulation Sourcing 0mA ≤I L ≤+4mA 0.0030.1%/mA (Max)Sinking0mA ≥I L ≥−1mA 0.20.6%/mA (Max)Line Regulation4.5V ≤V +≤5.5V 0.56mV (Max)I SCShort Circuit Current VREFOut =0V1425mA (Max)∆V REF /∆t Long-Term Stability 200ppm/1kHrt SU Start-Up TimeC L =330µF 20msDIGITAL AND DC CHARACTERISTICSV IN(1)Logical “1”Input Voltage V +=5.5V2.0V (Min)V IN(0)Logical “0”Input Voltage V +=4.5V 0.8V (Max)I IN(1)Logical “1”Input Current V IN =5.0V 0.005 2.5µA (Max)I IN(0)Logical “0”Input Current V IN =0V −0.005−2.5µA (Max)V OUT(1)Logical “1”Output VoltageV +=4.5V:I OUT =−360µA 2.4V (Min)I OUT =−10µA4.25V (Min)V OUT(0)Logical “0”Output Voltage V +=4.5V 0.4V (Max)I OUT =1.6mA I OUT TRI-STATE ®Output Current V OUT =0V−0.01−3µA (Max)V OUT =5V 0.013µA (Max)+I SC Output Short Circuit Source Current V OUT =0V −40−10mA (Min)−I SC Output Short Circuit V OUT =DV +3010mA (Min)Sink CurrentDI+Digital Supply Current CS =HIGH0.752mA (Max)CS =HIGH,f CLK =0Hz 0.15mA (Max)AI +Analog Supply Current CS =HIGH3 4.5mA (Max)CS =HIGH,f CLK =0Hz 3mA (Max)I−Negative Supply Current CS =HIGH3.54.5mA (Max)CS =HIGH,f CLK =0Hz 3.5mA (Max)I REFReference Input CurrentV REF +=5V0.71.1mA (Max)ADC10154/ADC101585Electrical CharacteristicsThe following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 16)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)AC CHARACTERISTICS f CLKClock Frequency 8 5.0MHz (Max)10kHz (Min)Clock Duty Cycle20%(Min)80%(Max)t CConversion 8-Bit Unipolar Mode161/f CLK Timef CLK=5.0MHz3.2µs (Max)8-Bit Bipolar Mode181/f CLK f CLK =5.0MHz3.6µs (Max)10-Bit Unipolar Mode201/f CLK f CLK =5.0MHz4.0µs (Max)10-Bit Bipolar Mode221/f CLK f CLK =5.0MHz4.4µs (Max)t A Acquisition Time61/f CLK f CLK =5.0MHz1.2µs t CR Delay between Falling Edge of 05ns (Min)CS and Falling Edge of RD t RC Delay betwee Rising Edge 05ns (Min)RD and Rising Edge of CS t CW Delay between Falling Edge 05ns (Min)of CS and Falling Edge of WR t WC Delay between Rising Edge 05ns (Min)of WR and Rising Edge of CS t RW Delay between Falling Edge 05ns (Min)of RD and Falling Edge of WR t W(WR)WR Pulse Width2550ns (Min)t WS WR High to CLK ÷2Low Set-Up Time 5ns (Max)t DS Data Set-Up Time 615ns (Max)t DH Data Hold Time 05ns (Max)t WR Delay from Rising Edge 05ns (Min)of WR to Rising Edge RD t ACC Access Time (Delay from Falling C L =100pF2545ns (Max)Edge of RD to Output Data Valid)t WI ,t RI Delay from Falling Edge C L =100pF2540ns (Max)of WR or RD to Reset of INT t INTL Delay from Falling Edge of CLK ÷2to Falling Edge of INT40ns t 1H ,t 0H TRI-STATE Control (Delay from C L =10pF,R L =1k Ω2035ns (Max)Rising Edge of RD to Hi-Z State)t RR Delay between Successive 2550ns (Min)RD Pulsest PDelay between Last Rising Edge of RD and the Next Falling 2050ns (Min)Edge of WRC IN Capacitance of Logic Inputs 5pF C OUTCapacitance of Logic Outputs5pFNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.A D C 10154/A D C 10158 6Electrical Characteristics(Continued)Note 2:Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may de-grade when the device is not operated under the listed test conditions.Note 3:All voltages are measured with respect to GND,unless otherwise specified.Note 4:When the input voltage (V IN )at any pin exceeds the power supplies (V IN <V −or V IN >AV +or DV +),the current at that pin should be limited to 5mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four.Note 5:The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax ,θJA and the ambient temperature,T A .The maximum allowable power dissipation at any temperature is P D =(T Jmax −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For this device,T Jmax =150˚C.The typical thermal resistance (θJA )of these parts when board mounted follow:ADC10154with BIN and CIN suffixes 65˚C/W,ADC10154with BIJ,CIJ and CMJ suffixes 49˚C/W,ADC10154with BIWM and CIWM suffixes 72˚C/W,ADC10158with BIN and CIN suffixes 59˚C/W,ADC10158with BIJ,CIJ,and CMJ suffixes 46˚C/W,ADC10158with BIWM and CIWM suffixes 68˚C/W.Note 6:Human body model,100pF capacitor discharged through a 1.5k Ωresistor.Note 7:See AN-450“Surface Mounting Methods and Their Effect on Product Reliability”or the section titled “Surface Mount”found in any post-1986National Semi-conductor Linear Data Book for other methods of soldering surface mount devices.Note 8:Two on-chip diodes are tied to each analog input as shown below.They will forward-conduct for analog input voltages one diode drop below V −supply or one diode drop greater than V +supply.Be careful during testing at low V +levels (4.5V),as high level analog inputs (5V)can cause an input diode to conduct,es-pecially at elevated temperatures,which will cause errors for analog inputs near full-scale.The specification allows 50mV forward bias of either diode;this means that as long as the analog V IN does not exceed the supply voltage by more than 50mV,the output code will be correct.Exceeding this range on an unselected chan-nel will corrupt the reading of a selected channel.This means that if AV +and DV +are minimum (4.5V DC )and V −is a maximum (−4.5V DC )full scale must be ≤±4.55V DC .Note 9:A diode exists between AV +and DV +as shown below.Note 10:Typicals are at T J =T A =25˚C and represent most likely parametric norm.Note 11:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 12:One LSB is referenced to 10bits of resolution.Note 13:Total unadjusted error includes offset,full-scale,linearity,multiplexer,and hold step errors.Note 14:For DC Common Mode Error the only specification that is measured is offset error.Note 15:Channel leakage current is measured after the channel selection.Note 16:All the timing specifications are tested at the TTL logic levels,V IL =0.8V for a falling edge and V IH =2.0V for a rising.DS011225-4DS011225-5To guarantee accuracy,it is required that the AV +and DV +be connected together to a power supply with separate bypass filter at each V +pin.ADC10154/ADC101587Electrical Characteristics(Continued)Ordering InformationIndustrial −40˚C ≤T A ≤85˚C Package ADC10154CIWM M24B ADC10158CIN N28B ADC10158CIWMM28BDS011225-6FIGURE 1.Transfer CharacteristicDS011225-7FIGURE 2.Simplified Error Curve vs Output CodeA D C 10154/A D C 10158 8Typical Converter Performance CharacteristicsTotal Positive SupplyCurrent(DI++AI+)vs TemperatureDS011225-27Total Positive PowerSupply Current(DI++AI+)vs Clock FrequencyDS011225-28Offset Errorvs TemperatureDS011225-29Offset Error vsReference VoltageDS011225-30Linearity Errorvs TemperatureDS011225-31Linearity Error vsReference VoltageDS011225-32Linearity Error vsClock FrequencyDS011225-33Spectral Response with50kHz Sine WaveDS011225-3410-Bit UnsignedSignal-to-Noise+THD Ratiovs Input Signal LevelDS011225-35ADC10154/ADC101589Typical Reference Performance CharacteristicsLeakage Current Test CircuitLoad RegulationDS011225-36Line Regulation (3Typical Parts)DS011225-37Output Drift vs Temperature (3Typical Parts)DS011225-38AvailableOutput Current vs Supply VoltageDS011225-39DS011225-10A D C 10154/A D C 10158 10TRI-STATE Test Circuits and WaveformsTiming DiagramsDS011225-11DS011225-12DS011225-13DS011225-14DS011225-15DIAGRAM 1.Starting a Conversion with New MUX Channel and Output ConfigurationADC10154/ADC1015811Timing Diagrams(Continued)DS011225-16DIAGRAM 2.Starting a Conversion without Changing the MUX Channel or Output ConfigurationDS011225-17DIAGRAM 3.Reading the Conversion ResultA D C 10154/A D C 10158 12Multiplexer Addressing and Output Data Configuration TablesTABLE1.ADC10154and ADC10158Output Data ConfigurationOutput Data Format Control Input Data Bus Output AssignmentResolution Data8/10U/S L/R DB7DB6DB5DB4DB3DB2DB1DB010-Bits+Sign Right-Justified L L L Sign Sign Sign Sign Sign Sign MSB9First Byte Read8765432LSB Second Byte Read10-Bits+Sign Left-Justified L L H Sign MSB987654First Byte Read32LSB L L L L L Second Byte Read10-Bits Right-Justified L H L L L L L L L MSB9First Byte Read8765432LSB Second Byte Read10-Bits Left-Justified L H H MSB9876543First Byte Read2LSB L L L L L L Second Byte Read8-Bits+Sign Right-Justified H L L Sign Sign Sign Sign Sign Sign Sign Sign First Byte ReadMSB765432LSB Second Byte Read8-Bits+Sign Left-Justified H L H Sign MSB765432First Byte ReadLSB L L L L L L L Second Byte Read8-Bits Right-Justified H H L L L L L L L L L First Byte ReadMSB765432LSB Second Byte Read8-Bits Left-Justified H H H MSB765432LSB First Byte ReadL L L L L L L L Second Byte ReadTABLE2.ADC10158Multiplexer AddressingMUX Address CS WR RD Channel Number MUXModeMA4MA3MA2MA1MA0CH0CH1CH2CH3CH4CH5CH6CH7V REF−X L L L L L H+−X L L L H L H−+X L L H L L H+−X L L H H L L H−+DifferentialX L H L L L H+−X L H L H L H−+X L H H L L H+−X L H H H L H−+L H L L L L H+−L H L L H L H+−L H L H L L H+−L H L H H L L H+−Single-EndedL H H L L L H+−L H H L H L H+−L H H H L L H+−L H H H H L H+−H H L L L L H+−H H L L H L H+−H H L H L L H+−H H L H H L L H+−Pseudo-DifferentialH H H L L L H+−H H H L H L H+−H H H H L L H+−X X X X X L L L Previous Channel ConfigurationADC10154/ADC1015813Multiplexer Addressing and Output Data Configuration Tables(Continued)TABLE 3.ADC10154Multiplexer AddressingMUX AddressCS WR RDChannel Number MUX Mode MA4MA3MA2MA1MA0CH0CH1CH2CH3V REF−X X L L L L H +−X X L L H L LH −+DifferentialX X L H L L H +−X X L H H L H −+X L H L L L H +−X L H L H L L H +−Single-EndedX L H H L L H +−X L H H H L H +−X H H L L L H +−X H H L H L L H +−Pseudo-DifferentialX H H H L L H +−XXXXXLL LPrevious Channel ConfigurationA D C 10154/A D C 10158 14Detailed Block DiagramD S 011225-18ADC10154/ADC10158151.0Functional DescriptionThe ADC10154and ADC10158use successive approxima-tion to digitize an analog input voltage.Additional logic has been incorporated in the devices to allow for the programma-bility of the resolution,conversion time and digital output for-mat.A capacitive array and a resistive ladder structure are used in the DAC portion of the A/D converters.The structure of the DAC allows a very simple switching scheme to provide a very versatile analog input multiplexer.Also,inherent in this structure is a sample/hold.A 2.5V CMOS band-gap ref-erence is also provided on the ADC10154and ADC10158.1.1DIGITAL INTERFACEThe ADC10154and ADC10158have eight digital outputs (DB0–DB8)and can be easily interfaced to an 8-bit data bus.Taking CS and WR low simultaneously will strobe the data word on the data-bus into the input latch.This word will be decoded to determine the multiplexer channel selection,the A/D conversion resolution and the output data format.The following table shows the input word data-bit assign-ment.DB0through DB4are assigned to the multiplexer address data bits zero through four (MA0–MA4).Tables 2,3describe the multiplexer address assignment.DB5selects unsigned or signed (U/S)operation.DB6selects 8-or 10-bit resolu-tion.DB7selects left or right justification of the output data.Refer to Table 1for the effect the Control Input Data has on the digital output word.The conversion process is started by the rising edge of WR,which sets the “start conversion”bit inside the ADC.If this bit is set,the converter will start acquiring the input voltage on the next falling edge of the internal CLK ÷2signal.The acqui-sition period is 3CLK ÷2periods,or 6CLK periods.Immedi-ately after the acquisition period the input signal is held and the actual conversion begins.The number of clocks required for a conversion is given in the following table:Conversion Type CLK ÷2CLK CyclesCycles (N)8-Bit 8168-Bit +Sign 91810-Bit 102010-Bit +Sign1122Since the CLK ÷2signal is internal to the ADC,it is initially impossible to know which falling edge of CLK corresponds to the falling edge of CLK ÷2.For the first conversion,the rising edge of WR should occur at least t WS ns before any falling edge of CLK.If this edge happens to be on the rising edge of CLK ÷2,this will add 2CLK cycles to the total conversion time.The phase of the CLK ÷2signal can be determined at the end of the first conversion,when INT goes low.INT al-ways goes low on the falling edge of the CLK ÷2signal.From the first falling edge of INT onward,every other falling edge of CLK will correspond to the falling edge of CLK ÷2.With the phase of CLK ÷2now known,the conversion time can be minimized by taking WR high at least t WS ns before the fall-ing edge of CLK ÷2.Upon completion of the conversion,INT goes low to signal the A/D conversion result is ready to be read.Taking CS and RD low will enable the digital output buffer and put byte 1of the conversion result on DB0through DB7.The falling edge of RD resets the INT output high.Taking CS and RD low a second time will put byte 2of the conversion result on DB7–DB0.Table 1defines the DB0–DB7assignment for dif-ferent Control Input Data.The second read does not have to be completed before a new conversion is started.Taking CS,WR and RD low simultaneously will start a con-version without changing the multiplexer channel assign-ment or output configuration and resolution.The timing dia-gram in Figure 3shows the sequence of events that implement this function.Refer to Diagrams 1,2,and 3in the Timing Diagrams section for the timing constraints that must be met.DS011225-44DS011225-19FIGURE 3.Starting a Conversion without Updating the Channel Configuration,Resolution,or Data FormatA D C 10154/A D C 10158 161.0Functional Description(Continued)Digital Interface Hints:•Reads and writes can be completely asynchronous to CLK.•In addition to the timing indicated in Diagrams1–3,CS can be tied low permanently or taken low for entire con-versions,eliminating all the CS guardbands(t CR,t RC, t CW,t WC).•If CS is used as shown in Diagrams1–-3,the CS guard-bands(t CR,t RC,t CW,t WC)between CS and the RD and WR signals can safely be ignored as long as the follow-ing two conditions are met:1)When initiating a write,CS and WR must be simulta-neously low for at least t W(WR)ns(see Diagram1).The “start”conversion”bit will be set on the rising edge of WR or CS,whichever is first.2)When reading data,understand that data will not be validuntil t ACC ns after both CS and RD go low.The output data will enter TRI-STATE t1H ns or t0H ns after either CS or RD goes high(see Diagrams2and3).1.2ARCHITECTUREBefore a conversion is started,during the analog input sam-pling period,the sampled data comparator is zeroed.As the comparator is being zeroed the channel assigned to be the positive input is connected to the A/D’s input capacitor.(See the Digital Interface section for a description of the assign-ment procedure.)This charges the input32C capacitor of the DAC to the positive analog input voltage.The switches shown in the DAC portion of the detailed block diagram are set for this zeroing/acquisition period.The voltage at the in-put and output of the comparator are at equilibrium at this point in time.When the conversion is started the comparator feedback switches are opened and the32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens a fixed amount of charge is trapped on the common plates of the capacitors. The voltage at the input of the comparator moves away from equilibrium when the32C capacitor is switched to the as-signed negative input voltage,causing the output of the com-parator to go high(“1”)or low(“0”).The SAR next goes through an algorithm,controlled by the output state of the comparator,that redistributes the charge on the capacitor ar-ray by switching the voltage on one side of the capacitors in the array.The objective of the SAR algorithm is to return the voltage at the input of the comparator as close as possible to equilibrium.The switch position information at the completion of the suc-cessive approximation routine is a direct representation ofthe digital output.This information is then manipulated by theDigital Output decoder to the programmed format.The refor-matted data is then available to be strobed onto the data bus(DB0–DB7)via the digital output buffers by taking CS andRD low.2.0Applications Information2.1MULTIPLEXER CONFIGURATIONThe design of these converters utilizes a sampled-data com-parator structure which allows a differential analog input tobe converted by the successive approximation routine.The actual voltage converted is always the difference be-tween an assigned“+”input terminal and a“−”input terminal.The polarity of each input terminal or pair of input terminalsbeing converted indicates which line the converter expectsto be the most positive.If the assigned“+”input is less thanthe“−”input the converter responds with an all zeros outputcode when configured for unsigned operation.When config-ured for signed operation the A/D responds with the appro-priate output digital code.A unique input multiplexing scheme has been utilized to pro-vide multiple analog channels.The input channels can besoftware configured into three modes:differential,single-ended,or pseudo-differential.Figure4shows thethree modes using the4-channel MUX of the ADC10154.The eight inputs of the ADC10158can also be configured inany of the three modes.The single-ended mode hasCH0–CH3assigned as the positive input with the negativeinput being the V REF−of the device.In the differential mode,the ADC10154channel inputs are grouped in pairs,CH0with CH1and CH2with CH3.The polarity assignment ofeach channel in the pair is interchangeable.Finally,in thepseudo-differential mode CH0–CH2are positive inputs re-ferred to CH3which is now a pseudo-ground.Thispseudo-ground input can be set to any potential within the in-put common-mode range of the converter.The analog signalconditioning required in transducer-based data acquisitionsystems is significantly simplified with this type of input flex-ibility.One converter package can now handleground-referred inputs and true differential inputs as well assignals referred to a specific voltage.The analog input voltages for each channel can range from50mV below V−(typically ground for unipolar operation or−5V for bipolar operation)to50mV above V+=DV+=AV+(typically5V)without degrading conversion accuracy.If thevoltage on an unselected channel exceeds these limits itmay corrupt the reading of the selected channel.ADC10154/ADC1015817。
国家电子NI 9227 四通道、五臂、24位、同时、渠道间隔离模拟输入模块操作指南和规格说明书
Caution Ensure that hazardous voltage wiring is performed only by qualified personnel adhering to local electrical standards. Caution Do not mix hazardous voltage circuits and human-accessible circuits on the same module. Caution Make sure that devices and circuits connected to the module are properly insulated from human contact.
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2 | | NI 9227 Operating Instructions and Specifications
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Figure 5. Input Circuitry for One Channel of the NI 9227
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NI 9227
NI 9227 Operating Instructions and Specifications | © National Instruments | 9
Related Information
Digital Signal Processing
Digital Signal Processing Digital Signal Processing (DSP) is a field of study that deals with the manipulation of signals in the digital domain. It is an essential aspect of modern electronics, as most signals in the real world are analog in nature, and must be converted to digital signals before they can be processed by computers. DSP is used in a wide range of applications, including audio and video processing, telecommunications, control systems, and biomedical engineering. In this essay, we will explore the various aspects of DSP, including its history, principles, and applications. The history of DSP can be traced back to the early days of computing, when researchers first began to explore the possibilities of digital signal processing. In the 1960s, digital signal processing techniques were first developed for use in military applications, such as radar and sonar systems. These early systems were based on simple algorithms, such as the Fast Fourier Transform (FFT), which allowed signals to be analyzed and manipulated in the frequency domain. Over time, these techniques were refined and expanded, and DSP became an essential part of modern electronics. One of the key principles of DSP is the concept of sampling. In order to process analog signals in the digital domain, they must first be sampled at regular intervals. This process involves taking discrete measurements of the signal at specific points in time, and then converting these measurements into digital values. The frequency at which the signal is sampled is known as the sampling rate, and it is an important parameter that affects the quality of the digital signal. Higher sampling rates generally result in better quality signals, but they also require more processing power and storage capacity. Another important principle of DSP is the use of digital filters. These filters are used to manipulate the frequency content of a signal, and they can be used to remove unwanted noise or enhance specific features of the signal. There are many different types of digital filters, including low-pass, high-pass, band-pass, and notch filters, each of which is designed to perform a specific function. Digital filters can be implemented using a variety of algorithms, including Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters. DSP has many applications in a wide range of fields. One of the most common applications of DSP is in audio processing, where it is used tomanipulate and enhance sound signals. DSP techniques can be used to remove unwanted noise from audio recordings, enhance the clarity of speech, and improve the overall quality of music recordings. DSP is also used in video processing, where it is used to enhance the quality of images and video streams. In telecommunications, DSP is used to encode and decode digital signals, and it is an essential component of modern digital communication systems. Another important application of DSP is in control systems, where it is used to manipulate signals to control the behavior of machines and systems. DSP techniques can be used to control the speed of motors, adjust the position of robotic arms, and regulate the temperature of industrial processes. In biomedical engineering, DSP is used to analyze and manipulate signals from medical devices, such as ECG machines and MRI scanners. DSP techniques can be used to detect abnormalities in medical signals, enhance the quality of medical images, and improve the accuracy of medical diagnoses. In conclusion, Digital Signal Processing is an essential aspect of modern electronics, with applications in a wide range of fields. Its principles are based on the manipulation of signals in the digital domain, using techniques such as sampling and digital filtering. DSP has a rich history, dating back to the early days of computing, and it has evolved to become a vital component of modern technology. Its applications are diverse, including audio and video processing, telecommunications, control systems, and biomedical engineering. As technology continues to advance, DSP will continue to play a critical role in shaping the future of electronics and communications.。
Z90348中文资料
FEATURESs Part ROM RAM Speed Number(Word)(Word)(MHz)Z9034901K12Z9034801K12s144-Pin Grid Array (PGA) Package (Z90349) 100-Pin Quad Flat Pack (QFP) Package (Z90348) s 4.5- to 5.5-Volt Operating Ranges Z89C00 RISC Processor Cores0°C to +70°C Temperature Range GENERAL DESCRIPTION P RELIMINARYC USTOMER P ROCUREMENT S PECIFICATIONZ90349/348DIGITAL TELEVISION CONTROLLER IN-CIRCUIT EMULATOR (ICE) DEVICEThe Z90349 and Z90348 are ROMless versions of the Z89300 family of Zilog's Digital Television Controllers designed for use in emulators and development boards to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities.The powerful Z89C00 RISC processor core allows users to control on-board peripheral functions and registers using the standard processor instruction set.In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters.The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set.Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industry-standard I2C port.Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibility of text by adding a right-sided shadow effect to the characters.Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports.Notes:All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below:Connection Circuit Device Power VCCVDD Ground GND VSSs Direct Closed Caption Decodings TV Tuner Serial Interfaces Customized Character Sets Character Control Modes Directly Controlled Receiver Functionss V-Chip DecodeGENERAL DESCRIPTION (Continued)Functional Block DiagramPIN DESCRIPTION144-Pin PGA Configuration100-Pin QFP ConfigurationPIN DESCRIPTION (Continued)Z90349/Z90348 Pin Identification Table Number Pin Name144-Pin100-Pin1P03D3522P02/I2CSSC C2533VCC B14gnd D25address12E354 6address11C155 7P0I/I2CSS0E256 8address10D157 9address9F358 10address8F259 11address7E160 12address6G261 13CVI/ADC0G362 14address5F163 15address4G16416VCC H217gnd H118address3H365 19LPF J366 20address2J16721address1K168 22address0J269 23IE K270 24R/W K371 25AGNDF L17226sys_clk L273 27EA0M174 28EA1N175 29EA2M276 30ADC5L37731P04/ADC4N278address19P1address18M3address17N332P05/ADC3N479 33gnd P334P00/ADC2P280 35int_bus0P436P17/ADC1N581 37int_bus1R382 38AGND P583 39int_bus2R440AVCC N68441int_bus3P685 42P0F/strans R586 43V3 (B)P78744VCC N745V2 (G)R688Number Pin Name144-Pin100-Pin 46V1 (R)R78947gnd P848Blank R89049HSync N89150int_bus4N951VSync R99252P12/I2CMSD2R109353int_bus5P954P11/I2CMSC2P109455int_bus6N109556P0E R119657int_bus7P119758I2CMSD1R129859VCCR1360I2CMSC1P129961int_bus8N1110062/Reset P131address 16R14address 15N12XR/W N13/XOE P1463XTAL1P15264XTAL2L13365int_bus9N1566gnd L1467data15M15468data11X13569GND K14670data10L15771data14J14872data13J13973data12X151074_pabus J1511*75VCC/VDDH141276_romless H1513*77data9H131478data8G131579data7G151680stopwdt F1581AGNDX G141782single-stop F1483data6F131884data5E151985data4E142086data3D152187PWM1C152288data2D142389data1E132490data0C142591V B15Number Pin Name144-Pin100-Pin 92PWM2D152693gnd C13P1A B14P1B A15PIC C1294PWM3B132795PWM4A142896PWM5B122997int_bus10C113098PWM6A133199int_bus11B1132 100P10/4<0>A1233 101int_bus12C1034 102P08/R<1>B1035 103VCC A11104P18/G<0>B936 105P13/G<1>C937 106gnd A10107P14/B<0>A938 108P15/B<1>B839 109int_bus13A8110P16/SCLK C840 111int_bus14C7112IRIN A741 113int_bus15A6114P0C B742 115P0B B643 116P0A C644 117P19A545 118P09B546119VCC A4120P0D A347 121address14B448 122P07/CSync C549 123address13B350 124P06/Cnter A551P1D C4P1E C3P1F B2V1, V2, V3 ANALOG OUTPUT Specifications V CC = 5.25 VV CC = 5.25 V Condition LimitOutput VoltageBit = 11 2.10 V ± 0.3 V Bit = 10 1.75 V ± 0.30 V Bit = 01 1.28 V ± 0.30 V Bit = 000.0Setting Time70% of DC Level, < 50 ns10pf LoadV1, V2, V3 ANALOG OUTPUT Specifications V CC = 4.75 VV CC = 4.75 V Condition LimitOutput VoltageBit = 11 1.90 V ± 0.30 V Bit = 10 1.60 V ± 0.30 V Bit = 01 1.20 V ± 0.30 V Bit = 000.0Setting Time70% of DC Level, < 50 ns10pf Load32K Oscillator Recommended Circuit560pF68pFABSOLUTE MAXIMUM RATINGSSymbol ParameterMin Max Units Conditions V CC Power Supply Voltage 0 7V V ID Input Voltage –0.3V CC +0.3 V Digital InputsV IA Input Voltage –0.3V CC +0.3 V Analog Inputs (A/D0...A/D4)V O Output Voltage–0.3V CC +0.3 V All Push-Pull Digital Output I OH Output Current High –10/–1a mA One Pin I OH Output Current High –100mA All Pins I OL Output Current Low 20/1b mA One Pin I OL Output Current Low 200mA All PinsT A Operating Temperature 070 °C T SStorage Temperature–65150°CDC CHARACTERISTICST A = 0°C to + 70°C; V CC = 4.5 V to + 5.5 V; F OSC = 32.768 KHzSymbol Parameter Min Max Typical Units ConditionsV IL Input Voltage Low 00.2 V CC 0.4V V IH Input Voltage High 0.6 V CCV CC 3.6V V OL Output Voltage Low 0.40.16V @ I OL = 1 mA V OH Output Voltage High V CC –0.9 4.75V @ I OL = 0.75 mA V XL Input Voltage XTAL1 Low 0.3 V CC 1.0V External Clock V XH Input Voltage XTAL1 HighV CC –2.0 3.5 V Generator Driven V HY Schmitt Hysteresis 3.00.75 0.5V On XTAL1 Input Pin I IR Reset Input Current150 90µA V RL = 0 V I IL Input Leakage –3.03.00.01µA @ 0 V and V CCI CC Supply Current 10060mA I CC1Supply Current 300 100µA Sleep Mode @ 32 KHz I CC2Supply Current405µAStop Mode Notes:a) 1 mA max. when output pad impedance is 600 Ω.b) 1 mA max. when output pad impedance is 600 Ω.Zilog’s products are not authorized for use as critical compo-nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform,when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.Zilog, Inc. 210 East Hacienda Ave.Campbell, CA 95008-6600Telephone (408) 370-8000Telex 910-338-7621FAX 408 370-8056Internet: © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer-chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document.Zilog, Inc. makes no commitment to update or keep current the information contained in this document.AC CHARACTERISTICST A = 0°C to + 70°C; V CC = 4.5 V to 5.5 V; F OSC = 32.768 KHzSymbol ParameterMin Max Typical Units NoteT P C Input Clock Period1610032µs T R C,T F C Clock Input Rise and Fall 12µs T D PORPower On Reset Delay0.81.2sDepends on Crystal AC CHARACTERISTICS*T A = 0°C to + 70°C; V CC = 4.5 V to 5.5 V; F OSC = 32.768 KHzSymbol ParameterMin Max Typical Units T W RES Power-On Reset Min. Width 5TPC µs T D H S H_Sync Incoming Signal Width 5.512.511µs T D V S V_Sync Incoming Signal Width0.15 1.5 1.0ms T D E S Time Delay Between Leading Edge –12+120µs of V_Sync and H_Sync in Even Field T D O S Time Delay Between Leading Edge 204432µs of H_Sync in Odd FieldT W HV SH_Sync/V_Sync Edge Width2.00.5µsNotes:All timing of the I 2C bus interface are defined by related specifications of the I 2C bus interface.。
Programmable high pass digital filter of analog si
专利名称：Programmable high pass digital filter of analog signal发明人：Carlos D. Cardon,Lawrence P. Griffone申请号：US05/600018申请日：19750729公开号：US04002988A公开日：19770111专利内容由知识产权出版社提供摘要：A novel circuit combination comprised of small scale integrated (SSI) and medium scale integrated (MSI) integrated circuits (IC) for the filtering and passing of a selected high band of passable frequencies and of a selected amplitude is disclosed. The novel circuit combination is a special-purpose high pass digital filter of a programmable low frequency limit that is determined by the sample time T. sub.S duration and the programmable low F.sub.L frequency of the passable analog signal frequency having a nominal carrier signal frequency F.sub.A. The analog signal is initially tested for a minimal amplitude and converted to a binary digital signal. The pulses of the binary digital signal are counted over the sample time T.sub.S. If the number of pulses N.sub.A counted, i.e., the analog signal frequency F.sub.A (where F.sub.A = N.sub. A /T.sub.S, similarly, any frequency F.sub.X = N.sub.X /T.sub.S), over the sample time T.sub.S is within the passable high band, i.e., passable (F.sub.L ≦F.sub.A), a first binary signal is generated. Alternatively, if the number of pulses N.sub.A counted over the sample time T.sub.S is without the passable high band, i.e., not passable (F.sub. L > F.sub.A), the first binary signal is not generated. The first binary signal is ANDed with the binary digital signal for gating out the binary digital signal to user equipment, while, alternatively, the absence of the firstbinary signal inhibits the gating of the binary digital signal to user equipment. Sample times continue throughout the detection-comparing operation to ensure a continuous filtering process.申请人：SPERRY RAND CORPORATION代理人：Kenneth T. Grace,Thomas J. Nikolai,Marshall M. Truex更多信息请下载全文后查看。
Digitally controlled SMALA
专利名称：Digitally controlled SMALA发明人：Bohn, Thomas,Wiegner, Dirk,Machinal, Robin申请号：EP09001272.5申请日：20090130公开号：EP2214305A1公开日：20100804专利内容由知识产权出版社提供专利附图：摘要：A method for operating a digital in - analogue out radio frequency amplifier,further referred to as DARFA (50), wherein a digital input signal (53) is processed in adigital signal processing unit, further referred to as DSP unit (51), generating a processed digital baseband signal (54) out of the digital input signal (53), wherein an analogue RFinput signal (24) with a non-constant envelope is generated out of the processed digital baseband signal (54), wherein the analogue RF input signal (24) is fed into an RF power amplifier (22) which generates an amplified analogue RF output signal (26) out of the analogue RF input signal (24), wherein the RF power amplifier (22) receives a supply voltage (27a) from a modulator unit (21), wherein the modulator unit (21) comprises a linear amplifier stage (33) and a switching amplifier stage (38), whose outputs (36, 37) are combined to one common modulator output (28) providing the supply voltage (27a) and supply current, and wherein the input (30) of the linear amplifier stage (33) is fed with an analogue input signal (29) corresponding to the envelope of the processed digital baseband signal (54), is characterized in that the switching amplifier stage (38) is controlled by means of a pulse width modulated signal (44) generated within the DSP unit (51), wherein the pulse width modulated signal (44) is derived digitally from the partially or completely processed digital baseband signal (54). The invention provides a method for operating a DARFA which allows a higher accuracy in the control of the RF power amplifier.申请人：Alcatel-Lucent Deutschland AG地址：Lorenzstrasse 10 70435 Stuttgart DE国籍：DE代理机构：Kohler Schmid Möbus更多信息请下载全文后查看。
AD5174
Single-Channel, 1024-Position, Digital Rheostatwith SPI Interface and 50-TP MemoryAD5174 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, N orwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.FEATURESSingle-channel, 1024-position resolution10 kΩ nominal resistance50-times programmable (50-TP) wiper memoryRheostat mode temperature coefficient: 35 ppm/°C2.7 V to 5.5 V single-supply operation±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operationsSPI-compatible interfaceWiper setting and memory readbackPower on refreshed from memoryResistor tolerance stored in memoryThin LFCSP 10-lead, 3 mm × 3 mm× 0.8 mm package Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package APPLICATIONSMechanical rheostat replacementsOp-amp: variable gain controlInstrumentation: gain, offset adjustmentProgrammable voltage-to-current conversions Programmable filters, delays, time constants Programmable power supplySensor calibrationFUNCTIONAL BLOCK DIAGRAMVSSAW SCLKDINSDOSYNC8718-1Figure 1.GENERAL DESCRIPTIONThe AD5174 is a single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. This device supports both dual-supply operation at ±2.5 V to ±2.75 V and single-supply operation at 2.7 V to 5.5 V and offers 50-times programmable (50-TP) memory. The AD5174 device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5174 does not require any external voltage supply to facili-tate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the resistance position (analogous to placing epoxy on a mechanical rheostat).The AD5174 is available in a 3 mm × 3mm 10-lead LFCSP package and in a 10-lead MSOP package. The part is guaranteed to operate over the extended industrial temperature range of−40°C to +125°C.AD5174Rev. B | Page 2 of 20TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Electrical Characteristics.............................................................3 Interface Timing Specifications..................................................4 Absolute Maximum Ratings............................................................6 Thermal Resistance......................................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Typical Performance Characteristics.............................................8 Test Circuits.....................................................................................11 Theory of Operation......................................................................12 Serial Data Interface...................................................................12 Shift Register...............................................................................12 RDAC Register............................................................................12 50-TP Memory Block................................................................12 Write Protection.........................................................................12 RDAC and 50-TP Read Operation..........................................13 Shutdown Mode.........................................................................14 Reset.............................................................................................14 SDO Pin and Daisy-Chain Operation.....................................15 RDAC Architecture....................................................................16 Programming the Variable Resistor.........................................16 EXT_CAP Capacitor..................................................................17 Terminal Voltage Operating Range.........................................17 Power-Up Sequence...................................................................17 Outline Dimensions.......................................................................18 Ordering Guide.. (18)REVISION HISTORY12/10—Rev. A to Rev. BChanges to SDO Pin Description...................................................7 Changes to SDO Pin and Daisy-Chain Operation Section.......15 7/10—Rev. 0 to Rev. AChanges to Daisy-Chain Operation Section including Changing Title to SDO Pin and Daisy-Chain Operation Section.............15 Added Table 11...............................................................................15 Changes to Ordering Guide..........................................................18 3/10—Revision 0: Initial VersionAD5174Rev. B | Page 3 of 20SPECIFICATIONSELECTRICAL CHARACTERISTICSV DD = 2.7 V to 5.5 V , V SS = 0 V; V DD = 2.5 V to 2.75 V , V SS = −2.5 V to −2.75 V; −40°C < T A < 125°C, unless otherwise noted.Table 1.Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution 10 BitsResistor Integral Nonlinearity 2, 3R-INL |V DD − V SS | = 3.6 V to 5.5 V −1 +1 LSB |V DD − V SS | = 3.3 V to 3.6 V −1 +1.5 LSB |V DD − V SS | = 2.7 V to 3.3 V −2.5 +2.5 LSBResistor Differential Nonlinearity 2R-DNL −1 +1 LSB Nominal Resistor Tolerance ±15 %Resistance Temperature Coefficient 4, 5Code = full scale 35 ppm/°C Wiper Resistance Code = zero scale 35 70 Ω RESISTOR TERMINALSTerminal Voltage Range 4, 6V TERM V SS V DD V Capacitance A 4 f = 1 MHz, measured to GND, code = half scale 90 pFCapacitance W 4f = 1 MHz, measured to GND, code = half scale 40 pF Common-Mode Leakage Current 4 V A = V W 50 nA DIGITAL INPUTSInput Logic 4igh V INH 2.0 V Low V INL 0.8 V Input Current I IN ±1 μAInput Capacitance 4C IN 5 pF DIGITAL OUTPUT Output Voltage 4 High V OH R PULL_UP = 2.2 kΩ to V DD V DD − 0.1 V Low V OL R PULL_UP = 2.2 kΩ to V DD V DD = 2.7 V to 5.5 V, V SS = 0 V 0.4 V V DD = 2.5 V to 2.75 V, V SS = −2.5 V to −2.75 V 0.6 V Tristate Leakage Current −1 +1 μAOutput Capacitance 45 pF POWER SUPPLIES Single-Supply Power Range V SS = 0 V 2.7 5.5 V Dual-Supply Power Range ±2.5 ±2.75 V Supply Current Positive I DD 1 μA Negative I SS −1 μA50-TP Store Current 4, 7Positive I DD_OTP_STORE 4 mA Negative I SS_OTP_STORE −4 mA 50-TP Read Current 4, 8 Positive I DD_OTP_READ 500 μA Negative I SS_OTP_READ −500 μA Power Dissipation 9 P DISS V IH = V DD or V IL = GND 5.5 μWPower Supply Rejection Ratio 4PSRR ΔV DD /ΔV SS = ±5 V ± 10% −50 −55 dBAD5174Rev. B | Page 4 of 20Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit DYNAMIC CHARACTERISTICS 4, 10 Bandwidth −3 dB, R AW = 5 kΩ, Terminal W, see Figure 24 700 kHz Total Harmonic Distortion V A = 1 V rms, f = 1 kHz, R AW = 5 kΩ −90 dB Resistor Noise Density R WB = 5 kΩ, T A = 25°C, f = 10 kHz 13 nV/√Hz1 Typical specifications represent average readings at 25°C, V DD = 5 V, and V SS = 0 V.2Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. 3The maximum current in each code is defined by I AW = (V DD − 1)/R AW . 4Guaranteed by design and not subject to production test. 5See Figure 9 for more details. 6Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 7Different from operating current; the supply current for the fuse program lasts approximately 55 ms. 8Different from operating current; the supply current for the fuse read lasts approximately 500 ns. 9P DISS is calculated from (I DD × V DD ) + (I SS × V SS ). 10All dynamic characteristics use V DD = +2.5 V, V SS = −2.5 V.INTERFACE TIMING SPECIFICATIONSV DD = 2.7 V to 5.5 V , V SS = 0 V; V DD = 2.5 V , V SS = −2.5 V; all specifications T MIN to T MAX , unless otherwise noted.1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V DD ) and timed from a voltage level of (V IL + V IH )/2. 2Maximum SCLK frequency is 50 MHz. 3Refer to t MEMORY_READ and t MEMORY_PROGRAM for memory commands operations. 4R PULL_UP = 2.2 kΩ to V DD with a capacitance load of 168 pF. 5Maximum time after V DD − V SS is equal to 2.5 V.AD5174Rev. B | Page 5 of 20Shift Register and Timing Diagrams08718-002Figure 2. Shift Register ContentSCLKSDODIN SYNC08718-003Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1SCLKSDODIN SYNC08718-004Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1AD5174Rev. B | Page 6 of 20ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted.Table 3.Parameter RatingV DD to GND –0.3 V to +7.0 VV SS to GND +0.3 V to −7.0 VV DD to V SS 7 VV A , V W to GND V SS − 0.3 V, V DD + 0.3 V Digital Input and Output Voltage to GND −0.3 V to V DD + 0.3 V EXT_CAP to V SS 7 VI A , I WPulsed 1 Frequency > 10 kHz ±6 mA/d 2 Frequency ≤ 10 kHz ±6 mA/√d 2Continuous ±6 mA Operating Temperature Range 3−40°C to +125°C Maximum Junction Temperature (T J Maximum)150°C Storage Temperature Range −65°C to +150°C Reflow SolderingPeak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (T J max − T A )/θJAStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these orany other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51 and the value isdependent on the test board and test environment.Table 4. Thermal ResistancePackage Type θJA 1 θJC Unit 10-Lead LFCSP 50 3 °C/W10-Lead MSOP 135 N/A °C/W1JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION1Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2Pulse duty factor. 3Includes programming of 50-TP memory.AD5174Rev. B | Page 7 of 20PIN CONFIGURATION AND FUNCTION DESCRIPTIONSV DDV A SDOSCLK EXT_CAP DIN GNDSYNC 08718-005SYNCV DD 1V SS 2A 3W 4SDO 1098SCLK 75EXT_CAP DIN 6GND*LEAVE FLOATING OR CONNECTED TO V SS .AD5174(EXPOSED PAD)*08718-103Figure 5. MSOP Pin Configuration Figure 6. LFCSP Pin ConfigurationAD5174Rev. B | Page 8 of 20TYPICAL PERFORMANCE CHARACTERISTICS0.8–0.6–0.4–0.200.20.40.601282563845126407688961023I N L (L S B )CODE (Decimal)08718-014Figure 7. R-INL vs. Code vs. Temperature0.4–0.3–0.2–0.100.10.20.301282563845126407688961023D N L (L S B )CODE (Decimal)08718-015Figure 8. R-DNL vs. Code vs. Temperature700600500400300200100001282563845126407688961023R H E O S T A T M O D E T E M P C O (p p m /°C )CODE (Decimal)08718-019Figure 9. Tempco ΔR WA /ΔT vs. Code00.20.40.60.81.0C U R R E N T (m A )VOLTAGE (V)0.51.01.52.02.53.03.54.04.55.05.508718-023Figure 10. Supply Current (I DD ) vs. Digital Input Voltage–500–400–300–200–1000100200300400500C U R R E N T (n A )TEMPERATURE (°C)–40–30–20–10020304050607080901001101008718-018Figure 11. Supply Current (I DD , I SS ) vs. Temperature70123456102385076593568051059534042517025585T H E O R E T I C A L l W A _M A X (m A)CODE (Decimal)08718-028Figure 12. Theoretical Maximum Current vs. CodeAD5174Rev. B | Page 9 of 2008718-031–50–45–35–40–30–25–20–15–10–50110M1M100k10k1k10010G A I N (d B )FREQUENCY (Hz)Figure 13. Bandwidth vs. Frequency vs. CodeT H D + N (d B )08718-039–120–100–80–60–40–20101001k 10k 100k FREQUENCY (Hz)1MFigure 14. THD + N vs. Frequency–100–80–60–40–200.0010.010.11T H D +N (d B )AMPLITUDE (V rms)08718-026Figure 15. THD + N vs. Amplitude–20–25–30–35–40–45–50–55–60101001M100k 10k 1k P S R R (d B )FREQUENCY (Hz)08718-024Figure 16. PSRR vs. Frequency45678V O L T A G E (V )TIME (Seconds)0.070.090.110.130.150.1708718-029Figure 17. V EXT_CAP Waveform While Writing Fuse20–70–60–50–40–30–20–10010–2420G L I T C H A M P L I T U D E (m V )TIME (µs)08718-102Figure 18. Maximum Glitch EnergyAD5174Rev. B | Page 10 of 201.0–1.5–1.0–0.50.5–106050403020100V O L T A G E (m V )TIME (µs)08718-1000.006–0.002–0.0010.0010.0020.0030.0040.0051000900800700600500400300200100∆R A W R E S I S T A N C E (%)OPERATION AT 150°C (Hours)08718-101Figure 19. Digital FeedthroughFigure 20. Long-Term Drift Accelerated Average by Burn-InTEST CIRCUITSFigure 21 to Figure 25 define the test conditions used in the Specifications section.08718-033Figure 21. Resistor Position Nonlinearity Error(Rheostat Operation; R-INL, R-DNL)08718-034R WA =V MSI WW =R WA 2CODE = 0x00Figure 22. Wiper Resistance∆V MS %∆V DD %V+ = V DD ±10%PSRR (dB) = 20 logPSS (%/%) =08718-035Figure 23. Power Supply Sensitivity (PSS, PSRR)08718-036Figure 24. Gain vs. FrequencyNC 08718-037Figure 25. Common Leakage CurrentTHEORY OF OPERATIONThe AD5174 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of V SS < V TERM < V DD . The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting by using the SPI interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequentpower-ups. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5174 locks to prevent any changes from taking place.The AD5174 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical.SERIAL DATA INTERFACEThe AD5174 contains a serial interface (, SCLK, DIN, and SDO) that is compatible with SPI interface standards, as well as most DSPs. This device allows writing of data via the serial interface to every register.SHIFT REGISTERThe shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit D9). The four control bits determine the function of the software command as listed in Table 6. Figure 3 shows a timing diagram of a typical AD5174 write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in . The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5174 has an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, AD5174 works with a 32-bit word but does not work properly with a 31-bit or 33-bit word. The AD5174 does not require a continuous SCLK when Table 6SYNC is high. To minimize power consumption in the digital input buffers, operate all serial interface pins close to the V DD supply rails.RDAC REGISTERThe RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal A of the variable resistor. The RDAC register is a standard logic register, and there is no restriction on the number of changes allowed. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 6) and with the desired wiper position data.50-TP MEMORY BLOCKThe AD5174 contains an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 10 shows the memory map. When the desired wiper position is determined, the user can load the serial data input register with Command 3 (see Table 6), which stores the wiper position data in a 50-TP memory register. The first address to be programmed is Location 0x01 (see Table 10); the AD5174 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approx-imately 350 ms to complete, during which time the shift register locks to prevent any changes from occurring. Bit C2 of the control register can be polled to verify that the fuse program command was completed properly. No change in supply voltage is required to program the 50-TP memory; however, a 1 μF capacitor on the EXT_CAP pin is required (see Figure 28). Prior to 50-TP activation, the AD5174 presets to midscale on power-up.WRITE PROTECTIONAt power-up, the serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit, C1, of the control register (see Table 8 and Table 9) is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4 (see Table 6). To enable programming of the RDAC register, the write protect bit (Bit C1), of the control register must first be programmed by loading the serial data input register with Command 7. To enable programming of the 50-TP memory, the program enable bit (Bit C0) of the control register, which is set to 0 by default, must first be set to 1.RDAC AND 50-TP READ OPERATIONA serial data output SDO pin is available for readback of the internal RDAC register or 50-TP memory contents. The contents of the RDAC register can be read back through SDO by using Command 2 (see Table 6). Data from the RDAC register is clocked out of the SDO pin during the last 10 clocks of the next SPI operation.It is possible to read back the contents of any of the 50-TP memory registers through SDO by using Command 5. The lower six LSB bits, D5 to D0 of the data byte, select which memory location is to be read back, as shown in Table 10. Data from the selected memory location is clocked out of the SDO pin during the next SPI operation. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 (see Table 6). This can be used to monitor the spare memory status of the 50-TP memory block. Table 7 provides a sample listing for the sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for a write and read to both the RDAC register and the 50-TP memory (Memory Location 20).Table 6. Command Operation Truth TableCommand[DB13:DB10] Data[DB9:DB0]1CommandNumber C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation0 0 0 0 0 X X X X X X X X X X NOP:donothing.1 0 0 0 1 D9D8D7D6D5D4D3D2 D1 D0Write contents of serial registerdata to RDAC.2 0 0 1 0 X X X X X X X X X X Read contents of RDAC wiperregister.3 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDACsetting to 50-TP.4 0 1 0 0 X X X X X X X X X X Software reset: refresh RDAC withlast 50-TP memory stored value. 520 1 0 1 X X X X D5D4D3D2 D1 D0 Read contents of 50-TP from SDOoutput in the next frame.6 0 1 1 0 X X X X X X X X X X Read address of last 50-TPprogrammed memory location. 730 1 1 1 X X X X X X X X D1 D0 Write contents of serial registerdata to control register.8 1 0 0 0 X X X X X X X X X X Read contents of control register.9 1 0 0 1 X X X X X X X X X D0 Softwareshutdown.D0 = 0; normal mode.D0 = 1; device placed in shutdownmode.1 X is don’t care.2 See Table 10 for 50-TP memory map.3 See Table 9 for bit details.SHUTDOWN MODEThe AD5174 can be shut down by executing the software shutdown command, Command 9 (see Table 6), and setting the LSB to 1. This feature places the RDAC in a zero-power-consumption state where Terminal A is open circuited and the wiper terminal, W, remains connected. It is possible to execute any command from Table 6 while the AD5174 is in shutdown mode. The parts can be taken out of shutdown mode by executing Command 9 and setting the LSB to 0or by a software reset, Command 4 (see Table 6). RESETThe AD5174 can be reset through software by executing Com-mand 4 (see Table 6). The reset command loads the RDAC register with the contents of the most recently programmed 50-TP memory location. The RDAC register loads with midscale if no 50-TP memory location has been previously programmed.Table 7. Write and Read to RDAC and 50-TP MemoryDI N SDO1 Action0x1C03 0xXXXX Enable update of the wiper position and the 50-TP memory contents through the digital interface.0x0500 0x1C03 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.0x0800 0x0500 Prepares data read from RDAC register.0x0C00 0x100 Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10 bits contain the contents of the RDAC register (0x100).0x1800 0x0C00 Prepares data read of the last programmed 50-TP memory monitor location.0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, last six bits) contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 10).0x1419 0x0000 Prepares data read from Memory Location 0x19.0x2000 0x0100 Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Location 0x19.0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.If Bit C2 = 1, the fuse program command was successful.1 X is don’t care.Table 8. Control Register Bit MapD9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 C2 0 C1 C0Table 9. Control Register Bit DescriptionBit Name DescriptionC0 50-TP program enable0 = 50-TP program disabled (default)1 = enable device for 50-TP programC1 RDAC register write protect0 = wiper position frozen to value in 50-TP memory (default)11 = allow update of wiper position through digital interfaceC2 50-TP memory program success bit0 = fuse program command was unsuccessful (default)1 = fuse program command was successful1 Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.Table 10. Memory MapData Byte[DB9:DB0]1Command NumberD9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents X X X 0 0 0 0 0 0 0 ReservedX X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01) X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02) X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03) X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04) … … … … … … … … … … …X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA) … … … … … … … … … … …X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14) … … … … … … … … … … …X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E)… … … … … … … … … … …X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28) … … … … … … … … … … …X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32) … … … … … … … … … … … X X X 0 1 1 1 0 0 1 MSB resistance tolerance (0x39) 5X X X 0 1 1 1 0 1 0 LSB resistance tolerance(0x3A)1X is don’t care.SDO PIN AND DAISY-CHAIN OPERATIONThe serial data output pin (SDO) serves two purposes: it can be used to read the contents of the wiper setting and 50-TP values using Command 2 and Command 5, respectively (see Table 6) or the SDO pin can be used in daisy-chain mode. Data is clocked out of SDO on the rising edge of SCLK. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor. To place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by Command 0 should be sent to the part. Table 11 provides a sample listing for the sequence of the serial datainput (DIN). Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 26, users need to tie the SDO pin of one package to the DIN pin of the next package. Users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO-to-DIN interface may require additional time delay between subsequent devices. When two AD5174 devices are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1.Table 11. Minimize Power Dissipation at SDO PinDI N SDO 1 Action 0xXXXX 0xXXXX Last user command sent to the digipot 0x8001 0xXXXX Prepares the SDO pin to be placed inhigh impedance mode0x0000 High Impedance The SDO pin is placed in highimpedance1X is don’t care.Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation.V 08718-006Figure 26. Daisy-Chain Configuration Using SDO。
DC575 24-Bit Differential Input Delta Sigma ADC 快速
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 57524-BIT DIFFERENTIAL INPUT DELTA SIGMA ADCLTC2410 DESCRIPTIONDemonstration circuit 575 features the LTC2410, a 24-bit high performance ∆Σ analog-to-digital con-verter (ADC). The LTC2410 features 2ppm linearity, 2.5ppm full-scale accuracy, 0.1ppm offset, and 0.16ppm noise. The inputs and reference are fully differential, with input common mode rejection of 140 dB. The LTC2410 is available in a 16 pin GN package and has an easy to use SPI interface.DC575 is a member of Linear Technology‘s QuickEval™ family of demonstration boards. It is de-signed to allow easy evaluation of the LTC2410 and may be connected directly to the target application’s analog signals while using the DC590 USB Serial Controller board and supplied software to measure performance. The exposed ground planes allow proper grounding to prototype circuitry. After evaluat-ing with Linear Technology’s software, the digital sig-nals can be connected to the end application’s proc-essor / controller for development of the serial inter-face.Design files for this circuit board are available. Call the LTC factory.QUICK START PROCEDUREConnect DC575 to a DC590 USB Serial Controller us-ing the supplied 14-conductor ribbon cable. Connect DC590 to the host PC with a standard USB A/B cable. Run the evaluation software supplied with DC590 or downloaded from . The correct pro-gram will be loaded automatically. Click the COLLECT button to start reading the input voltage. Details on software features are documented in the control panel’s help menu.Tools are available for logging data, changing refer-ence voltage, changing the number of points in thestrip chart and histogram, and changing the number of points averaged for the DVM display.HARDWARE SET-UPJUMPERSJP1 – Select the source for REF+, either external or 5.00 volts from the onboard LT1236 reference (de-fault.)JP2 – Select the source for REF-, either external or Ground (0 volts, default.)JP3 – Select the trigger mode, either normal (de-fault) or externally triggered.JP4 – Select the notch frequency. This selects ei-ther 50Hz or 60Hz rejection mode. Remove this jumper when supplying an external clock to the Fo turret.JP5 – Trigger input signal. Pin 1 is a 5 volt logic signal, pin 2 is ground. When triggered mode is selected on JP3, a rising edge starts a new conver-sion.CONNECTION TO DC590 SERIAL CONTROLLER J2 is the power and digital interface connector. Connect to DC590 serial controller with supplied 14-conductor ribbon cable.An external conversion clock may be applied to the Fo turret to modify the frequency rejection charac-teristics or data output rate of the LTC2410. Be sure to remove JP4 before applying an external clock.This should be a square wave with a low level equal to ground and a high level equal to Vcc. While up to a 2M Hz clock can be used, performance may be compromised. Refer to the LTC2410 data sheet. ANALOG CONNECTIONSAnalog signal connections are made via the row of turret posts along the edge of the board. When connecting the board to an existing circuit, the ex-posed ground planes along the edges of the board may be used to form a solid connection between grounds.GND – Ground turrets are connected directly to the internal ground planes.VCC – This is the supply for the ADC. Do not draw any power from this point.REF+, REF- – These are connected to the LTC2410 REF+ and REF- pins. If the onboard reference is be-ing used, the reference voltage may be monitored from this point. An external reference may be con-nected to these terminals if JP1 and JP2 are con-figured for external reference.IN+, IN- – These are the differential inputs to the LTC2410.EXPERIMENTSINPUT NOISESolder a short wire from the IN- turret post to the IN+ turret post. Noise should be approximately 0.16ppm (800nV.)COMMON MODE REJECTIONTie the two inputs (still connected together) to ground through a short wire and note the indicated voltage. Tie the inputs to REF+; the difference should be less than 1.6uV due to the 130dB CMRRof the LTC2410.RESOLVING MILLIAMPS WITH MILLIOHM SHUNTSOne application that can benefit greatly from the LTC2410’s input resolution is current measurement.It is advantageous to use a very low resistance shunt to minimize the voltage drop. To demonstrate this, make a simple current shunt by soldering a 1-inch length of 24 gauge copper wire from the IN+ turret to the IN- turret. This is a resistance of ap-proximately 2.4 milliohms. Connect the IN- turret to the GND turret through a short wire. Start the dem-onstration software and note the initial voltage, which should be close to zero. Next, connect IN+ to REF+ through a 1k resistor, which will allow ap-proximately 5mA to flow through the shunt. The indicated voltage should increase by approximately 12uV (The actual increase will depend on the toler-ance of the wire material, diameter, and length.) Since the common mode range of the inputs ex-tends from ground to VCC, the current shunt can also be used at the “high side.” To do this, tie the IN+ turret to VCC and connect the resistor from IN-to ground. Thus, the current of a circuit can be monitored with minimal impact on supply voltage and without breaking any ground connections. BIPOLAR SYMMETRYTo demonstrate the symmetry of the ADCs transfer function, connect a stable, low noise, floating volt-age source (with a voltage less than Vref/2) from IN+ to IN- and note the indicated voltage. Reverse the polarity; the indicated voltage will typically be within 15uV of the first reading, multiplied by –1. One convenient voltage source for this experiment is a single alkaline battery. While a battery has fairly, low noise, it is sensitive to temperature drift. It is best to use a large (D-size) battery that is insulated from air currents. A better source is a battery pow-ered series reference such as the LT1790. This part is available with output voltages of 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V.INPUT NORMAL MODE REJECTIONThe LTC2410’s SINC4 digital filter is trimmed to strongly reject 50 or 60Hz line noise when operated with the internal conversion clock. To measure in-put normal mode rejection, connect IN- to a 2.5 volt source such as an LT1790-2.5 reference or a power supply. Apply a 10Hz, 2V peak-to-peak sine wave to IN+ through a 1uF capacitor.Start taking data. The input noise will be quite large, and the graph of output vs. time should show large variations.Next, slowly increase the frequency to 60Hz. The noise should be almost undetectable in the graph. Note that the indicated noise in ppm may still be above that of the datasheet specification because the inputs are not connected to a DC source.。
Digital filters
Digital filtersThese days it is increasingly common for signal processing such as digital filtering to be done by a microprocessor with appropriate software instead of an analogue electronic circuit. There are a number of reasons for this:♦analogue components are variable and their parameters tend to drift with time. A microprocessor always performs exactly the same way♦the microprocessor can be reprogrammed to incorporate new and improved features.An analogue circuit would have to be rebuilt♦many applications already have a microprocessor in them — it makes sense to minimise the analogue part of the circuit and do as much processing as possible in software♦some processing tasks cannot be done in an analogue circuitWe’ll look at a particular example of di gital signal processing — the low passfilter.Analogue approachThe classic RC filter shown in Figure 1 is an example of a low pass filter. The break frequency is 1/2πRC. Signals of frequency below this are unaffected, while signals of higher frequency are attenuated, as shown in Figure 2.R and C are chosen to give a break frequency ofSoftware approachA digital filter can achieve the same effect. We need some kind of microprocessor, anA/D converter, and a D/A converter. Many real life applications have these anyway, so there is no additional cost.It turns out that low pass filtering can be done remarkably easily. One method is to generate an output that is just a weighted sum of the input and the previous output, ie: Output = A * previous output + B * input(Proving this formula isn’t so easy.)The constants A and B are given by:RC t e A / ∆−= B = 1-Awhere ∆t is the time taken to process each sample, and R and C are the values that would have been used in the analogue circuit.We can show that this method gives similar results with a couple of spreadsheets. Suppose we apply a 1-Volt step input to both circuits. The output should start off at 0V and get closer and closer to 1V without ever getting there.In spreadsheet 1, the capacitor voltage is calculated every 1ms for an RC filter withR=10k Ωand C=1 µF. The formula required is:) ( / RC to e 1 E V −−=R = 10000C = 0.000001time (ms) Vout0 0.0001 0.0952 0.1813 0.2954 0.330(Rows missed out to save space)17 0.81718 0.83519 0.85020 0.865Spreadsheet 1 — Analogue filterIn spreadsheet 2, the output is predicted for a digital filter doing one calculation every millisecond. Constants A and B are calculated from R and C using the formulas above. R = 10000 A = 0.948374C = 0.000001 B = 0.091625time (ms) Vin Vout0 1 0.0001 1 0.0952 1 0.1813 1 0.2594 1 0.330(Row s missed out to save space)17 1 0.87718 1 0.83519 1 0.85020 1 0.865Spreadsheet 2 — Digital filterYou’ll see that both methods give results that are exactly the same. This may lead you to think that digital filters are perfect. Sadly, this isn’t the case. Firstly, t he analogue version gives an output that is continuously changing, while the digital version has an output that only changes once a millisecond in this case. (See graphs 1 and 2.) Secondly, we haven’t attempted to calculate the frequency response for the digital filter. This requires much more complex maths, and turns out to have some imperfections. Finally, if we are going to the trouble of building a circuit with a microprocessor in it, we could design a much more sophisticated filter than this.However, this example does show that digital signal processing can be used as an alternative to an analogue filter.Typical applicationTwo further applications of digital filtering are —(find examples yourself on the internet. Describe the applications in around 100–200 words each, and quote the sources and web addresses you referred to.)。
MT-011 找出那些难以琢磨、稍纵即逝的ADC代码和亚稳状态
MT-011TUTORIAL找出那些难以琢磨、稍纵即逝的ADC闪码和亚稳状态作者：Walt Kester简介数字通信系统设计关注的一个主要问题是误码率(BER)。
ADC噪声对系统BER的影响可以分析得出，但前提是该噪声须为高斯噪声。
遗憾的是，ADC可能存在非高斯误码，简单分析根本无法预测其对BER的贡献。
在数字示波器等仪表应用中，误码率也可能造成问题，尤其是当器件工作于“单发”模式时，或者当器件尝试捕获偶尔出现的瞬变脉冲时。
误码可能被误解为瞬变脉冲，从而导致错误的结果。
本指南介绍ADC中可能贡献误差率的基本因素，减少问题的办法，以及BER的测量方法。
闪码、误码、跳码(RABBITS)或飞码(FLYERS)随机噪声，无论来源于何处，都会产生有限概率的误差（与预期输出的偏差）。
但在描述误码源之前，我们需要定义什么是ADC误差或者“闪码”(sparkle code)。
在ADC之前或者内部产生的噪声可以通过传统方法进行分析。
在大多数情况下，ADC噪声呈高斯分布，表现为ADC的分辨率（量化噪声）与ADC内部产生的额外噪声（折合到输入端噪声）的函数。
ADC跳码指无法归因于ADC有效高斯噪声、与预期输出之间的任何偏差。
图1所示为当一个低幅正弦波被施加给一个存在误码的ADC时，被夸大了的输出情况。
图中未显示ADC的高斯噪声。
LOW-AMPLITUDE DIGITIZED SINEWAVE (SPARKLE CODES, FLYERS, RABBITS)图1：存在误码的ADC的夸大版输出这些误差较大，比ADC高斯噪声导致的误差更加明显，属于非预期噪声。
这些误差具有随机性，出现频率非常低，对ADC进行FFT SNR测试很难检测到。
20世纪70年代，这类误差困扰着部分早期的视频ADC，由于它们在电视屏幕上表现为小白点，或者在某些测试条件下表现为“闪点”，因而被称为“闪码”。
这类误差也被称为跳码(rabbit)或飞码(flyer)。
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ABSTRACT
This paper presents a post-ADC digital filtering technique to reduce the temporal noise by exploiting the comparator transition patterns in the column single slope ADC in the CIS. The de-noising schemes do not impose additional conversion time. A simulation was conducted to analyze the effectiveness of the schemes. A test element has been fabricated using CMOS 0.18-μm single-poly five-metal (1P5M) process as a part of 4K-pixel 3T photodiode CMOS image sensor. The comparator transition patterns are digitally processed and the de-noising performances are compared. The measurement results from the test element shows that the suppression of the signal to noise ratio effectively improves by 0.57-bit of accuracy.
2. NOISE ESTIMATION ALGORITHM
The comparator output pattern reflects the temporal noise introduced at the inputs of the comparator, which are traditionally discarded. Closer to the sampled photodiode signal voltage, more frequent comparator output transitions are likely to occur. It is because that the noise of the ramp reference signal has the PDF of the white Gaussian distribution, the total noise PDF around the comparator threshold would be, due to its additive property, also the sum of the white Gaussian distribution among
Keywords: Column single slope ADC, Post-ADC processing, De-noise, CMOS image sensor.
1. INTRODUCTION
The single slope ADC architecture is widely used in commercial CISs from small size [1], [2] to very large number of pixels for the professional cameras [3]. One of reasons for the wide variety of application is due to the inherent simple column circuit structure that is indeed scalable as the pixel pitch becomes smaller [4]. However, because of its simplicity, the column single slope ADC is sensitive to the temporal noise caused by the power/ground bounce, the intrinsic noise such as thermal, shot and 1/f of the reference ramp driver and comparator, and the clock jitter [5]-[7]. It is because any input voltage fluctuation close to its threshold voltage of the comparator affects directly and yields false ADC codes. Assuming sampled photodiode signal is to be compared with the ramp signal and no fluctuation; all temporal noise is aggregated to the ramp reference signal, the noise presented at the comparator input converts the noise amplitude and frequency characteristics to various comparator output transition patterns. Thus if the noise probability density function (PDF) of the aggregated noise is known, the dynamic signal to noise ratio can be improved by estimating the true value. Fig. 1 shows the correction model, in which the sampled photodiode signal (regard as the true value), VIN, is compared with the ramp signal, VRAMP, affected by the aggregated noise, δ, and the comparator output is input to the ADC code memory to store the first or last comparator transition (regarded as a DC offset) and the noise estimator, E(*). Then the true value estimation, DOUT, is calculated by subtracting the estimated noise from the non-filtered ADC code. This estimated noise value provides the average difference between the non-filtered ADC code that is affected by the noise, and the true value. As explained in the section 2, it is equivalent to have the photodiode signal be affected by the noise, ε, and removing the ramp signal for simplicity. Then a formula can be found by the representing it in the symbolic expression.
each ramp steps of those cross the threshold as shown in Fig. 2. In case of the column single slope ADC, the ramp reference signal is constantly changing, thus a number of available samples are inevitably little. The simplest estimation method is an average of the first and last transition ADC codes, g(VIN(0)) and g(VIN(N-1)), respectively as described in (2).
[P10] Post-ADC Digital Filtering in the CIS with the Column Single Slope ADC
Toshinori Otaka *, Takumi Hiraga and Takayuki Hamamoto
Tokyo University of Science Chiyoda-ku 102-0073 Tokyo Japan E-mail: ootaka@isl.ee.kagu.tus.ac.jp TEL/FAX: +81-3-5528-8334
ˆ ˆ D OUT g V IN E g g V IN பைடு நூலகம் g g V IN
(1)
Note that g(*) represents the comparator transfer function; the function is assumed linear time invariant. DOUT and g(ε) indicate the non-filtered ADC code and the estimated noise, respectively. The first or last comparator transition ADC code is affected by the noise greatly and stored as DOUT. This noise itself can not be estimated with a simple circuit and an algorithm, however the noise average that is the center of the random noise can be estimated by processing the noise-affected comparator outputs. Since the noise average can be regarded as the true value without the DC offset as explained in the section 2, by subtracting it from the DC offset; pushes back the final transition ADC code close to the true value. So the key point is how to estimate the noise average precisely using a small number of the comparator transition patterns which are stored in the noise estimator. We propose the de-noising scheme using the arithmetic operation with the comparator transition patterns and the circuit structure that sustains the simple column layout and stringent area constraints without increasing the conversion time.