使用说明(iisplever教程(带注释))

FPGA Design withispLEVER Tutorial Lattice Semiconductor Corporation5555 NE Moore CourtHillsboro, OR 97124(503) 268-8000September 2008CopyrightCopyright © 2008 Lattice Semiconductor Corporation.This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation.TrademarksLattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. 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LSC recommends its customers obtain thelatest version of the relevant information to establish, before ordering, that theinformation being relied upon is current.Type Conventions Used in This DocumentConvention Meaning or UseBold Items in the user interface that you select or click. Text that you typeinto the user interface.<Italic>Variables in commands, code syntax, and path names.Ctrl+L Press the two keys at the same time.CourierCode examples. Messages, reports, and prompts from the software....Omitted material in a line of code....Omitted lines in code and report examples.[ ]Optional items in syntax descriptions. In bus specifications, thebrackets are required.( )Grouped items in syntax descriptions.{ }Repeatable items in syntax descriptions.| A choice between items in syntax descriptions.斜体描述ContentsIntroduction1Learning Objectives1Time to Complete This Tutorial2System Requirements2Accessing Online Help2About the Tutorial Design2About the Tutorial Data Flow3Restore the Tutorial Files4Task 1: Create a New Verilog or VHDL Project5Create a New Project5View Project Source File9Adjust Tool and Environment Options9Task 2: Assign Location and Timing Preferences11Assign Pin Location Preferences11Assign Timing Preferences15Task 3: Design Synthesis and Mapping19View the Mapping Results19View the Static Timing Analysis Report20Task 4: Place, Route, and Post-Route Timing20Place and Route the Design21View the Static Timing Analysis Report23Task 5: Viewing the Device Implementation24View the Device Implementation After Placement and Routing24 Find the Critical Path24Examine Programming of Design Planner Elements28Examine the Counter Implementation in Slices30Task 6: Improving PAR Results – Part 133Improving PAR Results for Verilog33ContentsImproving PAR Results for VHDL34Viewing the TRACE Reports34Task 7: Generate a Module Using IPexpress35Generate a sysCLOCK PLL Module36Add a PLL Instance39Examine Timing Results with sysCLOCK PLL42Task 8: Improving PAR Results – Part 243Add a Delay Adjustment Factor44Perform Placement and Routing45Guide Component Placement46Task 9: Examining Device Utilization48View the Device Implementation48View the Routing Congestion48Task 10: Estimating Power Consumption51Estimate Power for Routed Design51Estimate Power for a Different Temperature53Estimate Power for a Different Device53Task 11: Simulating the Design54Start Functional Simulation57Start Timing Simulation58Summary58Glossary58Recommended Reference Materials60FPGA Design withispLEVER TutorialIntroductionThis tutorial is intended for a new user or a user who uses ispLEVERinfrequently. It shows you how to use several processes, tools, and reportsfrom the ispLEVER software suite to implement a simple (RTL) Verilog or实现VHDL design in a LatticeEC family device. You will prepare the design forsimulation, power estimation, static timing analysis, and timing-drivenplacement and routing, reviewing output reports as you make progress. Youwill constrain the design’s inputs and outputs to meet the signal type andlocation requirements of your system-level design. You will modify andconstrain the design to leverage the architectural resources of the LatticeECdevice to give you a high-performance implementation. The tutorial covers themost common procedure and software options, so you will have a base ofunderstanding before you tackle larger or more timing-critical designs thatmay require more refinement and control to meet your performance andutilization objectives.Learning ObjectivesWhen you have completed this tutorial, you should be able to do the following:Use ispLEVER to create a new Verilog HDL or VHDL project, target adevice, and add a Verilog HDL or VHDL source file to the project usingProject Navigator.Generate a sysCLOCK PLL module, add it to your project, and refer to itfrom your source using IPexpress and Text Editor.Lock signals to device package pins and define a period or frequency andclock-to-out timing constraints using Design Planner.Implement the design using the mapping, placing, and routing processesand view the resulting reports using Project Navigator.Interpret the static timing analysis report and adjust the design to meetyour timing objectives. Modify and constrain the design to meet your performance objectives.View the device implementation and review the relative routing congestion and programmable functional unit (PFU) utilization using Design Planner.Estimate power consumption using Power Calculator. Prepare the design for simulation.Time to Complete This Tutorial The time to complete this tutorial is about two and a half hours.System Requirements One of the following software configurations is required to complete the tutorial:ispLEVERispLEVER Pro ispLEVER StarterAccessing Online HelpYou can find online help information on any tool included in the tutorial at anytime by pressing the F1 key.About the Tutorial Design The tutorial design begins with a simple counter described with register-transfer-level (RTL) Verilog or VHDL that you might find in any Verilog orVHDL textbook. It evolves into a more sophisticated version that uses registered outputs and a phase-locked loop to help reconcile the internal timing of the FPGA with the external specifications. The design is modified and constrained to account for the f MAX switching characteristics of theLatticeEC device (programmable function units (PFUs) as compared toprogrammable interface cells (PICs)) and special features like the sysCLOCKPLL to leverage the feedback compensation of the internal VCO to reduceclock-to-output delay (t CO ).You can perform the tutorial with either a Verilog HDL or VHDL source file.The complete tutorial design is composed of two Verilog or VHDL modules: a16-bit up counter with an active-low asynchronous reset and a PLL. Figure 1illustrates versions A through C of the tutorial design and the resulting timingcharacteristics. The counter is described with register-transfer-level (RTL)Verilog or VHDL and a structural model produced by an ispLEVER applicationcalled IPexpress, which describes the PLL module. The counter’s 250-MHzclock is driven externally in versions A and B of the design. In version C, it is produced by a sysCLOCK PLL that is introduced to effectively remove fromthe critical path timing equation the route delay introduced by the clock tree,allowing easier timing analysis at the PC board.说明拥挤消耗功率计算器RTL 描述复杂的使一致规格外部的Figure 1: Tutorial DesignAbout the Tutorial Data FlowA few key processes of the ispLEVER Project Navigator are used to transformthe Verilog or VHDL source code of the tutorial design into LatticeSemiconductor databases that are used by the software system to implementand analyze the logic. Figure 2 illustrates the tutorial data flow through thesystem. You may find it helpful to refer to this diagram as you move throughthe tutorial tasks.NoteIn this tutorial, where the step to be performed depends on the type of source file youare using, the step is prefaced by “Verilog:” or “VHDL:.” Where a sequence of stepsdiverge for Verilog or VHDL, they are grouped by headings that indicate their application to Verilog or VHDL.指出有少数一些按键是 将源代码转换成Lattice 半导体的数据资料丆用来 通过软件实现和 分析逻辑Figure 2: Tutorial Design Flow Restore the Tutorial FilesIf this tutorial has been previously run on your system, use the followingprocedure to restore the original tutorial files.To restore the original tutorial files:pinassign_pll_a.v (or pinassign_pll_a.vhd )IPexpress pinassign_pll.v or pinassign_pll.vhd Build Database Map DesignMap TRACE Report/Place& Route TRACE Reportec_pll.v or ec_pll.vhd pinassign_pll.prf Place & Route Design pinassign_pll.ncdpinassign_pll.ngd pinassign_pll.tw1pinassign_pll twr设计流程图Task 1: Create a New Verilog or VHDL ProjectIn this task, you will create a new Verilog HDL- or VHDL-type project andprovide it with a simple title using Project Navigator. To begin a new project,you give the project file (.syn) a name and declare the project type. TheispLEVER software saves an initial design file with the .syn file extension inthe directory that you specify. All project files are typically created in this指定directory, but you can reference source files from outside of it. The projecttype specifies that all design sources will be of this type.Create a New ProjectIf you want to preserve the original tutorial files, save the fpga_design_tutordirectory to another location on your computer before proceeding.To create a new project:1.Start Project Navigator if it is not already running.2.In Project Navigator, choose File > New Project to open the ProjectWizard dialog box.3.In the Project Wizard dialog box, shown in Figure3, do the following:a.In the Project Name box, type pinassign_PLL.b.In the Location box, specify the following directory:<install_path>\examples\Tutorial\fpga_design_tutorc.In the Design Entry Type box, choose Verilog HDL or VHDL.d.In the Synthesis Tools box, choose Synplify.e.In the Simulator Tools box, choose your preferred simulator.f.Click Next.Figure 3: Project Wizard Dialog Box4.In the Project Wizard – Select Device dialog box, shown in Figure 4, dothe following:a.In the Family box, choose LatticeEC .b.In the Device box, choose LFEC1E .c.In the Speed Grade box, choose -3.d.In the Package Type box, choose TQFP100.e.In the Operating Conditions box, choose Commercial .f.Click Next to open the Project Wizard – Add Source dialog box.5.In the Project Wizard – Add Source dialog box, click Add Source toactivate the Import File dialog box.6.Select pinassign_pll.v (or pinassign_pll.vhd ) and click the Open buttonto open the Import Source Type dialog box, shown in Figure 5.7.Select Verilog Module (or VHDL Module ) and click OK .Figure 4: Project Wizard – Select a Device Dialog BoxFigure 5: Import Source Type Dialog BoxThe file is added to the source file list in the Project Wizard – Add Sourcedialog box, as shown in Figure 6.8.Click Next .9.In the Project Wizard – Project Information dialog box, shown in Figure 7,click Finish .The new project is created, and the source file is referenced in theSources in Project list, as shown in Figure 8. Click on the part name to seethe contents of the Processes for Current Source window.Figure 6: Project Wizard – Add Source Dialog BoxFigure 7: Project Wizard – Project Information Dialog Box10.The Sources Window provides two tabs to organize the design modulesand files related to the project. The Modules tab displays each unique module and related filename used in the design hierarchy. A text entry box and magnifying glass icon allows you to search the module list.In the Sources Window, click the Files tab. Project comments and source files related to the project appear. Folders such as Documents, Stimulus Files and Input Files help organize files. Project Navigator automatically compiles all HDL source files of the project to create the module hierarchy and an ordered file list for simulation and synthesis tools. If syntax faults occur or the top of design is ambiguous you may be prompted to specify the top. File order can be adjusted in those cases where automaticordering does not work correctly.11.In the Sources in Project window, double-click the project title,pinassign_PLL, to open the Project Properties dialog box.The default title for a new project is the project name that you initiated instep 3. You can create another title for the project with as many charactersas you want. The title can contain spaces and any other keyboardcharacters, except tabs and returns.12.In the Title text box, type Pin assign and PLL sample and click OK.Figure 8: Project Navigator Window Showing New ProjectNoteYou can target a design to another Lattice Semiconductor device later, if you want. Forexample, you may discover that you can target a smaller, less expensive devicepackage if your design will fit, or you may decide to migrate an existing project to anew device family. To select a new device, choose Source > Select New Device.两个标签模块等级安排好你也可以创建另一个标题给这个工程很多人都这样做标题可以包含其他的字符丆制表符除外View Project Source FileYou “describe” a project by specifying the source files that represent the design. You can either import an existing source or create a new one. The source files for the project appear in hierarchical and alphabetical order within the Sources in Project window, Modules tab, by module name. If your source file contains more than one module, it will appear in the list as many times as there are module instantiations, using the style:module_name (source_filename)To view a source file of the project:1.Click the Modules tab in the Sources in Project window.2.Double-click the pinassign_PLL module to open the source file in TextEditor, as shown in Figure9.Figure 9: Source File in Text Editor3.Choose File > Exit to exit Text Editor.Adjust Tool and Environment OptionsTiming checkpoints occur after both the mapping and the placement and routing stages of the process flow to flag excessive delay conditions. In this tutorial, you will set checkpoints that will report if a check fails, but not block forward progress.To adjust tool and environment options:1.Choose Tools > Timing Checkpoint Options to bring up the TimingCheckpoint Options dialog box, shown in Figure10.2.In this dialog box, select the following:a.In the Checkpoint Options section of the Before Route field, set If Checkpoint failed to Continue .b.In the Checkpoint Options section of the After Route field, set IfCheckpoint fails to Continue .c.Click OK .3.Choose Options > Environment to open the Environment Options dialogbox, shown in Figure 11. In this dialog box, do the following:a.Click the Log tab.b.Turn off Using Web Browser .c.Click the Revision Control tab.d.Select Close Window when Revision Control is Disabled .e.Click OK .4.If the Revision Control window at the right of Project Navigator is open,right-click in it and choose Turn Off from the pop-up menu.The revision control window closes. This tutorial will not use projectrevision control.To re-open the Revision Control window, click on the Revision Controlicon in the Project Navigator toolbar.Figure 10: Timing Checkpoint Options Dialog Box布线 领域Task 2: Assign Location and Timing PreferencesIn this task, you lock signals to device package pins and define period or frequency and clock-to-out timing constraints. You use Design Planner, agraphical interface to the logical preference file (<project_name >.lpf), tocreate timing and location constraints for ispLEVER. The logical preferencefile is interpreted by the design mapper (Map Design process) to produce aphysical preference file (<project_name >.prf) for the place-and-route system.Now that the logic design has been captured, you can create constraints that will guide the placement and routing process to locate signals at specificpackage pin locations and implement the logic and routing to meet yourdesign’s performance objectives.Assign Pin Location PreferencesIn Project Navigator, select the LFEC1E-3T100C device in the Sources inProject window.and translates the synthesis output in EDIF to an NGD Logical Designdatabase. Information and warning messages appear in the AutomakeLog tab of the output panel of Project Navigator. You can ignore these warnings in this tutorial.The Spreadsheet View, Package View, and Design Planner Controlwindows now appear.If it is not already selected, select the Port Attributes tab in theSpreadsheet View.Figure 11: Environment Options周期或者频率约束面板The Spreadsheet View displays the Port Attributes tab for assignmentsrelated to location and buffer configuration. Preferences such as pinlocation, I/O type, and slew rate appear as columns in the sheet. It iscommon to use the Logic Signal Connections section of the device datasheet as a reference to type in pin locations.4.Click anywhere on the Spreadsheet View and verify that the View > ShowDefault Value option is selected.The Package View window provides a graphical representation of the100-pin TQFP device package.In the next steps, you will drag and drop external signals to pin locations inthe Package View window.5.Double-click the title bar of the Package View window to enlarge the view.6.Click anywhere in the right pane of the Package View window and chooseView > Top View .The Package View window adjusts to display the device package asviewed from above.7.Click on the + next to Device and next to Design Signals, then click on the+ next to all pins under Device to expand the list of pins.a.Find pin 99 in the expanded tree.b.Highlight pin 99 and right-click.c.Select Locate Device Pin .The Package View expands the view and highlights pin 99.8.Click on + to expand the CNT[15:0] bus in the left pane, as shown inFigure 12.NoteThe menu items of the Spreadsheet View are context-sensitive and enablefunctions only if they apply to the window or pane that is selected. If a menu item isunexpectedly unavailable, click on the pane to which the function applies.NoteYou can display the name of each pad by positioning the cursor over the pad.核实丆查证敏感的如果一个菜单项是不能用的点击那个函数申请的窗口9.Drag and drop the CNT[15:0] bus onto device pin 99.Design Planner fills the top left I/O bank (Bank 0) and a portion of the topright bank (Bank 1). The colored outlines of the pads represent banks.RESET_L, pin 3 (global reset) CLK, pin 19 (one of two reference clock pins for the LFEC1, 100-pinTQFP sysCLOCK PLL, which will be added later in the tutorial)As you assign pins, the package view is colored yellow to indicate outputtype ports, and the pin number appears next to the user signal in the leftpane of the Package View pane. The blue color represents inputs.Figure 12: List of Signals in BusNoteBe sure that you place the arrow connected to the bus squarely onto thedevice.衬底特殊作业光标The Spreadsheet View is also updated with the assignments that youhave made. The Pin column of the Port Attributes tab displays the pinnumbers assigned to each user signal.11.Click on the Spreadsheet View and choose Tools > PIOS DRC.12.Click OK in the Design Planner - Information pop-up message box thatcontains the following line:PIO DRC checks: No errors detected.The results of the PIO design rule check appear in the Design PlannerControl window. They help to ensure that the assignments that you havemade are legal before you submit the design to the mapping, placement,and routing tools later.13.In the Spreadsheet View, choose File > Save to update pinassign_pll.lpf.Figure13 shows the pin assignments in the Spreadsheet View.Figure 13: Pin Assignments in the Spreadsheet View专业的工具This task provides a preview of the many logical and physical preferences available for constraining FPGA mapping, placement, and routing. The FPGA Preference Language is explained in detail in the online help.To assign timing preferences with the Design Planner:1.Maximize the Spreadsheet View by double-clicking on the title bar, andchoose Preference > Period/Frequency to open the PERIOD/FREQUENCY Preference dialog box, shown in Figure14.In the Type field of the dialog box, select FREQUENCY.b.In the Second Type field, select Clock Port.A list of clock ports appears in the Available Clock Ports list.c.In the Frequency box, type 250.d.Select CLK in the Available Clock Ports box.e.Click Add.f.Click OK to close the dialog box.Figure 14: PERIOD/FREQUENCY Preference Dialog BoxThe new preference appears in the Period/Frequency tab of theSpreadsheet View, as shown in Figure 15.The FREQUENCY preference identifies the minimum operating frequencyfor all sequential-output-to-sequential-input pins clocked by the specified net.2.Choose Preference > Input_setup/Clock_to_out to open theINPUT_SETUP / CLOCK_TO_OUT Preference dialog box, shown inFigure 16.a.In the Type field of the dialog box, select CLOCK_TO_OUT .A list of signal names appears as the Clock Out Ports list.b.In the Second Type field, choose All Ports .c.In the Time box, enter 4.0 ns.d.In the Clock Ports/Nets box, select CLK .e.Click Add . Figure 15: Frequency Preference Set in Spreadsheet View这个频率参数 识别最小的工作频率对于连续输出和 连续输入 引脚f.Click OK to close the dialog box.Figure 16: INPUT_SETUP/CLOCK_TO_OUT Preference Dialog BoxThe new preference appears in the In/Out Clock tab of the SpreadsheetView, as shown in Figure17.Figure 17: Clock-to-Out Preference Set in In/Out Clock Tab of Spreadsheet Viewclock的最大允许输出延时The CLOCK_TO_OUT preference specifies a maximum allowable outputdelay relative to a clock. For example, the delay from CLK to theb.In the Filter box, type R*, and click Go .Those nets that begin with “R” appear in the Available Nets list.c.Select RESET_L_c .d.Click Add .e.Click OKto close the dialog box.The new preference appears in the Block tab of the Spreadsheet View, asshown in Figure 19.The BLOCK preference blocks timing analysis on nets, paths, buses, orcomponent pins that are irrelevant to the timing of the design. In this example, RESET_L_c drives the global set/reset (GSR) line that servesFigure 18: Block Preference Dialog BoxFigure 19: Block Preference Set in Block Tab of Spreadsheet ViewBLOCK 参数 全程时间分析 在 网络丆路径丆总线和 器件管脚与设计不相关的 时间FPGA Design with ispLEVER Tutorial Task 3: Design Synthesis and Mappingas the counter’s asynchronous reset. You can safely ignore it duringtiming analysis.4.Choose File > Save to update pinassign_pll.lpf.5.Choose File > Exit in the Design Planner Control window to exit theDesign Planner.Task 3: Design Synthesis and Mapping In this task, you will review the report created by the mapping process, which converts a logical design represented as a network of device-independent components (for example, gates and flip-flops) produced by logic synthesisand the Build Database process into a network of device-specific components(for example, PFU/PFF, IOLOGIC, or EBR) that will be eventuallyimplemented by the placement and routing process.After mapping is complete, you can perform static timing analysis to confirmthat the current implementation, accounting only for logic element delays, willmeet the timing constraints that you specified earlier.View the Mapping ResultsTo view the mapping results:1.In Project Navigator, select the LFEC1E-3T100C device in the Sources inProject window.2.Double-click Map Report .After a few moments, the pinassign_pll.mrp tab appears in the outputpanel.3.Review the major sections of the report:Design Information: Command line, device, and software versionNoteFor more information on setting preferences, select the Setting Preferences topicin the online help.NoteNotice the <port_name >_c net names created by the Synplify synthesis process for the clock tree and GSR nets. These internal signals are driven through buffersinferred by logic synthesis. In some cases, timing and location preferences refer tothese internal names instead of the external port name associated with an I/Obuffer pad. You may need to inspect the Map report or the output EDIF netlist ofthe Build Database process to understand what nets your synthesis tool produced.NoteClick on a tab to view it. If you do not see a tab, drag the vertical splitter bar to theright.注意丗端口名是被 Synplify 综合进程对时钟树和 GSR 网络综合产生的综合和 映射把逻辑设计转换为独立的器件网表仅仅是 器件 延时。