EDA综合复习1

3-8译码器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38_A ISPORT(A2,A1,A0:IN STD_LOGIC;S3,S2,S1:IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY DECODER38_A;ARCHITECTURE ONE OF DECODER38_A ISBEGINY<="11111111" WHEN S1='0' OR S2='1' OR S3='1'ELSE "11111110" WHEN A2='0' AND A1='0' AND A0='0'ELSE "11111101" WHEN A2='0' AND A1='0' AND A0='1'ELSE "11111011" WHEN A2='0' AND A1='1' AND A0='0'ELSE "11110111" WHEN A2='0' AND A1='1' AND A0='1'ELSE "11101111" WHEN A2='1' AND A1='0' AND A0='0'ELSE "11011111" WHEN A2='1' AND A1='0' AND A0='1'ELSE "10111111" WHEN A2='1' AND A1='1' AND A0='0'ELSE "01111111" ;END ARCHITECTURE ONE;七段显示器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DISPL Y_DECODER ISPORT(A3,A2,A1,A0:IN STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END ENTITY DISPL Y_DECODER;ARCHITECTURE DOUBT OF DISPL Y_DECODER ISBEGINDOUT<="1000000" WHEN A3='0' AND A2='0' AND A1='0' AND A0='0' ELSE "1111001" WHEN A3='0' AND A2='0' AND A1='0' AND A0='1'ELSE "0100100" WHEN A3='0' AND A2='0' AND A1='1' AND A0='0'ELSE "0110000" WHEN A3='0' AND A2='0' AND A1='1' AND A0='1'ELSE "0011001" WHEN A3='0' AND A2='1' AND A1='0' AND A0='0'ELSE "0010010" WHEN A3='0' AND A2='1' AND A1='0' AND A0='1'ELSE "0000010" WHEN A3='0' AND A2='1' AND A1='1' AND A0='0'ELSE "1111000" WHEN A3='0' AND A2='1' AND A1='1' AND A0='1'ELSE "0000000" WHEN A3='1' AND A2='0' AND A1='0' AND A0='0'ELSE "0010000" WHEN A3='1' AND A2='0' AND A1='0' AND A0='1'ELSE "1111111";END ARCHITECTURE DOUBT;D触发器（<同步清零，低电平有效>,<异步置数，高电平有效>）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DFF2 ISPORT(CLK:IN STD_LOGIC;D:IN STD_LOGIC;Clr:IN STD_LOGIC;Set:IN STD_LOGIC;Q: OUT STD_LOGIC);END DFF2;ARCHITECTURE bhv OF DFF2 ISBEGINPROCESS(CLK,Clr,Set)BEGINIF Set='1' THEN q<='1';ELSE IF CLK'EVENT AND CLK='1'THENIF Clr='0' THEN q<='0';ELSE Q<=D;END IF;END IF;END IF;END PROCESS;END bhv;JK触发器异步清零（高电平有效）同步置数（低电平有效）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY J_KFF ISPORT(CLK:IN STD_LOGIC;J,K,RD,SD:IN STD_LOGIC;Q,QN:OUT STD_LOGIC);END J_KFF;ARCHITECTURE SPRINT OF J_KFF ISSIGNAL Q_TEMP:STD_LOGIC:='0';SIGNAL JK:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINJK<=J&K;PROCESS(RD,SD,CLK,J,K)BEGINIF RD='1' THEN Q_TEMP<='0';ELSE IF CLK'EVENT AND CLK='0' THENIF SD='0' THEN Q_TEMP<='1';ELSECASE JK ISWHEN "00"=>Q_TEMP<=Q_TEMP;WHEN "01"=>Q_TEMP<='0';WHEN "10"=>Q_TEMP<='1';WHEN "11"=>Q_TEMP<=NOT Q_TEMP;WHEN OTHERS=>Q_TEMP<='X';END CASE;END IF;END IF;END IF;Q<=Q_TEMP;QN<=NOT Q_TEMP;END PROCESS;END SPRINT;76进制BCD码计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU_76 ISPORT (CLK:IN STD_LOGIC;Q2,Q1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END CDU_76;ARCHITECTURE DT OF CDU_76 ISSIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF (CLK'EVENT AND CLK='1')THENIF ((COUT2=7) AND (COUT1=5)) THEN COUT2<="0000";COUT1<="0000";ELSE IF (COUT1=9) THEN COUT2<=COUT2+1; COUT1<="0000";ELSE COUT2<=COUT2;COUT1<=COUT1+1;END IF;END IF;END IF;END PROCESS;Q2<=COUT2;Q1<=COUT1;END DT;156进制BCD码计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU_156 ISPORT(CLK:IN STD_LOGIC;Q3,Q2,Q1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END CDU_156;ARCHITECTURE IDT OF CDU_156 ISSIGNAL COUT3,COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF(CLK'EVENT AND CLK='1')THENIF(COUT3=1 AND COUT2=5 AND COUT1=5)THEN COUT3<="0000";COUT2<="0000";COUT1<="0000";ELSE IF (COUT2/=9 AND COUT1=9)THEN COUT2<=COUT2+1;COUT1<="0000";ELSE IF(COUT2=9 AND COUT1=9)THEN COUT3<=COUT3+1;COUT2<="0000";COUT1<="0000";ELSE COUT3<=COUT3;COUT2<=COUT2;COUT1<=COUT1+1;END IF;END IF;END IF;END IF;END PROCESS;Q3<=COUT3;Q2<=COUT2;Q1<=COUT1;END IDT;1）十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(CLK,RD,LD,EP,ET:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC);END CNT10;ARCHITECTURE ST OF CNT10 ISBEGINPROCESS(CLK,RD,LD,EP,ET)VARIABLE QI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINIF RD='0' THEN QI:=(OTHERS=>'0');ELSE IF CLK'EVENT AND CLK='1' THENIF LD='0' THEN QI:="0110";ELSE IF ((EP AND ET)='1') THENIF QI<9 THEN QI:=QI+1;COUT<='0';ELSE QI:=(OTHERS=>'0');COUT<='1';END IF;END IF;END IF;END IF;END IF;Q<=QI;END PROCESS;END ST;12位右移移位寄存器（上升沿触发，最高位补零，最低位串行输出）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHFRT ISPORT(CLK,LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(11 DOWNTO 0);QB:OUT STD_LOGIC);END SHFRT;ARCHITECTURE EDT OF SHFRT ISBEGINPROCESS(CLK,LOAD)V ARIABLE REG12:STD_LOGIC_VECTOR(11 DOWNTO 0);BEGINIF CLK'EVENT AND CLK='1' THENIF LOAD='0' THEN REG12:=DIN;ELSE REG12(10 DOWNTO 0):=REG12(11 DOWNTO 1);REG12(11):='0';END IF;END IF;QB<=REG12(0);END PROCESS;END EDT;8位左移寄存器（下降沿触发，最低位补零，8位并行输出）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHFRT1 ISPORT(CLK,LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END SHFRT1;ARCHITECTURE SPRINT OF SHFRT1 ISBEGINPROCESS(CLK,LOAD)V ARIABLE REG8:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK'EVENT AND CLK='0' THENIF LOAD='0' THEN REG8:=DIN;ELSE REG8(7 DOWNTO 1):=REG8(6 DOWNTO 0);REG8(0):='1';END IF;END IF;QB<=REG8;END PROCESS;END SPRINT;9位循环左移移位寄存器（下降沿触发，9位并行输出）：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHFRT2 ISPORT(CLK,LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(8 DOWNTO 0);QB: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));END SHFRT2;ARCHITECTURE GB OF SHFRT2 ISBEGINPROCESS(CLK,LOAD)V ARIABLE REG9:STD_LOGIC_VECTOR(8 DOWNTO 0);V ARIABLE DIL:STD_LOGIC;BEGINIF CLK'EVENT AND CLK='0' THENIF LOAD='0' THEN REG9:=DIN;ELSE DIL:=REG9(8);REG9(8 DOWNTO 1):=REG9(7 DOWNTO 0);REG9(0):=DIL;END IF;END IF;QB<=REG9;END PROCESS;END GB;。