EDA作业

EDA作业
学号：20091001680 班级：072095-11 姓名：刘云
第五章习题作业
5-8设计一个7人表决电路，参加的表决的7人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮；表决不通过则红指示灯亮。

图1 .bdf条件
图2 RTL综合图
第五章实验
5-4（3）完成半加器和全加器的设计
Full_adder的VHDL语言：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY f_adder IS
PORT(cin : IN STD_LOGIC;
bin : IN STD_LOGIC;
ain : IN STD_LOGIC;
count : OUT STD_LOGIC;
sum : OUT STD_LOGIC);
END f_adder;
ARCHITECTURE bdf_type OF f_adder IS COMPONENT or2a
PORT(a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END COMPONENT;
COMPONENT h_adder
PORT(a : IN STD_LOGIC;
b : IN STD_LOGIC;
co : OUT STD_LOGIC;
so : OUT STD_LOGIC);
END COMPONENT;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; BEGIN
b2v_inst : or2a
PORT MAP(a => SYNTHESIZED_WIRE_0,
b => SYNTHESIZED_WIRE_1,
c => count);
b2v_inst1 : h_adder
PORT MAP(a => ain,
b => bin,
co => SYNTHESIZED_WIRE_0,
so => SYNTHESIZED_WIRE_2);
b2v_inst2 : h_adder
PORT MAP(a => SYNTHESIZED_WIRE_2,
b => cin,
co => SYNTHESIZED_WIRE_1,
so => sum);
END bdf_type;
f_adder适配图
f_adde r原理输入图
f_adder时序仿真图
h_adder的VHDL语言：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS
PORT(a,b :IN STD_LOGIC;
co, so:OUT STD_LOGIC);
END ENTITY H_ADDER;
ARCHITECTURE FH1 OF H_ADDER IS
BEGIN
so <=NOT(a XOR (NOT B));
co <=a AND b;
END ARCHITECTURE FH1;
RTL综合图
第六章习题作业
6-8判断下面三个程序中是否有错误，若有则指出错误所在，并给出完整程序程序1:
Signal A, EN : std_logic;
Process(A, EN)
Variable B:std_logic;
Begin
if EN = l then B<=A; end if; --将“B<=A”改成“B:=A”
end process;
程序2:
Architecture one of sample is
variable a，b，c:integer;
begin
c<=a+b; --将“c<=a+b”改成“c:=a+b”
end;
完整程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux21 is
port(clk:in integer range 10 downto 0;
d:out integer range 20 downto 0);
end mux21;
architecture one of mux21 is
begin
process (clk)
variable a,b:integer range 10 downto 0 ;
variable c :integer range 20 downto 0 ;
begin
if clk = 1 then
b:=5;
c:=a+b;
d<=c;
else c:=a-b;d<=c;
end if;
end process;
end architecture one;
RTL综合图
仿真图
程序3:
library ieee;
use ieee.std_logic_1164.all;
entity mux21 is
port(a,b:in std_logic; sel:in std_logic;c:out std_logic;); --将“;)”改成“)” end sam2; --将“sam2”改成“entity mux21” architecture one of mux2l is
begin --增加“process(a,b,sel) begin” if sel= '0' then c:=a; else c:=b; end if; --应改成“if sel= '0' then c<=a;
else c<=b; end if;”
--增加“end process;”
end two; --将“two”改成“architecture one”
library ieee;
use ieee.std_logic_1164.all;
entity mux21 is
port (a,b:in std_logic;
sel:in std_logic;
c :out std_logic);
end entity mux21;
architecture one of mux21 is
begin
process(a,b,sel)
begin
if sel= '0' then c<=a; else c<=b; end if;
end process;
end architecture one;
RTL综合图
仿真图
第六章实验
6-4 32位并进/并出移位寄存器设计
仅用例6-8一个8位移位寄存器，再增加一些电路，如4个8位锁存器等，设计成为一个能为32位二进制数进行不同方式移位的移位寄存器。

这个电路模型十分容易用到CPU的设计中。

程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity move_32 is
port( clk,rst,load,mve :in std_logic;
din :in std_logic_vector(31 downto 0);
qh,qb :out std_logic);
end move_32;
architecture one of move_32 is
begin
process(clk,rst,load,mve)
variable reg32: std_logic_vector(31 downto 0); begin
if rst='1' then
reg32:=(others=>'0');
elsif clk'event and clk='1' then
if load='1' then
reg32:=din;
elsif mve='1' then
reg32(30 downto 0):=reg32(31 downto 1);
else reg32(31 downto 1):=reg32(30 downto 0); end if;
end if;
qb<=reg32(0);
qh<=reg32(31);
end process;
end one;
RTL综合图
仿真图。