EDA课后作业

❖ End generate; end;
4-6. 根据图4-21，写出顶层文件MX3256.VHD的VHDL设计文件。
t3 t4
t2 t1
图4-21 题4-6电路图
❖ Library ieee; use ieee.std_logic_1164.alll; ❖ Entity mx3256 is ❖ Port(ina,inb,inck,inc:in std_logic; ❖ e,out1:out std_logic); ❖ End mx3256; ❖ Architecture behav of mx3256 is ❖ Component lk35 ❖ Port(a1,a2,clk:in std_logic; ❖ q1,q2:out std_logic); End component; ❖ Signal t1,t2,t3,t4:std_logic; ❖ Begin u1:lk35 port
❖ End one;
❖ 使用CASE语句：
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Entity mux41 is
❖ Port(s0,s1,a,b,c,d:in std_logic;
❖ y:out std_logic);
❖ End mux41;
❖ Architecture one of mux41 is
❖ End suber;
❖ Architecture behav of suber is
❖ Component h_suber
❖ Port(x,y:in std_logic;
❖
diff,s_out:out std_logic);
❖ End component;
❖ Signal t0,t1,t2:std_logic;
❖ Entity ex16 is
❖ Port(clk,clr,en,sel:in std_logic;
❖ Begin s10<=s1 &s0;
❖ process(s10,a,b,c,d)
❖
begin if s10=“00” then y<=a;
❖
elsif s10=“01 then y<=b;
❖
elsif s10=“10” then y<=c;
❖
else y<=d;
❖
end if ;
❖
end process;
❖ END buf3x ;
❖ ENTITY mux21 IS --实体2： 2选1多路选择器
❖ PORT (in0, in1, sel : IN STD_LOGIC;
❖
output : OUT STD_LOGIC);
4-2. 图4-17所示的是4选1多 路选择器，试分别用 IF_THEN语句和CASE语句 的表达方式写出此电路的 VHDL程序。
❖ End behav;
❖ 一位全减器的VHDL描述suber.vhd
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Entity suber is
❖ Port(x,y,sub_in:in std_logic;
❖
diffr,sub_out:out std_logic);
❖ 4-1画出与下例实体描述对应的原理图符号元件：
❖ ENTITY buf3s IS -- 实体1： 三态缓冲器
❖ PORT (input : IN STD_LOGIC ; -- 输入端
❖
enable : IN STD_LOGIC ; -- 使能端
❖
output : OUT STD_LOGIC ) ; -- 输出端
❖
C:out std_logic_vector(7 doento 0);
❖ End sub8;
❖ Architecture behav of suber8 is
❖ Component suber
❖ Port(x,y,sub_in:in std_logic;
❖ diffr,sub_out:out std_logic); End component;
❖
end case;
❖
end process;
❖ End one;
4-3. 图4-18所示的是双2选1多路选择器构成的电路MUXK，对 于其中MUX21A，当s='0'和'1'时，分别有y<='a'和y<='b'。试 在一个结构体中用两个进程来表达此电路，每个进程中用CASE 语句描述一个2选1多路选择器MUX21A。
❖
y:out std_logic); End component;
❖ Signal tmp:std_logic;
❖ Begin U1:mux21 port map(a=>a2,b=>a3,s=>s0,y=>tmp);
❖
U2:mux21 port map(a=>a1,b=>tmp,s=>s1,y=>outy);
❖ Entity muxk is
❖ Port(s0,s1,a1,a2,a3:in std_logic;
❖
outy:out std_logic);
❖ End muxk;
❖ Architecture beh of muxk is
❖ Component mux21
❖ port(s,a,b:in std_logic;
❖
process(s1,a1,tmp)
❖
begin case s1 is
❖
when ‘0’=>outy<=a1 ;
❖
when ‘1’=>outy<=tmp;
❖
end case;
❖
end process;
❖ End one;
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Signal s10:std_logic_vector(1 downto 0);
❖ Begin s10<=s1 &s0;
❖ process(s10,a,b,c,d)
❖
begin case s10 is
❖
when “00”=>y<=a; when “01”=>y<=b;
❖
when “10”=>y<=c; when others=>y<=a;
❖
end if;
❖ end process;
❖ Out1<=not tmp;
❖ End one;
4-5. 给出1位全减器的VHDL描述。要求： (1) 首先设计1位半减器，然后用例化语句将它们连接起来， 图4-20中h_suber是半减器，diff是输出差，s_out是借位输出， sub_in是借位输入。 (2) 以1位全减器为基本硬件，构成串行借位的8位减法器，要 求用例化语句来完成此项设计(减法运算是 x – y - sun_in = diffr)。
map(a1=>ina,a2=>inb,clk=>inck,q1=>t3,q2=>t2); ❖ U2: lk35 port
map(a1=>t2,a2=>t1,clk=>inck,q1=>t4,q2=>out1); ❖ Process(inck,inc) ❖ Begin if(inc=‘0’)then t1<=‘0’; ❖ elsif(rising_edge(inck)) then t1<=t2; ❖ End if; end process; ❖ E<=t4 when t2=‘0’ else t3; end;
图4-18 双2选1多路选择器
K 康芯科技 X
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Entity muxk is
❖ Port(s0,s1,a1,a2,a3:in std_logic;
❖ outy:out std_logic);
❖ End muxk;
选择控制的信号s1和s0的数 据类型为 STD_LOGIC_VECTOR；
当s1='0'，s0='0'；s1='0'， s0='1'；s1='1'，s0='0'和 s1='1'，s0='1'分别执行y<=a、 y<=b、y<=c、y<=d。
图4-17 4选1多路选择器
❖ 使用IF…THEN语句：
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Entity mux21 is
❖ port(s,a,b:in std_logic;
❖
y:out std_logic);
❖ End mux21;
❖ Architecture one of mux21 is
❖ Begin y<=a when s=‘0’ else b;
❖ End one;
❖ Library ieee; use ieee.std_logic_1164.alll;
❖ Architecture one of muxk is
❖ Signal tmp:std_logic;
❖ Begin process(s0,a2,a3)
❖
begin case s0 is
❖
when ‘0’=>tmp<=a2 ;
❖
when ‘1’=>tmp<=a3;