DESIGN OF HOMOGENEOUS COMMUNICATION INFRASTRUCTURES FOR PARTIALLY RECONFIGURABLE FPGAS

Authors:Jens Hagemeyer,Boris Kettelhoit,Markus Koester,Mario Porrmann

in proceedings of the2007International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA’07),Las Vegas,USA,June25-28,2007.

DESIGN OF HOMOGENEOUS COMMUNICATION INFRASTRUCTURES FOR

PARTIALLY RECONFIGURABLE FPGAS

Jens Hagemeyer,Boris Kettelhoit,Markus Koester,Mario Porrmann

Heinz Nixdorf Institute,System and Circuit Technology,

University of Paderborn,Germany

email:{jenze,boris,koester,porrmann}@hni.uni-paderborn.de

ABSTRACT

Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current pos-sibilities.One of the main prerequisites for its implemen-tation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time.In this paper we present a new com-munication macro for Xilinx FPGAs that considers the spe-cial requirements of these systems.While most solutions that were presented so far enable basic communication be-tween a low number of hardware modules atfixed positions, our approach implements an infrastructure that allows free placement of hardware modules at run-time.Methodolo-gies like2D-placement of modules,which were analyzed mainly in theory so far,can now be implemented with cur-rently available FPGAs.A tool-flow is presented,that au-tomatically generates the required homogeneous communi-cation infrastructure for any FPGA of the Xilinx Virtex-E to Virtex-5family.Performance and area requirements are analyzed based on two typical example implementations of

a Wishbone bus.

1.INTRODUCTION

In today’s digital systems more and more functionality is re-alized using FPGAs,which are replacing traditional ASIC or processor-based solutions due to their better cost/perfor-mance ratio or due to shorter time-to-market.Dynamic re-configuration,i.e.,partially changing the FPGA configu-ration at run-time is a promising approach to enhance the performance of a given architecture.While the theoreti-cal aspects of dynamic reconfiguration have been analyzed since more than ten years,applications that demonstrate the practical relevance of dynamic reconfiguration are still rare. The main reason for the lack of working implementations is the fact that tools enabling easy access to this new tech-nology are just coming up. E.g.,a novel method for re-alizing online-routing on Xilinx Virtex-2FPGAs was intro-duced in[4].Furthermore,most realizations of dynamically reconfigurable systems use simple approaches that are based onfixed module slots.These implementations are different from the possibilities and from the problems that are ana-lyzed in the theoretical research work.In this paper we try to help closing this gap by showing how today’s heteroge-neous FPGAs can be used for dynamic reconfiguration with free module placement,varying module sizes,and multiple instances of modules.The main aspect targeted in this paper is the design of a homogeneous communication infrastruc-ture for Xilinx FPGAs that enables data transfer between an arbitrary number of dynamically reconfigurable hardware modules–as aflexible yet resource efficient alternative to the typically used Xilinx bus macros.

Our methodology is widely independent from the in-ternal structure of the FPGA since the communication in-frastructure can be realized with tristate buffers as well as with slice-based routing,which has been introduced in[3]. The proposed approach based on the design-flow presented in[10].In the next section the principles of dynamic recon-figuration with FPGAs are discussed and our communica-tion infrastructure is presented,highlighting the relation of our approach to the current state of research.Details of the homogeneous communication infrastructure are sketched in Section3,followed by a description of the automatic gen-eration of the required embedded communication macros in Section4.Finally,example implementations and results concerning area efficiency and performance are presented in Section5.

2.PARTIALLY RECONFIGURABLE SYSTEMS The design of a partially reconfigurable system requires par-titioning of the area of the FPGA into a static and a dy-namic region.In the following,a corresponding partitioning scheme is introduced.

2.1.Partitioning the FPGA

A partially reconfigurable system is composed of static com-ponents and dynamic components.Static components are the parts of the system that are always present,like the re-