AT89C51RB2-RC2部分中文翻译
关于单片机at89c51的外文翻译5000字英文
关于单片机at89c51的外文翻译5000字英文篇一：毕业设计外文翻译单片机AT89C51附件1：外文资料翻译译文AT89C51主要性能参数：与MCS-51产品如前所述完全兼容4K字节可重檫写Flash闪速存储器1000次檫写周期全静态操作：0HZ-24MHZ三级加密程序存储器128*8字节内部RAM32个可编程I/O口线2个16位定时/记数器6个中断源可编程串行UART通道低功耗空闲和掉电操作方式功能特性概述：AT89C51提供更多以下标准功能：4K字节Flash闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时/记数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器妥善钟电路。
同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但允许RAM，定时/记数器，串行通信口及中断系统继续工作。
掉电方式保存RAM中的内容，但振荡器停止工作直到下一个硬件逊位。
AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4k bytes的可反复擦写的只读程序存储器（PEROM）和128 bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C51单片机用法可为您提供许多高性价比的应用场合，可灵活科技领域应用于各种支配领域。
AT89C51方框图引脚功能说明·Vcc：电源电压·GND：地·P0 口：P0 口是一组8 位漏极开路型双向I／O 口，也即地址／数据总线复用口。
作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1”可作为差阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
关于AT89C51单片机的中英翻译
The Introduction of AT 89C51 DescriptionMicrocontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system tocontinue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description·VCC: Supply voltage.·GND: Ground.·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.·Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification.·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory andduring accesses to external data memory that uses 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below。
AT89C51单片机中文资料
AT89C51单片机中文资料AT89C51是一种带4K字节闪烁可编程可擦除只读存储器(FPEROM—Falsh Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机.2.管脚说明：VCC：供电电压。
GND：接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。
当P1口的管脚第一次写1时，被定义为高阻输入。
P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。
在FIASH编程时,P0 口作为原码输入口，当FIASH进行校验时，P0输出原码,此时P0外部必须被拉高。
P1口：P1口是一个内部提供上拉电阻的8位双向I/O口，P1口缓冲器能接收输出4TTL门电流。
P1口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。
在FLASH编程和校验时，P1口作为第八位地址接收.P2口：P2口为一个内部上拉电阻的8位双向I/O口,P2口缓冲器可接收，输出4个TTL门电流,当P2口被写“1"时，其管脚被内部上拉电阻拉高，且作为输入。
并因此作为输入时，P2口的管脚被外部拉低，将输出电流。
这是由于内部上拉的缘故.P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位.在给出地址“1”时，它利用内部上拉优势,当对外部八位地址数据存储器进行读写时，P2口输出其特殊功能寄存器的内容。
P2口在FLASH编程和校验时接收高八位地址信号和控制信号。
P3口：P3口管脚是8个带内部上拉电阻的双向I/O口，可接收输出4个TTL门电流.当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。
作为输入，由于外部下拉为低电平，P3口将输出电流(ILL)这是由于上拉的缘故。
P3口也可作为AT89C51的一些特殊功能口,如下表所示:口管脚备选功能P3.0 RXD（串行输入口）P3。
AT89C51单片机中文资料
AT89C51单片机中文资料ＡＴ89C5１就是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM—Fａlsh Programｍａble and Eｒasａｂｌe Reａd ＯｎlｙＭemory)得低电压,高性能CMOＳ８位微处理器,俗称单片机.2、管脚说明:VCC:供电电压。
GＮD:接地.P0口:P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。
当P１口得管脚第一次写１时,被定义为高阻输入。
Ｐ0能够用于外部程序数据存储器,它可以被定义为数据/地址得第八位。
在FIＡＳH编程时，P０口作为原码输入口,当FIAＳＨ进行校验时，P０输出原码,此时Ｐ0外部必须被拉高。
P1口:P１口就是一个内部提供上拉电阻得8位双向Ｉ／O口,Ｐ1口缓冲器能接收输出4TTL 门电流。
Ｐ１口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时,将输出电流,这就是由于内部上拉得缘故。
在ＦLＡＳH编程与校验时,P1口作为第八位地址接收。
Ｐ２口：P2口为一个内部上拉电阻得8位双向I/Ｏ口，P2口缓冲器可接收，输出4个ＴTL 门电流，当P2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。
并因此作为输入时,Ｐ2口得管脚被外部拉低，将输出电流。
这就是由于内部上拉得缘故.P2口当用于外部程序存储器或１6位地址外部数据存储器进行存取时，P２口输出地址得高八位。
在给出地址“1”时，它利用内部上拉优势，当对外部八位地址数据存储器进行读写时,P2口输出其特殊功能寄存器得内容。
Ｐ2口在FLASＨ编程与校验时接收高八位地址信号与控制信号。
P3口：P3口管脚就是８个带内部上拉电阻得双向I/O口,可接收输出4个ＴTL门电流。
当P ３口写入“1”后,它们被内部上拉为高电平,并用作输入.作为输入，由于外部下拉为低电平,P3口将输出电流（ILＬ)这就是由于上拉得缘故。
P3口也可作为AT89C51得一些特殊功能口,如下表所示:口管脚备选功能Ｐ3、0 RXD（串行输入口)P３、１ TＸD（串行输出口)P3、2 ／INT0（外部中断０）P3、３／ＩNT1(外部中断1）Ｐ3、４ T0（记时器０外部输入）P3、５ T1(记时器1外部输入)Ｐ3、６/WR(外部数据存储器写选通）P3、7 /ＲD（外部数据存储器读选通)P3口同时为闪烁编程与编程校验接收一些控制信号。
英译汉AT89C51的外文翻译
The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.1Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.2Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit3set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.45Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum andmaximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset,6the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can beprogrammed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to functionproperly.译文：AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
AT89C51单片机中文资料
AT89C51单片机中文资料AT89C51是一种带4K字节闪烁可编程可擦除只读存储器(FPEROM—Falsh Programmable and Erasable Read Only Memory)的低电压，高性能CMOS8位微处理器，俗称单片机。
2.管脚说明：VCC:供电电压.GND:接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。
当P1口的管脚第一次写1时，被定义为高阻输入。
P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。
在FIASH编程时,P0 口作为原码输入口，当FIASH进行校验时，P0输出原码,此时P0外部必须被拉高。
P1口：P1口是一个内部提供上拉电阻的8位双向I/O口，P1口缓冲器能接收输出4TTL门电流。
P1口管脚写入1后，被内部上拉为高,可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。
在FLASH编程和校验时，P1口作为第八位地址接收。
P2口：P2口为一个内部上拉电阻的8位双向I/O口,P2口缓冲器可接收，输出4个TTL门电流,当P2口被写“1"时，其管脚被内部上拉电阻拉高,且作为输入。
并因此作为输入时，P2口的管脚被外部拉低，将输出电流。
这是由于内部上拉的缘故。
P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位。
在给出地址“1”时，它利用内部上拉优势,当对外部八位地址数据存储器进行读写时，P2口输出其特殊功能寄存器的内容.P2口在FLASH编程和校验时接收高八位地址信号和控制信号。
P3口：P3口管脚是8个带内部上拉电阻的双向I/O口,可接收输出4个TTL门电流。
当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。
作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。
P3口也可作为AT89C51的一些特殊功能口,如下表所示：口管脚备选功能P3.0 RXD（串行输入口）P3.1 TXD(串行输出口）P3.2 /INT0(外部中断0）P3.3 /INT1（外部中断1)P3.4 T0（记时器0外部输入）P3.5 T1(记时器1外部输入)P3.6 /WR(外部数据存储器写选通)P3。
AT89C51芯片介绍完整中英文翻译
DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by theinternal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write toa port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down ModesPower Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value,and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object reached.Data PollingThe AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/BusyThe progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program VerifyIf lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip EraseThe entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature BytesThe signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
AT89C51的介绍外文翻译
The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 aslisted below:Port 3 also receives some control signals for Flash programming and verification. RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in orderfor the device to function properly.AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
单片机89C52中英文对照翻译(经典版)
AT89C52 internal structure analysis DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM contentsbut freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, eachpin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to externalprogram memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000Hup to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate er software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed toexternal memory.On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 cont ains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are availableas stack space.Watchdog Timer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive anoutput RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow.The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether theWDT continues tocount if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (). From the home page, select ‘Products’,then ‘8051-Architecture Flash Microcontroller’, then‘Product Overview’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to the ATMEL Web site (). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samplesshow a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Sin ce two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In thismode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.译文：89C52的内部结构分析功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
AT89C51的介绍外文翻译1
AT89C51的介绍描述：AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。
片内含有8位中央处理器和闪烁存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：·与MCS-51产品指令系统完全兼容·4K字节可重擦写Flash闪速存储器·1000次擦写周期·数据保留时间：10年·全静态操作：0Hz—24MHz·三级加密程序存储器·128×8字节内部RAM·32个可编程I/O口线·2个16位定时/计数器·6个中断源·可编程串行UART通道·低功耗空闲和掉电模式·片内振荡器和时钟电路·全双工UART串行中断口线·双数据寄存器指针功能特性概述：AT89C51提供以下标准功能：4K字节Flash闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。
同时，AT89C51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但允许RAM，定时/计数器。
串行通信口及中断系统继续工作。
掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
AT89C51单片机是一个行业标准架构，被广泛接受和应用，并作为一种开发工具。
有许多工业供应商，他们供应这种控制器或把这种控制器集成到某种类型的系统芯片的结构。
医学研究理事会和高级微电子研究所都选择这个设备，但他们论证的是两种截然不同固化工艺。
AT89C51芯片介绍完整中英文翻译
DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s.During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG)during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown inFigure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down ModesPower Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated.The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programmingmode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data PollingThe AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Pollingmay begin any time after a write cycle has been initiated.Ready/BusyThe progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program VerifyIf lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip EraseThe entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature BytesThe signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes 的快速可擦写的只读程序存储器（PEROM）和128bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
ATM89C51单片机简介中英双语
原文：The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel 'shigh-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memoryto be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51provides the following standard features: 4K bytes of Flash, 128 bytes of RAM,32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, theAT89C51 is designed with static logic for operation down to zerofrequency and supports two software selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,timer/counters, serial port and interruptsystem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage .GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When1s are written to port 0 pins, the pins can be used as highimpedance 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL 1s arewritten to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal 2 emits the high-order address byte during fetches from externalprogram memoryand during accesses to external data memorythat use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL 1s arewritten to Port 3 pins they are pulled high by the internal pullups and can be used as in puts. As in puts,Port 3 pins that are exter nally being pulled low will source current (IIL) because of the 3 also serves the fun cti ons of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verificati on.RSTReset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch En able output pulse for latch ing the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and maybe used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000Hup to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on should bestrapped to VCCfor internal program pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure a quartzcrystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of theexternal clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Clock Drive Con figurati onIdle ModeIn idle mode, the CPUputs itself to sleep while all the on chip peripherals rema inactive. The mode is invoked by software. The content of the on-chip RAM and all thespecial fun cti ons registers rema in un cha nged duri ng this mode. The idle mode canbe term in ated by any en abled in terrupt or by a hardware should be no ted that whe n idle is term in ated by a hard ware reset, the device no rmally resumes program executio n,from where it left off, up to two machi ne cycles before the internal reset algorithmtakes control. On-chip hardwarein hibits access to internal RAM in this eve nt, but access to the port pins is not in hibited. To elim in ate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to exter nal memory.X1AL2EXTERNALOSCILLATOR XTAL.1 SIGNALGNDVFigure 2. Exter nalX7AL2X7AL1 「讣 Figure 1. Oscillator Conn ecti onsPower-dow n ModeIn the power-dow n mode, the oscillator is stopped, and theinstruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Fun cti on Registers retai n their values until the power-down modeis terminated. The only exit from power-dow n is a hardware reset. Reset redefi nes the SFRs but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its n ormal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize.Status of External Pins During Idle and Power-down ModesProgram Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed(U) or can be programmed(P) to obtain the additional features listed in the table below. Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pinis sampled and latched duri ng reset. If the device is powered upwithout a reset, the latch initializes to a random value, and holdsthat value until reset is activated. It is necessary that the latchedvalue of EA be in agreement with the current logic level at thatpin in order for the device to fun cti on properly.译文：AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS啦单片机带有4K字节的可反复擦写的程序存储器（PENROM这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。
89C51RB2资料
元器件交易网SCON Address = 98H Reset Value = 0000 0000B Bit AddressableSM0/FE SM1SM2REN TB8RB8Tl RlBit:76543210(SMOD0 = 0/1)*Symbol FunctionFE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.SM0Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)SM1Serial Port Mode Bit 1SM0SM1Mode Description Baud Rate**000shift register f OSC/6 (6 clock mode) or f OSC/12 (12 clock mode)0118-bit UART variable1029-bit UART f OSC/32 or f OSC/16 (6 clock mode) orf OSC/64 or f OSC/32 (12 clock mode)1139-bit UART variableSM2Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is aGiven or Broadcast Address. In Mode 0, SM2 should be 0.REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.TB8The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.RB8In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.In Mode 0, RB8 is not used.Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software.Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.NOTE:*SMOD0 is located at PCON6.**f OSC = oscillator frequency SU01255Figure 7. SCON: Serial Port Control RegisterPX0IP (0B8H)Priority Bit = 1 assigns high priorityPriority Bit = 0 assigns low priorityBIT SYMBOL FUNCTIONIP .7––IP .6PPC PCA interrupt priority bitIP .5PT2Timer 2 interrupt priority bit.IP .4PS Serial Port interrupt priority bit.IP .3PT1Timer 1 interrupt priority bit.IP .2PX1External interrupt 1 priority bit.IP .1PT0Timer 0 interrupt priority bit.IP .0PX0External interrupt 0 priority bit.SU01291PT0PX1PT1PS PT2PPC –01234567Figure 11. IP RegistersPX0HIPH (B7H)Priority Bit = 1 assigns higher priorityPriority Bit = 0 assigns lower priorityBIT SYMBOL FUNCTIONIPH.7––IPH.6PPCH PCA interrupt priority bitIPH.5PT2H Timer 2 interrupt priority bit high.IPH.4PSH Serial Port interrupt priority bit high.IPH.3PT1H Timer 1 interrupt priority bit high.IPH.2PX1H External interrupt 1 priority bit high.IPH.1PT0H Timer 0 interrupt priority bit high.IPH.0PX0H External interrupt 0 priority bit high.SU01292PT0H PX1H PT1H PSH PT2H PPCH –01234567Figure 12. IPH RegistersCMOD Address = C1H Reset Value = 00XX X000BCIDL WDTE–––CPS1CPS0ECFBit:76543210Symbol FunctionCIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle.WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.–Not implemented, reserved for future use.*CPS1PCA Count Pulse Select bit 1.CPS0PCA Count Pulse Select bit 0.CPS1CPS0Selected PCA Input**000Internal clock, f OSC/6 in 6 clock mode (f OSC/12 in 12 clock mode)011Internal clock, f OSC/2 in 6 clock mode (f OSC/4 in 12 clock mode)102Timer 0 overflow113External clock at ECI/P1.2 pin(max. rate = f OSC/4 in 6 clock mode, f OCS/8 in 12 clock mode)ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.NOTE:*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.**f OSC = oscillator frequencySU01257Figure 17. CMOD: PCA Counter Mode RegisterCCON Address = 0C0H Reset Value = 00X0 0000B Bit AddressableCF CR–CCF4CCF3CCF2CCF1CCF076543210Bit:Symbol FunctionCF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software.CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off.–Not implemented, reserved for future use*.CCF4PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.CCF3PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.CCF2PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.CCF1PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.CCF0PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.NOTE:*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.SU01099Figure 18. CCON: PCA Counter Control RegisterDIP40:plastic dual in-line package; 40 leads (600 mil)SOT129-1PLCC44:plastic leaded chip carrier; 44 leads SOT187-2QFP44:plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2。
AT89C51单片机英文文献附带翻译
AT89C51的概况一 AT89C51应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。
然而，这些关键应用领域也要求这些单片机高度可靠。
健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。
Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51 汽车单片机多线性测试环境。
这种环境的目标不仅是为AT89C51 汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。
开发的这种环境连接了AT89C51。
本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51。
1.1 介绍8 位AT89C51 CHMOS 工艺单片机被设计用于处理高速计算和快速输入/输出。
MCS51 单片机典型的应用是高速事件控制系统。
商业应用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。
汽车工业把MCS51 单片机用于发动机控制系统，悬挂系统和反锁制动系统。
AT89C51 尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。
由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。
拥有操作不可预测的设备的经济和法律风险是很高的。
一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。
重新设计的费用可以高达500K 美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。
另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。
基于89C51单片机的中英翻译
（AT89C51中英文翻译对照）Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1. IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these criticalapplications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix meansback annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postsilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins the y are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri -ng each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationNote: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic ResonatorsPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokespower-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Flash Programming ModesFigure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.Flash Programming and Verification CharacteristicsTA = 0°C to 70°C, VCC = 5.0 10%Note: 1. Only used in 12-volt programming mode.Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsTA = -40°C to 85°C, VCC = 5.0V 20% (unless otherwise noted)AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.External Program and Data Memory CharacteristicsExternal Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsSerial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V 20%; Load Capacitance = 80 pF)Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1) Float Waveforms(1)A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps.An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for adigital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amp lified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. T hese hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
(完整word版)89C51单片机简介外文翻译
89C51单片机简介单片机广泛应用于各个商业领域，比如：调制解调器，电动机控制系统,空调控制系统，汽车发动机和其他一些领域.这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。
然而,这些关键应用领域对这些单片机有高度可靠的要求。
健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。
Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51汽车单片机多线性测试环境。
这种环境的目标不仅是为AT89C51汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。
开发的这种环境连接了AT89C51.本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51.早期的单片机都是8位或4位的。
其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。
此后在8031上发展出了MCS51系列单片机系统。
基于这一系统的单片机系统直到现在还在广泛使用。
随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。
90年代后随着消费电子产品大发展，单片机技术得到了巨大的提高.随着INTEL i960系列特别是后来的ARM系列的广泛应用,32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。
而传统的8位单片机的性能也得到了飞速提高,处理能力比起80年代提高了数百倍。
目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。
当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。
而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。
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Features 特征
•80C52 Compatible 80C52兼容
–8051 Pin and Instruction Compatible 8051引脚和指令兼容
–Four 8-bit I/O Ports 4个8位I/O口
–Three 16-bit Timer/Counters 3个16位定时器/计数器
–256 Bytes Scratch Pad RAM 256字节片内RAM
–9 Interrupt Sources with 4 Priority Levels 9个中断源4个优先级
–Dual Data Pointer 双数据指针
•Variable Length MOVX for Slow RAM/Peripherals
用于低速RAM/外设的可变长传送指令
•ISP (In-system Programming) Using Standard V CC Power Supply
在系统编程使用标准电源Vcc
•Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader
引导ROM包含底层闪存可编程例程和一个默认的串行加载器
•High-speed Architecture 高速构架
–48 MHz in Standard Mode and Internal Code Execution (40 MHz for external code) 在标准模式和内部代码执行为48兆赫兹（40兆赫兹用于外部代码）
–24 MHz in X2 Mode and internal code execution (20 MHz for external code) 在*2模式和内部代码执行为24兆赫兹（20兆赫兹用于外部代码）
–16K/32K Bytes On-chip Flash Program/Data Memory
16K/32K字节片上程序存储器/数据存储器
–Byte and Page (128 Bytes) Erase and Write 字节和页（128字节）擦写
–100K Write Cycles 100000次循环写入
•On-chip 1024 Bytes Expanded RAM (XRAM) 1024字节的外部随机存储器
–Software Selectable Size (0, 256, 512, 768, 1024 Bytes)软件可选择空间大小（字节）–256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
为与TS87C51RB2/RC2兼容，复位时选择256字节
•Keyboard Interrupt Interface on Port P1
键盘中断口在P1
•SPI Interface (Master/Slave Mode) SPI接口
•8-bit Clock Prescaler 8位时钟预分频器
•Improved X2 Mode with Independent Selection for CPU and Each Peripheral 对cpu和每个外设都有独立选择的*2模式
•Programmable Counter Array 5 Channels 5通道可编程计数器阵列
–High-speed Output 高速输出
–Compare/Capture 比较/捕获
–Pulse Width Modulator 脉宽调制器
–Watchdog Timer Capabilities 看门狗定时器功能
•Asynchronous Port Reset 异步端口复位
•Full Duplex Enhanced UART 全双工增强型通用异步收发机•Dedicated Baud Rate Generator for UART UART专用波特率生成器
•Low EMI (Inhibit ALE) 低电磁干扰（禁止ALE信号输出）
•Hardware Watchdog Timer (One-time Enabled with Reset-out)
硬件看门狗定时器
•Power Control Modes 电压控制模式
–Idle Mode 空闲模式
–Power-down Mode 掉电模式
–Power-off Flag 关机标志
•Power Supply: 电源
–2.7 to 3.6 (3V Version) 2.7-3.6（3V版本）
–2.7 to 5.5V (5V Version) 2.7-5.5V（5V版本）
•Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C) 温度范围:商业（0-70℃）工业（-40-85℃）
•Packages: PDIL40, PLCC44, VQFP44 封装
Description 描述
The AT89C51RB2/RC2 is a high-performance（高性能）Flash version（版本）of the 80C51 8-bit micro-controllers（单片机）. It contains a 16K or 32K Bytes Flash memory block（闪存块）for program and data.
The Flash memory can be programmed either in parallel mode（并行方式）or in serial mode（串行方式）withthe ISP capability or with software（用isp或软件编程）. The programming voltage is internally generated（内部产生）from the standard VCC pin.
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internalRAM, a 9-source AT89C51RB2/RC2保留80C52所有特性，256字节内部RAM，9个中断源4个控制级，三个定时器/计数器
4-level interrupt controller and three timer/counters.
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array（计数器阵
列）, an XRAM of1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface,
an SPI Interface（接口）, amore versatile serial channel（通用串行通道）that
facilitates multiprocessor communication (EUART多处理器通信)and a speed
improvement mechanism (X2 mode).The Pinout is the standard 40/44 pins of the
C52. The fully static design reduces system power consumption of the
AT89C51RB2/RC2 byallowing it to bring the clock frequency down to any value,
even DC, without loss of data（全静态设计通过允许将时钟频率降低到任何值甚
至直流来降低AT89C51RB2的功耗而又不丢失数据）.The AT89C51RB2/RC2 has 2
software-selectable（软件可选的）modes of reduced activity and 8-bitclock
prescaler(预分频器) for further reduction in power consumption（为进一步降低
功耗）. In Idle（空闲）mode, the CPU is fro-zen（停止）while the peripherals
（外设）and the interrupt system are still operating. In power-down（掉电）mode,
the RAM is saved and all other functions are inoperative（不起作用）.The added
features of the AT89C51RB2/RC2 make it more powerful for applicationsthat need
pulse width modulation（脉宽调制）, high speed I/O and counting capabilities（计
数功能）such asalarms, motor control（电机控制）, corded phones（有线电话）,
and smart card readers（智能卡读卡器）.。