ADC1113D125HNC15;ADC1113D125HNC1,5;中文规格书,Datasheet资料

1. General descriptionThe ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimizedfor high dynamic performance and low power at a sample rate of 125 Msps. Pipelined architecture and output error correction ensure the ADC1113D125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3V source for analog and a 1.8V source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A format. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of ICconfigurations is also available via the binary level control pins taken, which are used at power-up. The device also includes a programmable full-scale SPI to allow flexible input voltage range of 1V to 2V (peak-to-peak).Excellent dynamic performance is maintained from the baseband to input frequencies of 170MHz or more, making the ADC1113D125 ideal for use in communications, imaging, and medical applications.2. Features and benefits3. ApplicationsADC1113D125Dual 11-bit ADC; serial JESD204A interfaceRev. 3 — 10 February 2011Product data sheetSNR, 66.5 dBFS; SFDR, 86 dBc Input bandwidth, 600MHz Sample rate: 125 MspsPower dissipation, 1270mW Clock input divided by 2 for less jittercontributionSPI register programming 3V, 1.8V single supplies Duty Cycle Stabilizer (DCS) Flexible input voltage range:1V (p-p)to 2V (p-p)High IF capabilityTwo configurable serial outputsOffset binary, two’s complement, graycodeTwo JESD204A serial outputs Power-down mode and Sleep mode Pin compatible with ADC1613D series, ADC1413D series, and ADC1213D seriesHVQFN56 packageWireless and wired broadbandcommunications Portable instrumentation Spectral analysisImaging systemsUltrasound equipmentSoftware defined radio4. Ordering information5. Block diagramTable 1.Ordering informationType numberSamplingfrequency (Msps)Package Name DescriptionVersionADC1113D125HN/C1125HVQFN56plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8×8×0.85mmSOT684-76. Pinning information6.1Pinning6.2Pin descriptionTable 2.Pin descriptionSymbol Pin Type[1]DescriptionINAP1I channel A analog inputINAM2I channel A complementary analog inputVCMA3O channel A output common voltageREFAT4O channel A top referenceREFAB5O channel A bottom referenceAGND6G analog groundCLKP7I clock inputCLKM8I complementary clock inputAGND9G analog groundREFBB10O channel B bottom referenceREFBT11O channel B top referenceVCMB12O channel B output common voltageINBM13I channel B complementary analog inputINBP 14I channel B analog input VDDA 15P analog power supply 3V VDDA 16P analog power supply 3V SCLK 17I SPI clock SDIO 18I/O SPI data IO CS 19I chip select AGND 20G analog ground RESET21I JEDEC digital IP reset SCRAMBLER 22I scrambler enable and disableCFG023I/O see Table 28 (input) or OTRA (output)[2]CFG124I/O see Table 28 (input) or OTRB (output)[2]CFG225I/O see Table 28 (input)CFG326I/O see Table 28 (input)VDDD 27P digital power supply 1.8V DGND 28G digital ground DGND 29G digital ground DGND 30G digital groundVDDD 31P digital power supply 1.8V CMLPB 32O channel B outputCMLNB 33O channel B complementary output VDDD 34P digital power supply 1.8V DGND 35G digital ground DGND 36G digital groundVDDD 37P digital power supply 1.8V CMLNA 38O channel A complementary output CMLPA 39O channel A output VDDD 40P digital power supply 1.8 V DGND 41G digital ground DGND 42G digital groundSYNCP 43I synchronization from FPGA SYNCN 44I synchronization from FPGA DGND 45G digital groundVDDD 46P digital power supply 1.8VSWING_047I JESD204 serial buffer programmable output swing SWING_148I JESD204 serial buffer programmable output swing DNC 49O do not connectVDDA 50P analog power supply 3V AGND 51G analog ground AGND52Ganalog groundTable 2.Pin description …continuedSymbol Pin Type [1]DescriptionTable 2.Pin description …continuedSymbol Pin Type[1]DescriptionVDDA 53P analog power supply 3VSENSE54I reference programming pinVREF55I/O voltage reference input/outputVDDA 56P analog power supply 3V[1]P: power supply; G: ground; I: input; O: output; I/O: input/output.[2]OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B.7. Limiting valuesTable 3.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max UnitV DDA analog supply voltage−0.4+4.6VV DDD digital supply voltage−0.4+2.5VT stg storage temperature−55+125°CT amb ambient temperature−40+85°CT j junction temperature-125°C 8. Thermal characteristicsTable 4.Thermal characteristicsSymbol Parameter Conditions Typ UnitR th(j-a)thermal resistance from junction to ambient[1]17.8K/WR th(j-c)thermal resistance from junction to case[1] 6.8K/W[1]Value for six layers board in still air with a minimum of 25 thermal vias.9.Static characteristicsTable 5.Static characteristics[1]Symbol Parameter Conditions Min Typ Max Unit SuppliesV DDA analog supply voltage 2.85 3.0 3.4VV DDD digital supply voltage 1.65 1.8 1.95VI DDA analog supply current f clk=125Msps;-343-mAf i=70MHz-150-mA I DDD digital supply current f clk=125Msps;f i=70MHzP tot total power dissipation f clk=125Msps-1270-mW P power dissipation Power-down mode-30-mWStandby mode-200-mW Clock inputs: pins CLKP and CLKM (AC-coupled)Low-Voltage Positive Emitter-Coupled Logic (LVPECL)peak-to-peak-±1.6-VV i(clk)dif differential clock inputvoltageSINEpeak-to-peak-±3.0-VV i(clk)dif differential clock inputvoltageLow Voltage Complementary Metal Oxide Semiconductor (LVCMOS)V IL LOW-level input voltage--0.3V DDA VV IH HIGH-level input voltage0.7V DDA--V Logic inputs, Power-down: pins CFG0to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESETV IL LOW-level input voltage-0-VV IH HIGH-level input voltage-0.66V DDD-VI IL LOW-level input current−6-+6μA I IH HIGH-level input current−30-+30μA SPI: pins CS, SDIO, and SCLKV IL LOW-level input voltage0-0.3V DDA VV IH HIGH-level input voltage0.7V DDA-V DDA VI IL LOW-level input current−10-+10μA I IH HIGH-level input current−50-+50μA C I input capacitance-4-pFAnalog inputs: pins INAP, INAM, INBP, and INBMI I input current track mode−5-+5μA R I input resistance track mode-15-ΩC I input capacitance track mode-5-pF V I(cm)common-mode inputvoltagetrack mode0.9 1.52VB i input bandwidth-600-MHz V I(dif)differential input voltage peak-to-peak1-2V Voltage controlled regulator output: pins VCMA and VCMBV O(cm)common-mode outputvoltage-V DDA / 2-VI O(cm)common-mode outputcurrent-4-mA Reference voltage input/output: pin VREFV VREF voltage on pin VREF output0.5-1Vinput0.5-1V Data outputs: pins CMLPA, CMLNAOutput levels, V DDD=1.8V; SWING_SEL[2:0]=000V OL LOW-level outputvoltage DC coupled; output- 1.5-V AC coupled- 1.35-VV OH HIGH-level outputvoltage DC coupled; output- 1.8-V AC coupled - 1.65-VOutput levels, V DDD=1.8V; SWING_SEL[2:0]=001V OL LOW-level outputvoltage DC coupled; output- 1.45-V AC coupled - 1.275-VV OH HIGH-level outputvoltage DC coupled; output- 1.8-V AC coupled - 1.625-VOutput levels, V DDD=1.8V; SWING_SEL[2:0]=010V OL LOW-level outputvoltage DC coupled; output- 1.4-V AC coupled - 1.2-VV OH HIGH-level outputvoltage DC coupled; output- 1.8-V AC coupled - 1.6-VOutput levels, V DDD=1.8V; SWING_SEL[2:0]=011V OL LOW-level outputvoltage DC coupled; output- 1.35-V AC coupled - 1.125-VV OH HIGH-level outputvoltage DC coupled; output- 1.8-V AC coupled - 1.575-VOutput levels, V DDD=1.8V; SWING_SEL[2:0]=100V OL LOW-level outputvoltage DC coupled; output- 1.3-V AC coupled - 1.05-VV OH HIGH-level outputvoltage DC coupled; output- 1.8-V AC coupled - 1.55-VTable 5.Static characteristics[1] …continuedSymbol Parameter Conditions Min Typ Max Unit[1]Typical values measured at V DDA =3V,V DDD =1.8V, T amb =25°C. Minimum and maximum values are across the full temperature range T amb =−40°C to +85°C at V DDA =3V, V DDD =1.8V; V I (INAP , INBP)−V I (INAM, INBM)=−1dBFS; internal reference mode; 100Ω differential applied to serial outputs; unless otherwise specified.Serial configuration: pins SYNCCP , SYNCCNV IL LOW-level input voltagedifferential; input-0.95-V V IHHIGH-level input voltage differential; input - 1.47-V Accuracy INL integral non-linearity −5-+5LSB DNL differential non-linearity no missing codes guaranteed −0.95±0.25+0.95LSB E offset offset error -±2-mV E G gain errorfull-scale-±0.5-%M G(CTC)channel-to-channel gain matching- 1.1-%Supply PSRRpower supply rejection ratio200mV (p-p) on pin VDDA; f i =DC-−54-dBTable 5.Static characteristics [1] …continuedSymbol ParameterConditions Min Typ Max Unit10.Dynamic characteristics10.1Dynamic characteristicsTable 6.Dynamic characteristics[1]Symbol Parameter Conditions Min Typ Max Unit Analog signal processingα2H second harmonic level f i=3MHz-88-dBcf i=30MHz-87-dBcf i=70MHz-85-dBcf i=170MHz-83-dBcα3H third harmonic level f i=3MHz-87-dBcf i=30MHz-86-dBcf i=70MHz-84-dBcf i=170MHz-82-dBcTHD total harmonic distortion f i=3MHz-84-dBcf i=30MHz-83-dBcf i=70MHz-81-dBcf i=170MHz-79-dBc ENOB effective number of bits f i=3MHz-10.7-bitsf i=30MHz-10.7-bitsf i=70MHz-10.7-bitsf i=170MHz-10.6-bitsSNR signal-to-noise ratio f i=3MHz-66.2-dBFSf i=30MHz-66.2-dBFSf i=70MHz-66.0-dBFSf i=170MHz-65.8-dBFS SFDR spurious-free dynamic range f i=3MHz-87-dBcf i=30MHz-86-dBcf i=70MHz-84-dBcf i=170MHz-82-dBcIMD intermodulation distortion f i=3MHz-89-dBcf i=30MHz-88-dBcf i=70MHz-86-dBcf i=170MHz-84-dBcαct(ch)channel crosstalk f i=70MHz-100-dBc[1]Typical values measured at V DDA=3V,V DDD=1.8V, T amb=25°C. Minimum and maximum values are across the full temperaturerange T amb=−40°C to +85°C at V DDA=3V, V DDD=1.8V; V I(INAP, INBP)−V I(INAM, INBM)=−1dBFS; internal reference mode;100Ω differential applied to serial outputs; unless otherwise specified.10.2Clock and digital output timingTable 7.Characteristics[1]Symbol Parameter Conditions Min Typ Max Unit Clock timing input: pins CLKP and CLKMf clk clock frequency100-125Mspst lat(data)data latency time-14-clock cycle δclk clock duty cycle DCS_EN=logic1305070%DCS_EN=logic0455055%t d(s)sampling delay time-0.8-nst wake wake-up time-76-μs[1]Typical values measured at V DDA=3V,V DDD=1.8V, T amb=25°C. Minimum and maximum values are across the full temperaturerange T amb=−40°C to +85°C at V DDA=3V, V DDD=1.8V; V I(INAP, INBP)−V I(INAM, INBM)=−1dBFS; internal reference mode;100W differential applied to serial outputs; unless otherwise specified.10.3Serial output timingThe eye diagram of the serial output is shown in Figure3 and Figure4. Test conditionsare:• 3.125 Gbps data rate•T amb=25°C•DC coupling with two different receiver common-mode voltages分销商库存信息:NXPADC1113D125HN/C1:5ADC1113D125HN/C1,5。