201003_IT in TSMC
07- TSM V6.1 Monitoring and Reporting
Discovering the value of the IBM Tivoli Storage Manager v6.2 Product Family
Tivoli Storage Manager v6.x Monitoring and Reporting
An IBM Proof of Technology
The Tivoli Monitoring agent is installable on this OS
The agent is NOT installable on this OS but is able to monitor TSM remotely from the Tivoli Monitoring server The agent is NOT installable on this OS but is able to monitor TSM remotely from the Tivoli Monitoring server The agent is NOT installable on this OS but is able to monitor TSM remotely from the Tivoli Monitoring server The Tivoli Monitoring agent is installable on this OS
● Can monitor and report 5.4, 5.5 and 6.x servers ● No need to license DB2, Tivoli Monitoring or Tivoli Common Reporting separately
© 2010 IBM Corporation
IEEE拒绝收录的138个会议列表-推荐下载
IEEE拒绝收录的138个会议列表2011-10-27 14:54:18| 分类：EI、ISTP检索国际 | 标签：ieee 收录 138 会议列表 |字号大中小订阅IEEE拒绝收录的138个会议列表138个会议名单如下:2010 2nd Asia-Pacific Conference on Information Processing (APCIP)2010 2nd International Asia Symposium on Intelligent Interaction and Affective Computing & 2010 2nd International onInnovation Management (ASIA-ICIM)2010 2nd International Conference on Future Computer and Communication (FCC) 2010 2nd International Conference on Information and Multimedia Technology (ICIMT)2010 2nd International Conference on Intellectual Technique in Industrial Practice (ITIP 2010)2010 2nd International Conference on Multimedia and Computational Intelligence (ICMCI)2010 2nd International Conference on Research Challenges in Computer Science (ICRCCS)2010 2nd International Symposium on Computer Network and Multimedia Technology (CNMT 2010)2010 3rd International Conference on Computational Intelligence and Industrial Application (PACIIA)2010 3rd International Conference on Environmental and Computer Science (ICECS) 2010 3rd International Conference on Machine Vision (ICMV)2010 3rd International Conference on Power Electronics and Intelligent Transportation System (PEITS)2010 4th International Conference on Intelligent Information Technology Application (IITA)2010 6th International Conference on MEMS, NANO, and Smart Systems (ICMENS) 2010 First International Conference on Cellular, Molecular Biology, Biophysics and Bioengineering (CMBB)2010 IIS 2nd International Conference on Signal Processing, Robotics and Automation (ICSRA 2010)2010 International Asia Conference on Optical Instrument and Measurement (ACPIM)2010 International Conference on Bio-Inspired Systems and Signal Processing (ICBSSP)2010 International Conference on Biology, Environment and Chemistry (ICBEC) 2010 International Conference on Broadcast Technology and MultimediaCommunication (BTMC)2010 International Conference on Circuit and Signal Processing (ICCSP)2010 International Conference on Communication and Vehicular Technology (ICCVT)2010 International Conference on Computational Intelligence and Vehicular System (CIVS)2010 International Conference on Computer and Computational Intelligence (ICCCI) 2010 International Conference on Computer and Software Modeling (ICCSM)2010 International Conference on Computer Science and Sports Engineering (CSSE) 2010 International Conference on Computer-Aided Manufacturing and Design (CMD)2010 International Conference on Construction and Project Management (ICCPM) 2010 International Conference on Digital Enterprise and Digital Manufacturing (DEDM)2010 International Conference on E-business, Management and Economics (ICEME) 2010 International Conference on Economics, Business and Management (ICEBM) 2010 International Conference on Electrical Engineering and Automatic Control (ICEEAC)2010 International Conference on Embedded Systems and Microprocessors (ICESM) 2010 International Conference on Engineering Education and Educational Technology (EEET)2010 International Conference on Future Biomedical Information Engineering (FBIE) 2010 International Conference on Future Computer, Control and Communication (FCCC)2010 International Conference on Future Industrial Engineering and Application (ICFIEA)2010 International Conference on Future Information Technology (ICFIT)2010 International Conference on Future Information Technology and Computing (FITC)2010 International Conference on Graphic and Image Processing (ICGIP)2010 International Conference on Information and Finance (ICIF)2010 International Conference on Information Security and Artificial Intelligence (ISAI)2010 International Conference on Intelligence and Information Technology (ICIIT) 2010 International Conference on Intelligent Network and Computing (ICINC)2010 International Conference on Management Science (ICMS)2010 International Conference on Management Science and Information Engineering (ICMSIE)2010 International Conference on Manufacturing Science and Technology (ICMST) 2010 International Conference on Measurement and Control Engineering (ICMCE) 2010 International Conference on Mechanical and Aerospace Engineering (ICMAE) 2010 International Conference on Mechanical Engineering, Robotics and Aerospace (ICMERA)2010 International Conference on Modeling, Simulation and Control (ICMSC 2010)2010 International Conference on Nano Science and Technology (ICNST)2010 International Conference on Nanotechnology and Biosensors (ICNB)2010 International Conference on Nuclear Energy and Engineering Technology (NEET)2010 International Conference on Physics Science and Technology (ICPST)2010 International Conference on Psychology, Psychological Sciences and Computer Science (PPSCS)2010 International Conference on Remote Sensing (ICRS)2010 International Conference on Semiconductor Laser and Photonics (ICSLP)2010 International Conference on Services Science, Management and Engineering (SSME)2010 International Conference on Signal and Information Processing (ICSIP)2010 International Conference on Software and Computing Technology (ICSCT) 2010 International Conference on Sport Medicine, Sport Science, and Computer Science (SMSSCS)2010 ISECS International Colloquium on Computing, Communication, Control, and Management (CCCM 2010)2010 Second International Conference on E-Learning, E-Business, Enterprise Information Systems, and E-Government(EEEE)2010 Second International Conference on Test and Measurement (ICMT)2010 Second International Seminar on Business and Information Management (ISBIM)2010 Third International Conference on Computer and Electrical Engineering (ICCEE)2010 Third International Conference on Education Technology and Training (ETT) 2010 Third International Symposium on Intelligent Ubiquitous Computing and Education (IUCE)2010 Third Pacific-Asia Conference on Web Mining and Web-Based Application (WMWA)2011 15th Global Chinese Conference on Computers in Education (GCCCE)2011 2nd Asia-Pacific Conference on Wearable Computing Systems (APWCS)2011 2nd International Conference on Biomedical Engineering and Computer Science (ICBECS)2011 2nd International Conference on Biotechnology and Food Science (ICBFS) 2011 2nd International Conference on Data Storage and Data Engineering (DSDE) 2011 2nd International Conference on Environmental Science and Technology (ICEST)2011 2nd International Conference on Financial Theory and Engineering (ICFTE) 2011 2nd International Conference on Mechanical, Industrial, and Manufacturing Technologies (MIMT)2011 2nd Intl Conf on Innovative Computing & Communication and 2010 Asia-Pacific Conf on Information Technology &Ocean Engineering, (CICC-ITOE)2011 2nd World Congress on Computer Science and Information Engineering (CSIE) 2011 3rd IEEE International Conference on Information Management and Engineering (ICIME)2011 3rd International Conference on Bioinformatics and Biomedical Technology (ICBBT 2011)2011 3rd International Conference on Computer and Automation Engineering (ICCAE)2011 3rd International Conference on Computer and Network Technology (ICCNT) 2011 3rd International Conference on Computer Design and Applications (ICCDA 2011)2011 3rd International Conference on Computer Modeling and Simulation (ICCMS) 2011 3rd International Conference on E-business and Information System Security (EBISS)2011 3rd International Conference on Machine Learning and Computing (ICMLC) 2011 3rd International Conference on Networks Security, Wireless Communications and Trusted Computing (NSWCTC)2011 3rd International Conference on Signal Acquisition and Processing (ICSAP) 2011 3rd International Workshop on Education Technology and Computer Science (ETCS)2011 4th IEEE International Conference on Computer Science and Information Technology (ICCSIT 2011)2011 IEEE International Conference on Information and Education Technology (ICIET)2011 IEEE International Conference on Smart Grid and Clean Energy Technologies (ICSGCE)2011 International Conference on Applied Physics and Mathematics (ICAPM 2011) 2011 International Conference on Bioinformatics and Computational Biology (ICBCB)2011 International Conference on Bioscience, Biochemistry and Bioinformatics (ICBBB)2011 International Conference on Communication and Electronics Information (ICCEI)2011 International Conference on Computer and Communication Devices (ICCCD) 2011 International Conference on Computer Applications and Network Security (ICCANS)2011 International Conference on Computers, Communications, Control and Automation (CCCA)2011 International Conference on Control, Robotics and Cybernetics (ICCRC)2011 International Conference on Data Engineering and Internet Technology (DEIT) 2011 International Conference on Database and Data Mining (ICDDM)2011 International Conference on Digital Convergence (ICDC)2011 International Conference on Economics and Finance Research (ICEFR)2011 International Conference on Economics, Business and Marketing Management (CEBMM)2011 International Conference on Economics, Trade and Development (ICETD) 2011 International Conference on Electrical Energy and Networks (ICEEN)2011 International Conference on Energy and Environment (ICEE)2011 International Conference on Engineering and Information Management (ICEIM) 2011 International Conference on Environment Science and Engineering (ICESE) 2011 International Conference on Environmental Science and Development (ICESD) 2011 International Conference on Future Environment and Energy (ICFEE 2011) 2011 International Conference on Fuzzy Systems and Neural Computing (FSNC) 2011 International Conference on Information and Computer Applications (ICICA) 2011 International Conference on Information and Computer Networks (ICICN) 2011 International Conference on Information and Industrial Electronics (ICIIE) 2011 International Conference on Information Engineering and Mechanical Engineering (IEME)2011 International Conference on Innovation and Information Management (ICIIM) 2011 International Conference on Intelligent Information Networks (ICIIN)2011 International Conference on Knowledge Discovery (ICKD)2011 International Conference on Life Science and Technology (ICLST)2011 International Conference on Manufacturing and Industrial Engineering (ICMIE) 2011 International Conference on Mechanical and Aerospace Engineering (ICMAE) 2011 International Conference on Medical Information and Bioengineering (ICMIB) 2011 International Conference on Network Communication and Computer (ICNCC) 2011 International Conference on Product Development and Renewable Energy Resources (ICPDRE)2011 International Conference on Security Science and Technology (ICSST)2011 International Conference on Social Science and Humanity (ICSSH)2011 International Conference on Solid-State and Integrated Circuit (ICSIC)2011 International Conference on System Design and Data Proceesing (ICSDDP) 2011 International Conference on System。
tms320vc5416数据手册
TMS320VC5416Fixed-Point Digital Signal Processor Data ManualPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.Literature Number:SPRS095PMarch1999–Revised October2008Revision HistoryTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH 1999–REVISED OCTOBER 2008NOTE:Page numbers for previous revisions may differ from page numbers in the current version.This data sheet revision history highlights the technical changes made to the SPRS095O device-specific data sheet to make it an SPRS095P revision.Scope:This document has been reviewed for technical accuracy;the technical content is up-to-date as of the specified release date with the following corrections.2Revision History Submit Documentation FeedbackContentsTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH 1999–REVISED OCTOBER 2008Revision History ...........................................................................................................................1TMS320VC5416Features.......................................................................................................2Introduction.......................................................................................................................2.1Description ..................................................................................................................2.2PinAssignments............................................................................................................2.2.1TerminalAssignments forthe GGUPackage...............................................................2.2.2Pin AssignmentsforthePGEPackage......................................................................2.2.3Signal Descriptions ..............................................................................................3Functional Overview ...........................................................................................................3.1Memory ......................................................................................................................3.1.1Data Memory .....................................................................................................3.1.2Program Memory ................................................................................................3.1.3Extended Program Memory ...................................................................................3.2On-Chip ROM With Bootloader ...........................................................................................3.3On-Chip RAM ...............................................................................................................3.4On-Chip Memory Security .................................................................................................3.5Memory Map ................................................................................................................3.5.1Relocatable Interrupt Vector Table ............................................................................3.6On-Chip Peripherals .......................................................................................................3.6.1Software-Programmable Wait-State Generator .............................................................3.6.2Programmable Bank-Switching ................................................................................3.6.3Bus Holders ......................................................................................................3.7Parallel I/O Ports ...........................................................................................................3.7.1Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)..........................................................3.7.2HPI Nonmultiplexed Mode ......................................................................................3.8Multichannel Buffered Serial Ports (McBSPs)..........................................................................3.9Hardware Timer ............................................................................................................3.10Clock Generator ............................................................................................................3.11Enhanced External Parallel Interface (XIO2)...........................................................................3.12DMA Controller .............................................................................................................3.12.1Features ..........................................................................................................3.12.2DMA External Access ...........................................................................................3.12.3DMA Memory Maps .............................................................................................3.12.4DMA Priority Level ...............................................................................................3.12.5DMA Source/Destination Address Modification .............................................................3.12.6DMA in Autoinitialization Mode ................................................................................3.12.7DMA Transfer Counting .........................................................................................3.12.8DMA Transfer in Doubleword Mode ..........................................................................3.12.9DMA Channel Index Registers .................................................................................3.12.10DMA Interrupts ..................................................................................................3.12.11DMA Controller Synchronization Events .....................................................................3.13General-Purpose I/O Pins .................................................................................................3.13.1McBSP Pins as General-Purpose I/O .........................................................................3.13.2HPI Data Pins as General-Purpose I/O ......................................................................3.14Device ID Register .........................................................................................................3.15Memory-Mapped Registers ...............................................................................................3.16McBSP Control Registers and Subaddresses ..........................................................................3.17DMA Subbank Addressed Registers ....................................................................................3.18Interrupts ....................................................................................................................4Support .............................................................................................................................Contents3TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 4.1Documentation Support...................................................................................................4.2Device and Development-Support Tool Nomenclature................................................................5Electrical Specifications......................................................................................................5.1Absolute Maximum Ratings...............................................................................................5.2Recommended Operating Conditions...................................................................................5.3Electrical Characteristics.................................................................................................5.3.1Test Loading.....................................................................................................5.3.2Timing Parameter Symbology............................................................................................5.3.3Internal Oscillator With External Crystal.................................................................................5.4Clock Options...............................................................................................................5.4.1Divide-By-Two and Divide-By-Four Clock Options..........................................................5.4.2Multiply-By-N Clock Option(PLL Enabled)...................................................................5.5Memory and Parallel I/O Interface Timing..............................................................................5.5.1Memory Read....................................................................................................5.5.2Memory Write....................................................................................................5.5.3I/O Read..........................................................................................................5.5.4I/O Write..........................................................................................................5.5.5Ready Timing for Externally Generated Wait States..................................................................5.5.6and Timings...............................................................................................5.5.7Reset,BIO,Interrupt,and MP/MC Timings.............................................................................5.5.8Instruction Acquisition and Interrupt Acknowledge Timings..........................................5.5.9External Flag(XF)and TOUT Timings..................................................................................5.5.10Multichannel Buffered Serial Port(McBSP)Timing...................................................................5.5.10.1McBSP Transmit and Receive Timings....................................................................5.5.10.2McBSP General-Purpose I/O Timing.......................................................................5.5.10.3McBSP as SPI Master or Slave Timing....................................................................5.5.11Host-Port Interface Timing...............................................................................................5.5.11.1HPI8Mode.....................................................................................................5.5.11.2HPI16Mode....................................................................................................6Mechanical Data.................................................................................................................6.1Package Thermal Resistance Characteristics..........................................................................4Contents Submit Documentation FeedbackTMS320VC5416Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008List of Figures2-1144-Ball GGU MicroStar BGA™(Bottom View).............................................................................2-2144-Pin PGE Low-Profile Quad Flatpack(Top View).......................................................................3-1TMS320VC5416Functional Block Diagram..................................................................................3-2Program and Data Memory Map................................................................................................3-3Extended Program Memory Map...............................................................................................3-4Process Mode Status Register..................................................................................................3-5Software Wait-State Register(SWWSR)[Memory-Mapped Register(MMR)Address0028h].........................3-6Software Wait-State Register(SWWSR)[Memory-Mapped Register(MMR)Address0028h].........................3-7Bank-Switching Control Register BSCR)[MMR Address0029h]...........................................................3-8Host-Port Interface—Nonmulltiplexed Mode.................................................................................3-9HPI Memory Map.................................................................................................................3-10Multichannel Control Register(MCR1).........................................................................................3-11Multichannel Control Register(MCR2).........................................................................................3-12Pin Control Register(PCR)......................................................................................................3-13Nonconsecutive Memory Read and I/O Read Bus Sequence.............................................................3-14Consecutive Memory Read Bus Sequence(n=3reads)..................................................................3-15Memory Write and I/O Write Bus Sequence.................................................................................3-16DMA Transfer Mode Control Register(DMMCRn)...........................................................................3-17On-Chip DMA Memory Map for Program Space(DLAXS=0and SLAXS=0).........................................3-18On-Chip DMA Memory Map for Data and IO Space(DLAXS=0and SLAXS=0)....................................3-19DMPREC Register................................................................................................................3-20General-Purpose I/O Control Register(GPIOCR)[MMR Address003Ch]................................................3-21General-Purpose I/O Status Register(GPIOSR)[MMR Address003Dh].................................................3-22Device ID Register(CSIDR)[MMR Address003Eh].........................................................................3-23IFR and IMR Registers...........................................................................................................5-1Tester Pin Electronics............................................................................................................5-2Internal Divide-By-Two Clock Option With External Crystal...............................................................5-3External Divide-By-Two Clock Timing.........................................................................................5-4Multiply-By-One Clock Timing..................................................................................................5-5Nonconsecutive Mode Memory Reads.......................................................................................5-6Consecutive Mode Memory Reads............................................................................................5-7Memory Write(MSTRB=0)....................................................................................................5-8Parallel I/O Port Read(IOSTRB=0).........................................................................................5-9Parallel I/O Port Write(IOSTRB=0)..........................................................................................5-10Memory Read With Externally Generated Wait States.....................................................................5-11Memory Write With Externally Generated Wait States.....................................................................5-12I/O Read With Externally Generated Wait States...........................................................................5-13I/O Write With Externally Generated Wait States...........................................................................5-14HOLD and HOLDA Timings(HM=1).........................................................................................List of Figures5TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 5-15Reset and BIO Timings.........................................................................................................5-16Interrupt Timing..................................................................................................................5-17MP/MC Timing...................................................................................................................5-18Instruction Acquisition(IAQ)and Interrupt Acknowledge(IACK)Timings................................................5-19External Flag(XF)Timing......................................................................................................5-20TOUT Timing.....................................................................................................................5-21McBSP Receive Timings.......................................................................................................5-22McBSP Transmit Timings.......................................................................................................5-23McBSP General-Purpose I/O Timings........................................................................................5-24McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=0....................................................5-25McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=0....................................................5-26McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=1....................................................5-27McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=1....................................................5-28Using HDS to Control Accesses(HCS Always Low)........................................................................5-29Using HCS to Control Accesses...............................................................................................5-30HINT Timing......................................................................................................................5-31GPIOx Timings...................................................................................................................5-32Nonmultiplexed Read Timings.................................................................................................5-33Nonmultiplexed Write Timings.................................................................................................5-34HRDY Relative to CLKOUT....................................................................................................6List of Figures Submit Documentation FeedbackTMS320VC5416Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008List of Tables2-1Terminal Assignments for the TMS320VC5416GGU(144-Pin BGA Package).........................................2-2Signal Descriptions...............................................................................................................3-1Standard On-Chip ROM Layout...............................................................................................3-2Processor Mode Status(PMST)Register Bit Fields........................................................................3-3Software Wait-State Register(SWWSR)Bit Fields.........................................................................3-4Software Wait-State Control Register(SWCR)Bit Fields..................................................................3-5Bank-Switching Control Register(BSCR)Fields..............................................................................3-6Bus Holder Control Bits..........................................................................................................3-7Sample Rate Input Clock Selection...........................................................................................3-8Clock Mode Settings at Reset.................................................................................................3-9DMD Section of the DMMCRn Register......................................................................................3-10DMA Reload Register Selection...............................................................................................3-11DMA Interrupts...................................................................................................................3-12DMA Synchronization Events..................................................................................................3-13DMA Channel Interrupt Selection..............................................................................................3-14Device ID Register(CSIDR)Bits................................................................................................3-15CPU Memory-Mapped Registers................................................................................................3-16Peripheral Memory-Mapped Registers for Each DSP Subsystem........................................................3-17McBSP Control Registers and Subaddresses.................................................................................3-18DMA Subbank Addressed Registers...........................................................................................3-19Interrupt Locations and Priorities................................................................................................5-1Input Clock Frequency Characteristics.........................................................................................5-2Clock Mode Pin Settings for the Divide-By-2and By Divide-By-4Clock Options.......................................5-3Divide-By-2and Divide-By-4Clock Options Timing Requirements.......................................................5-4Divide-By-2and Divide-By-4Clock Options Switching Characteristics...................................................5-5Multiply-By-N Clock Option Timing Requirements..........................................................................5-6Multiply-By-N Clock Option Switching Characteristics......................................................................5-7Memory Read Timing Requirements..........................................................................................5-8Memory Read Switching Characteristics.....................................................................................5-9Memory Write Switching Characteristics.....................................................................................5-10I/O Read Timing Requirements................................................................................................5-11I/O Read Switching Characteristics...........................................................................................5-12I/O Write Switching Characteristics............................................................................................5-13Ready Timing Requirements for Externally Generated Wait States......................................................5-14Ready Switching Characteristics for Externally Generated Wait States..................................................5-15HOLD and HOLDA Timing Requirements....................................................................................5-16HOLD and HOLDA Switching Characteristics...............................................................................5-17Reset,BIO,Interrupt,and MP/MC Timing Requirements..................................................................5-18Instruction Acquisition(IAQ)and Interrupt Acknowledge(IACK)Switching Characteristics...........................List of Tables7TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 5-19External Flag(XF)and TOUT Switching Characteristics...................................................................5-20McBSP Transmit and Receive Timing Requirements.......................................................................5-21McBSP Transmit and Receive Switching Characteristics..................................................................5-22McBSP General-Purpose I/O Timing Requirements........................................................................5-23McBSP General-Purpose I/O Switching Characteristics...................................................................5-24McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=0).................................5-25McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=0).............................5-26McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=0).................................5-27McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=0).............................5-28McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=1).................................5-29McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=1).............................5-30McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=1).................................5-31McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=1).............................5-32HPI8Mode Timing Requirements.............................................................................................5-33HPI8Mode Switching Characteristics..........................................................................................5-34HPI16Mode Timing Requirements............................................................................................5-35HPI16Mode Switching Characteristics.......................................................................................6-1Thermal Resistance Characteristics............................................................................................8Submit Documentation Feedback List of Tables1TMS320VC5416FeaturesTMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008Reads•Advanced Multibus Architecture With ThreeSeparate16-Bit Data Memory Buses and One•Arithmetic Instructions With Parallel Store and Program Memory Bus Parallel Load•40-Bit Arithmetic Logic Unit(ALU)Including a•Conditional Store Instructions40-Bit Barrel Shifter and Two Independent•Fast Return From Interrupt 40-Bit Accumulators•On-Chip Peripherals•17-×17-Bit Parallel Multiplier Coupled to a–Software-Programmable Wait-State 40-Bit Dedicated Adder for Non-Pipelined Generator and ProgrammableSingle-Cycle Multiply/Accumulate(MAC)Bank-SwitchingOperation–On-Chip Programmable Phase-Locked •Compare,Select,and Store Unit(CSSU)for the Loop(PLL)Clock Generator With External Add/Compare Selection of the Viterbi Operator Clock Source–One16-Bit Timer•Exponent Encoder to Compute an Exponent–Six-Channel Direct Memory Access(DMA) Value of a40-Bit Accumulator Value in aControllerSingle Cycle–Three Multichannel Buffered Serial Ports •Two Address Generators With Eight Auxiliary(McBSPs)Registers and Two Auxiliary Register–8/16-Bit Enhanced Parallel Host-Port Arithmetic Units(ARAUs)Interface(HPI8/16)•Data Bus With a Bus Holder Feature•Power Consumption Control With IDLE1,•Extended Addressing Mode for8M×16-Bit IDLE2,and IDLE3Instructions With Maximum Addressable External ProgramPower-Down ModesSpace•CLKOUT Off Control to Disable CLKOUT •128K×16-Bit On-Chip RAM Composed of:•On-Chip Scan-Based Emulation Logic,IEEE –Eight Blocks of8K×16-Bit On-ChipStd1149.1(JTAG)Boundary Scan Logic(1) Dual-Access Program/Data RAM•144-Pin Ball Grid Array(BGA)(GGU Suffix)–Eight Blocks of8K×16-Bit On-ChipSingle-Access Program RAM•144-Pin Low-Profile Quad Flatpack(LQFP)(PGE Suffix)•16K×16-Bit On-Chip ROM Configured forProgram Memory• 6.25-ns Single-Cycle Fixed-Point InstructionExecution Time(160MIPS)•Enhanced External Parallel Interface(XIO2)•8.33-ns Single-Cycle Fixed-Point Instruction •Single-Instruction-Repeat and Block-RepeatExecution Time(120MIPS) Operations for Program Code• 3.3-V I/O Supply Voltage(160and120MIPS)•Block-Memory-Move Instructions for BetterProgram and Data Management• 1.6-V Core Supply Voltage(160MIPS)•Instructions With a32-Bit Long Word Operand• 1.5-V Core Supply Voltage(120MIPS)(1)IEEE Standard1149.1-1990Standard-Test-Access Port and •Instructions With Two-or Three-OperandBoundary Scan ArchitectureTMS320C54x,TMS320are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©1999–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.。
超大规模集成电路秋段成华老师第四次作业
1.Shown below are buffer-chain designs.(1) Calculate the minimum delay of a chain of inverters for the overall effectivefan-out of 64/1.(2) Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 Vpower supply, design a circuit simulation scheme to verify them with their correspondent parameters of N, f, and t p.N=3.6 ∴N=3.246(1)γ=1 F=64∴f=√F所以最佳反相器数目约为3通过仿真可以得到tphl=1.3568E-11 tplh=1.7498E-11 tp0=1.5533E-11(2)N=1时，tphl= 5.2735E-10 tplh= 8.1605E-10 tpd= 6.7170E-10N=2时，tplh=2.2478E-10 tphl=2.5567E-10 tpd=2.4023E-10N=3时，tphl=2.0574E-10 tplh=2.1781E-10 tpd=2.1178E-10N=4时，tplh=2.1579E-10 tphl=2.2189E-10 tpd=2.1884E-10从仿真结果可以看出N=3或者N=4时延迟时间最优，且N=2、3、4得到的仿真延迟时间与理论推导的时间比较接近，比例基本上是18、15、15.3，而N=1时仿真得到的延迟时间远小于理论推导的时间，但是最优结果依旧是N=3,f=4,tp=15。
* SPICE INPUT FILE: Bsim3demo1.sp--a chain of inverters.param Supply=1.8.lib 'C:\synopsys\Hspice_A-2007.09\tsmc018\mm018.l' TT.option captab.option list node post measout.tran 10p 6000p************************************************************.param tdval=10p.meas tran tplh trig v(in) val=0.9 td=tdval rise=2+targ v(out) val=0.9 rise=2.meas tran tphl trig v(in) val=0.9 td=tdval fall=2+targ v(out) val=0.9 fall=2.meas tpd param='(tphl+tplh)/2'*macro definitions**************************************************************nmos1.subckt nmos1 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=0.4u ad=0.2p^2 pd=0.4u as=0.2p^2 ps=0.4u.ends nmos1**pmos1*.subckt pmos1 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p^2 pd=0.8u as=0.4p^2 ps=0.8u.ends pmos1*.subckt inv1 in outxmn out in Gnd nmos1xmp out in Vcc pmos1vcc Vcc Gnd Supply.ends inv1**nmos2*.subckt nmos2 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=1.12u ad=0.56p^2 pd=1.12u as=0.56p^2 ps=1.12u .ends nmos2**pmos2*.subckt pmos2 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=2.24u ad=1.12p^2 pd=2.24u as=1.12p^2 ps=2.24u .ends pmos2*.subckt inv2 in outxmn out in Gnd nmos2xmp out in Vcc pmos2vcc Vcc Gnd Supply.ends inv2**nmos3*.subckt nmos3 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=3.2u ad=1.6p^2 pd=3.2u as=1.6p^2 ps=3.2u.ends nmos3**pmos3.subckt pmos3 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=6.4u ad=3.2p^2 pd=6.4u as=3.2p^2 ps=6.4u.ends pmos3*.subckt inv3 in outxmn out in Gnd nmos3xmp out in Vcc pmos3vcc Vcc Gnd Supply.ends inv3**nmos4*.subckt nmos4 n1 n2 n3mn n1 n2 n3 Gnd nch l=0.2u w=9.04u ad=4.52p^2 pd=9.04u as=4.52p^2 ps=9.04u.ends nmos4**pmos4*.subckt pmos4 p1 p2 p3mp p1 p2 p3 Vcc pch l=0.2u w=18.08u ad=9.04p^2 pd=18.08u as=9.04p^2 ps=18.08u .ends pmos4*.subckt inv4 in outxmn out in Gnd nmos4xmp out in Vcc pmos4vcc Vcc Gnd Supply.ends inv4*main circuit netlistxinv1 in out1 inv1xinv2 out1 out2 inv2xinv3 out2 out3 inv3xinv4 out3 out inv4cl out Gnd 154.24fVin in Gnd 0.9 pulse(0.0 1.8 219p 40p 40p 1100p 2400p).print tran v(in) v(out).end2.Consider the logic network below, which may represent the critical path of a morecomplex logic block. The output of the。
中国最先进集成电路芯片工艺指标
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Application_note_for_customized_cells
T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010Application Note for Customized Device inTSMC PDK4/21/2004 v0.1IntroductionThis document is an application note for TSMC PDK users who want to add customized devices or 3rd IP into TSMC PDK. There are three parts for users from data preparation, adding devices flow, to design flow.1. Data preparationLayoutNetlist or model i. Simulation netlist for IP or model for device ii. LVS netlist for IP or device iii. Pin order, name and position2. Add customized devices into TSMC PDK Layout view Symbol viewSimulation views (hpsiceS, spectre, ads, eldo ….) LVS views (auCdl, auLvs ..)3. Design flow for customized devicesSchematic entry Artist simulationVirtuosoXL layout driven flow Assura LVS flow Assura RCX flow Assura Extract view Calibre LVS flow Calibre RCX flowThe limitations of this method are1. Parameterized device is not includes in the document.2. The black box flow will skip the parasitic RC which over or near the customized cells._________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/20101. Data PreparationLayoutAfter the layouts ready, user needs to stream them into TSMC PDK library by using TSMC virtuoso tech file. And the cell name must be assigned to a corresponding name. There are two important steps need to be added in the layout.1. Create shape pin, the pin layer number must be the same as input/output layer. To add the pin layer is essential for Virtuoso XL and Assura LVS.2. Create label pin, the labels are used for Hercules/Calibre/Assura LVS recognized. User needs to follow TSMC layer definition to add corresponding label layer. For example, metal1’s label layer is ("METAL1" "pin"). Those names must be all the same as symbol._________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010 Netlist or modelIf the customized cell is a primitive device, it is necessary to prepare corresponding simulation model and LVS sub-circuit. The following is an example for a customized devicea. model for my_ind cellsubckt my_ind PLUS MINUSR1 (PLUS MINUS) resistor r=1000ends my_ind b. LVS sub-circuit.SUBCKT my_ind PLUS MINUS .ENDSNOTE : The cell name, pin names and order of pin name must be all the same at any place._________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/20102. Add customized devices into TSMC PDKLayout viewStream into TSMC PDK library as a cell, then and add shape pin and label.Please refer to layout of data preparation section. Symbol viewUse Virtuoso Symbol Editor to edit a symbol view, the pins must be correctly assigned. And the pin name must be the same with others.Other views (spectre, hspiceS, auLVS, auCdl ….)User needs to copy symbol view to other views, then loading a corresponding CDF (component description file). The sample CDF file is attached below. The red ink means they need to be modified case by case./****************************************************/ LIBRARY = "my_lib " CELL = "my_ind "_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010/****************************************************/let( ( libId cellId cdfId )unless( cellId = ddGetObj( LIBRARY CELL ) error( "Could not get cell %s." CELL ) )when( cdfId = cdfGetBaseCellCDF( cellId ) cdfDeleteCDF( cdfId ) )cdfId = cdfCreateBaseCellCDF( cellId ) ;;; Parameters cdfCreateParam( cdfId?name "model"?prompt "Model name" ?defValue "my_ind " ?type "string" ?display "t" ?editable "nil" ?parseAsCEL "yes" )cdfCreateParam( cdfId?name "macro"?prompt "Hspice S model name" ?defValue "my_ind " ?type "string" ?display "nil" ?editable "nil" ?parseAsCEL "yes" )cdfCreateParam( cdfId?name "macroArgumentStyle" ?prompt "macroStyles" ?defValue "hspiceS" ?type "string" ?display "nil" ?editable "nil" ?parseAsCEL "yes"_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010 ) ;;; Simulator Information cdfId->simInfo = list( nil ) cdfId->simInfo->Cdl = '( nilnetlistProcedure tsmcCdlSubcktCall componentName my_indtermOrder (PLUS MINUS ) namePrefix "X"modelName "model" )cdfId->simInfo->auCdl = '( nilnetlistProcedure tsmcCdlSubcktCall componentName my_indtermOrder (PLUS MINUS ) namePrefix "X"modelName "model" )cdfId->simInfo->auLvs = '( nilnetlistProcedure tsmcCdlSubcktCall componentName my_indtermOrder (PLUS MINUS ) namePrefix "X"modelName "model" )cdfId->simInfo->hspiceS = '( nil otherParameters (macro)termOrder (PLUS MINUS ) netlistProcedure ansHspiceSsubcktCall componentName subcircuit macroArguments nil namePrefix "X" )cdfId->simInfo->spectre = '( nil otherParametes (model)termOrder (PLUS MINUS ) termMapping (nil PLUS ":1" MINUS ":2") )_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010 ;;; PropertiescdfId->formInitProc = "" cdfId->doneProc = "" cdfId->buttonFieldWidth = 340 cdfId->fieldHeight = 35 cdfId->fieldWidth = 350 cdfId->promptWidth = 175cdfId->paramLabelSet = "-model n r widthW " cdfId->opPointLabelSet = "cap "cdfId->modelLabelSet = "c " cdfSaveCDF( cdfId ))_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T S MC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/20103. Design flowSchematic EntryJust use the customized cells as normal device. Instance customized cells then connect them with other cells in a schematic. The following schematic is a simple example. It will be used as a demo case for explaining design flow.Artist simulation (analog design environment)Include the customized model when doing simulation. The following spectre and spice netlists are generated from Cadence Analog Enviroment, it shows us the connectivity are all correct.Spectre netlist….include "/export/home/jwchen/PDK/project/IP_solution/data/my_ind.scs"// Library name: test// Cell name: test_my_ind // View name: schematic I1 (net6 net9) my_ind_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010R1 (net9 OUT) rnpo1w l=9.36u w=420.0n mf=(1)R0 (IN net6) rnpo1rpo l=8.92u w=2u mf=(1)…Spice netlistXI1 NET6 NET9 MY_INDXR1 NET9 OUT RNPO1W W=420E-9 L=9.36E-6 MF=1XR0 IN NET6 RNPO1RPO W=2E-6 L=8.92E-6 MF=1VirtuosoXL layout driven flowThe layout driven flow can work well. One important thing needs to take care is, the interconnect must connect to pin shape. The following layout is modified to let interconnect connect to pin shape after auto-router.Assura LVS flow for DFII flow and batch modei. Need to assign “blackBoxCell” to let LVS deck know it should not beextracted inside of the customized cell.ii. If the LVS deck has not defined pinLayer before, users have to modifyit. The pinLayer is essential for black box. (Please refer Cadence manual for the detail)_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T S MC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010extract.rullayerDefs( "df2"…metal2_player = pinLayer( "METAL2") metal3_player = pinLayer( "METAL3")…)layerDefs( "gds2"…metal2_player = pinLayer( 18)metal3_player = pinLayer( 28)…)M2=geomOr(M2 metal2_player)M3=geomOr(M3 metal3_player)…In batch model, the LVS.rsf need to be modified as following_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n330194T si n g h u a U n i v e r s i t y 01/25/2010LVS.rsfavParameters(..?blackBoxCell ("my_ind")..?textPriOnly nil ..)Assura RCX flowUse the same setup method as Assura LVSExtracted viewThe Assura extracted view will use layout view as symbol. The following picture is extracted view and extracted simulation netlist.Calibre LVS flowi. Output a CDL netlist then include LVS sub-circuit. The complete LVSis as below “test_my_ind.cdl”.ii. Insert a line “LVS BOX cell_name” into LVS deckiii.Different pins should not be shorted inside of blackbox, user can use_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010RMDUMMY to let LVS avoid the pin short problem.Test_my_ind.cdl.SUBCKT test_my_ind IN OUT *.PININFO IN:I OUT:I XI1 net6 net9 my_indRR1 net9 OUT 164.914 $[NS]RR0 IN net6 1.30232K $[NR].ENDS.SUBCKT my_ind PLUS MINUS .ENDS LVS deck…LVS BOX my_ind …Calibre RCX flowi. Insert a line “LVS BOX cell_name” into RCX deck ii. Prepare PEX X-Cells file iii. Change extract type to gate level extractionThe Calire RCX extracted netlist is as below, customized cell has been extracted as a sub-circuit..subckt test_my_ind IN OUT *xRR0 IN net6 rnpo1rpo $w=2e-06 $l=8.92e-06xRR1 net9 OUT rnpo1w $w=4.2e-07 $l=9.36e-06xI1 net6 net9 MY_IND c_3 IN 0 2.46362f c_6 net6 0 2.04346f c_7 net9 0 0.674213f c_10 OUT 0 2.94089f *_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________T SMC C o n f i d e n t i a l I n f o r m a t i o n 330194T si n g h u a U n i v e r s i t y 01/25/2010.include test_my_list.TEST_MY_IND.pxi *_________________ TSMC Confidential Information 330194 Tsinghua University 01/25/2010 _________________。
IBM与TSMC在32纳米技术上展开竞争
种应 变工 程手段 ，而这 同我们获得 低功 耗移动产 品的方案
正好相反 ，用户期待的正是成本非常低 的方案 。”
Ｉ Ｍ的工 程人员介绍 ，由于高ｋ 以在 ３ ｍ Ｂ 可 ２ｎ 工艺 中带
论的却是如果在３ ｍ工艺代 ，Ｉ ２ｒ ｉ ＢＭ及其伙伴采用先制作栅 来大量好处 ，很多客户将跳过４／ ｍ ５ ０ｎ 技术代而直接进入３ ４ ２
ａ 工艺 。Ｐ ｔ ｎ ｂ ｍ ａ ｏ ￣充说 ，３ ｍ ｔ ２ｎ 的工艺流程还考虑到了易于 Ｋ ａ ｌ： “ ｈｒＪ 我们的集成方法可以让流程适用于４或４ １ ｅ￣ ５ ＠
有 引入 其他 流程 。这与其他高ｌ金属栅 方案有着极大不同 ， √
低功耗移动 市场 已成为高速增长的市场分支 ， Ｂ Ｉ Ｍ副总 向２ 半节点转移的便利性 。 ８ｍ ａ
了获得不错 的性能 ，他们必须采用很薄 的氧化层 ，而这将增
３ ｍ ２ａ 技术世代如果采用氮氧化技术 ，那么短沟效应将 变得更 加显著 。Ｓｅｇ ｎ ｔ ｅ＇ ｅ ￣绍说 ： “ 是控制短沟的关键 ， 高ｋ
加漏电。”他还指 出，埋置式 Ｓ ｅ ｉ 应变技术也会增加成本。 Ｇ
ＩＭ高ｋ Ｂ ／ 金属栅技术的项 目 经理Ｍｕ ｅ ｈｒ ： “ ｋｓ Ｋ ａ 说 我 而使用氮 氧化层 则短 沟效应将 是个大麻 烦 。我们可 以进 行 ｈ ｅ 们在 引入一个重要元素 ：高ｋ 料 。坚持使用氧化多 晶方 法 栅长 的缩 减 以及 多 晶硅 的缩 减 ，并 比氮 氧化技术 获得更 好 材
Ｐｔ ｎ ａｔ 认为Ｔ ＭＣ ｏ Ｓ 是在倒退 ，并指 出 “２ａ ３ ｍ工艺 中多晶 度 （ ） 以达到ｌＡ。更薄的栅氧化层厚度提 高了性能 ， Ｔ 可 ４
氮氧化层将比高ｋ ／ 金属栅极还要 昂贵”。在３ 采用多晶氮 可 以将栅长降低 ￣３ ｍ，同时还可将Ｓ Ａ ２ｍ ａ ］ ｎ １０ Ｒ Ｍ的Ｖ 保持在优 氧化层的公 司将不得不转向三次氧化工艺 ，他补充道 ： “ 为 化的量级。可以将接触孔靠得更近而不会出现短路的危险。
TSM103_03资料
ELECTRICAL CHARACTERISTICS
Symbol Parameter Total Supply Current, excluding Current in the Voltage Reference VCC+ = 5V, no load Tmin. < Tamb < Tmax. VCC+ = 30V, no load Tmin. < Tamb < Tmax Min. Typ. Max. Unit
Package Part Number TSM103I/AI Temperature Range D -40°C, +105°C •
PIN CONNECTIONS (top view)
Output 1
1
OP1
Inverting Input 1 2 Non-inverting Input 1 3 V - 4 CC
ICC
1.2 0.7 2
mA
2/9
元器件交易网
TSM103/A
OPERATOR 2 (independent op-amp) VCC+ = +5V, VCC = Ground, V o = 1.4V,T amb = 25°C (unless otherwise specified)
3/9
元器件交易网
TSM103/A
OPERATOR 1 (op-amp with non-inverting input connected to the internal Vref) VCC+ = +5V, VCC- = Ground, Tamb = 25°C (unless otherwise specified)
TPS53311RGTT,TPS53311RGTT,TPS53311RGTT,TPS53311RGTR, 规格书,Datasheet 资料
VIN2.9VVDD2.9V toENSYNCTPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011 3-A Step-Down Regulator with Integrated SwitcherCheck for Samples:TPS53311FEATURES LOW VOLTAGE APPLICATIONS•5-V Step-down Rail•95.5%Maximum Efficiency• 3.3-V Step-down Rail•Continuous3-A Output Current•Supports All MLCC Output CapacitorDESCRIPTION•SmoothPWM™Auto-Skip Eco-mode™forThe TPS53310provides a fully integrated3-V to5-V Light-Load EfficiencyV IN integrated synchronous FET converter solution •Voltage Mode Control with16total components,in200mm2of PCB area.Due to the low R DS(on)and TI Proprietary •Supports Master-Slave Interleaved OperationSmoothPWM™skip mode of operation,it enables •Synchronization up to±20%of Nominal95.5%peak efficiency,and over90%efficiency atFrequencyloads as light as100mA.It requires only two22-µF •Conversion Voltage Range Between2.9V and ceramic output capacitors for a power-dense,3-A6.0V solution.•Soft-Stop Output Discharge During Disable The TPS53311features a 1.1-MHz switching •Adjustable Output Voltage Ranging Between frequency,SKIP mode operation support,pre-biasstartup,internal softstart,output soft discharge,0.6V and0.84V×V INinternal VBST switch,power good,EN/input UVLO,•Overcurrent,Overvoltage andovercurrent,overvoltage,undervoltage and Over-Temperature Protectionover-temperature protections and all ceramic output •Small,3mm×3mm,16-Pin QFN Package capacitor support.It supports supply voltage from2.9V to3.5V and conversion voltage from2.9V to •Open-Drain Power Good Indication6.0V,and output voltage is adjustable from0.6V to •Internal Boot Strap Switch0.84V×V IN.•Low R DS(on),24mΩwith3.3-V Input and19-mΩThe TPS53311is available in the3mm×3mm with5-V Input16-pin QFN package(Green RoHs compliant and Pb •Supports Pre-Bias Start-Up Functionality free)and operates between–40°C and85°C.TYPICAL APPLICATION CIRCUITPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SmoothPWM,Eco-mode are trademarks of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2010–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TPS53311SLUSA41A–JUNE2010–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ORDERING INFORMATION(1)(2)ORDERABLE MINIMUMT A PACKAGE PINS OUTPUT SUPPLY ECO PLANNUMBER QUANTITYTPS53311RGTR16Tape and reel3000Plastic QFN Green(RoHS and –40°C to85°C(RGT)no Pb/Br)TPS53311RGTT16Mini reel250(1)For the most current package and ordering information see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)VALUE UNITMIN MAXVIN,EN–0.37VBST–0.317Input voltage range V VBST(with respect to SW)–0.37FB,PS,VDD–0.3 3.7DC–17SWPulse<20ns,E=5μJ–310Output voltage range PGD–0.37VCOMP,SYNC–0.3 3.7PGND–0.30.3Human Body Model(HBM)2000 Electrostatic Discharge V Charged Device Model(CDM)500Ambient temperature T A–4085˚CStorage temperature T stg–55150˚CJunction temperature T J–40150˚CLead temperature1,6mm(1/16inch)from case for10seconds300˚C (1)Stresses beyond those listed under“absolute maximum ratings”may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2Submit Documentation Feedback Copyright©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311TPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011RECOMMENDED OPERATING CONDITIONSVALUEUNITMIN NOM MAXVIN 2.96VDD 2.9 3.3 3.5VBST–0.113.5Input voltage range VVBST(with respect to SW)–0.16EN–0.16FB,PS–0.1 3.5SW–1 6.5PGD–0.16Output voltage range VCOMP,SYNC–0.1 3.5PGND–0.10.1Junction temperature range,T J–40125°C PACKAGE DISSIPATION RATINGSTHERMAL IMPEDANCE,THERMAL IMPEDANCE,THERMAL IMPEDANCE, PACKAGEJUNCTION TO THERMAL PAD JUNCTION TO CASE JUNCTION TO AMBIENT 16-Pin Plastic QFN(RGT)5°C/W16°C/W40°C/WCopyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TPS53311TPS53311SLUSA41A–JUNE2010–REVISED ELECTRICAL CHARACTERISTICSover recommended free-air temperature range,V IN=3.3V,V VDD=3.3V,PGND=GND(Unless otherwise noted).PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY:VOLTAGE,CURRENTS,and UVLOV IN VIN supply voltage Nominal input voltage range 2.9 6.0VI VINSDN VIN shutdown current EN='LO'3µAV UVLO VIN UVLO threshold Ramp up;EN='HI' 2.8VV UVLOHYS VIN UVLO hysteresis VIN UVLO Hysteresis130mVV DD Internal circuitry supply voltage Nominal3.3-V input voltage range 2.9 3.3 3.5VI DDSDN VDD shut down current EN='LO'5µAI DD Standby current EN='HI',no switching 2.2 3.5mAV DDUVLO 3.3V UVLO threshold Ramp up;EN=’HI’ 2.8VV DDUVLOHYS 3.3V UVLO hysteresis75mV VOLTAGE FEEDBACK LOOP:VREF AND ERROR AMPLIFIERV VREF VREF Internal precision reference voltage0.6V0°C≤T A≤85°C–1%1%TOLV REF VREF Tolerance–40°C≤T A≤85°C–1.25% 1.25%UGBW(1)Unity gain bandwidth14MHzA OL(1)Open loop gain80dBI FBINT FB input leakage current Sourced from FB pin30nAOutput sinking and sourcingI EAMAX(1)C COMP=20pF5mAcurrentSR(1)Slew rate5V/µs OCP:OVER CURRENT AND ZERO CROSSINGWhen I OUT exceeds this threshold for4I OCPL Overcurrent limit on upper FET consecutive cycles.V IN=3.3V, 4.2 4.5 4.8AV OUT=1.5V with1-µH inductor,T A=25°CImmediately shut down when sensed currentOne time overcurrent latch offI OCPH reach this value.V IN=3.3V, 4.8 5.1 5.5Aon the lower FETV OUT=1.5V with1-µH inductor,T A=25°CZero crossing comparatorV ZXOFF(1)PGND–SW,SKIP mode–4.5–3.0–1.5mV internal offsetPROTECTION:OVP,UVP,PGD,AND INTERNAL THERMAL SHUTDOWNOvervoltage protectionV OVP Measured at FB wrt.VREF114%117%120% threshold voltageUndervoltage protectionV UVP Measured at FB wrt.VREF80%83%86% threshold voltageV PGDL PGD low threshold Measured at FB wrt.VREF80%83%86%V PGDU PGD upper threshold Measured at FB wrt.VREF.114%117%120%Minimum Vin voltage for valid Measured at V IN with1-mA(or2-mA)sinkV INMINPG1V PGD at start up.current on PGD pin at start upTHSD(1)Thermal shutdown Latch off controller,attempt soft-stop130140150°C THSD HYS(1)Thermal Shutdown hysteresis Controller restarts after temperature has dropped40°C (1)Ensured by design.Not production tested.4Submit Documentation Feedback Copyright©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311TPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011ELECTRICAL CHARACTERISTICS(continued)over recommended free-air temperature range,V IN=3.3V,V VDD=3.3V,PGND=GND(Unless otherwise noted).PARAMETER CONDITIONS MIN TYP MAX UNIT LOGIC PINS:I/O VOLTAGE AND CURRENTV PGPD PGD pull down voltage Pull-down voltage with4-mA sink current0.20.4VI PGLK PGD leakage current Hi-Z leakage current,apply3.3-V in off state–202µAR ENPU Enable pull up resistor 1.35MΩV ENH EN logic high threshold 1.10 1.18 1.30VV ENHYS EN hysteresis0.180.24VLevel1to level2(2)0.12Level2to level30.4PS THS PS mode threshold voltage Level3to level40.8VLevel4to level5 1.4Level5to level6 2.2I PS PS source10-µA pull-up current when enabled.81012µAf SYNCSL Slave SYNC frequency range Versus nominal switching frequency–20%20%PW SYNC SYNC low pulse width110nsI SYNC SYNC pin sink current10µAV SYNCTHS(3)SYNC threshold Falling edge 1.0VV SYNCHYS(3)SYNC hysteresis0.5V BOOT STRAP:VOLTAGE AND LEAKAGE CURRENTI VBSTLK VBST leakage current V IN=3.3V,V VBST=6.6V,T A=25°C1µA TIMERS:SS,FREQUENCY,RAMP,ON-TIME AND I/O TIMINGt SS_1Delay after EN asserting EN='HI',master or HEF mode0.2mst SS_2Delay after EN asserting EN='HI',slave waiting time0.5mst SS_3Soft-start ramp-up time Rising from V SS=0V to V SS=0.6V0.4msRising from V SS=0V to V SS=0.6V,t PGDENDLY PGD startup delay time0.4msfrom V SS reaching0.6V to V PGD going highOvervoltage protection delayt OVPDLY Time from FB out of+20%of VREF to OVP fault 1.0 1.7 2.5µs timeUndervoltage protection delayt UVPDLY Time from FB out of-20%of VREF to UVP fault11µs timef SW Switching frequency control Forced CCM mode0.99 1.1 1.21MHzRamp amplitude(3) 2.9V<V IN<6.0V V IN/4VFCCM mode or DE mode100140t MIN(off)Minimum OFF time nsHEF mode175250Maximum duty cycle,FCCM84%89%mode and DE modeD MAX f SW=1.1MHz,0°C≤T A≤85°CMaximum duty cycle,HEF75%81%modeSoft-discharge transistorR SFTSTP V EN=Low,V IN=3.3V,V OUT=0.5V60Ωresistance(2)See PS pin description for levels.(3)Ensured by design.Not production tested.Copyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):TPS533111234EN S WSYNC S WPGD S WVBSTP S121110916VDD P G N DAGND P G N DFB V I NCOMPV I N1514135678TPS53311RGT Package (Top View)TPS53311SLUSA41A –JUNE 2010–REVISED MARCH 2011PIN FUNCTIONSPINI/O (1)DESCRIPTIONNAME NO.AGND 11G Device analog ground terminal.COMP 9O Error amplifier compensation terminal.Type III compensation method is recommended for stability.EN 1I Enable.Internally pulled up to VDD with a 1.35-M Ωresistor.FB 10I Voltage feedback.Also used for OVP,UVP and PGD determination.PGD 3O Power good output flag.Open drain output.Pull up to an external rail via a resistor.15PGNDPIC power GND terminal.16Mode configuration pin (with 10µA current):Connecting to ground:Forced CCM slavePulled high or floating (internal pulled high):Forced CCM master PS 8IConnect with 24.3k Ωto GND:DE slave Connect with 57.6k Ωto GND:HEF mode Connect with 105k Ωto GND :reserved mode Connect with 174k Ωto GND:DE master.Synchronization signal for input interleaving.Master SYNC pin sends out 180°out-of-phase signal to slave SYNC 2BSYNC.SYNC frequency must be within ±20%of slave nominal frequency.5SW 6B Output inductor connection to integrated power devices.7VBST 4P Supply input for high-side MOSFET (bootstrap terminal).Connect capacitor from this pin to SW terminal.VDD 12P Input bias supply for analog functions.13VIN PGate driver supply and power conversion voltage.14(1)I –Input;B –Bidirectional;O –Output;G –Ground;P –Supply (or Ground)6Submit Documentation FeedbackCopyright ©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311FBCOMPSYNCVBSTSWPGNDVDD EN PS PGD AGNDVINVINPGNDSWUDG-10028SWTPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011FUNCTIONAL BLOCK DIAGRAMCopyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TPS533110.51.02.02.53.01.5I OUT –Output Current –Ah –E f f i c i e n c y –%84800.51.02.02.53.01.582969294908688I OUT –Output Current –A0.51.02.02.53.01.5I OUT –Output Current –Ah –E f f i c i e n c y –%0.51.02.02.53.01.5I OUT –Output Current –A848082969294908688h –E f f i c i e n c y –%TPS53311SLUSA41A –JUNE 2010–REVISED MARCH 2011TYPICAL CHARACTERISTICSInductor IN06142(1µH,5.4m Ω)is used.Figure 1.Efficiency vs.Output Current,Skip Mode,V IN =Figure 2.Efficiency vs.Output Current,FCCM,V IN =3.3V3.3VFigure 3.Efficiency vs.Output Current,Skip Mode,V IN =5Figure 4.Efficiency vs.Output Current,FCCM,V IN =5VV8Submit Documentation FeedbackCopyright ©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311–0.50.51.02.02.53.01.50.50.30.1–0.1Output Current (A)O u t p u t V o l t a g e C h a n g e (%)–0.3–40–1020658012535T A –Ambient Temperature –°C0.5900.5800.5850.6200.6100.6150.6050.5950.600V F B –F e e d b a c k V o l t a g e –V–25550951100.01100.11.01010k1000100Output Current (A)F r e q u e n c y (k H z )0.01100.11.01010k1000100Output Current (A)F r e q u e n c y (k H z )TPS53311SLUSA41A –JUNE 2010–REVISED MARCH 2011TYPICAL CHARACTERISTICS (continued)Inductor IN06142(1µH,5.4m Ω)is used.Figure 5.Feedback Voltage vs.Ambient TemperatureFigure 6.Output Voltage Change vs.Output CurrentFigure 7.Frequency vs.Output Current at V IN =3.3VFigure 8.Frequency vs.Output Current at V IN =5.0VCopyright ©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TPS53311HEF Mode VIN=3.3VI OUT =0AEN(5V/div)VOUT(1V/div)PGD(5V/div)t–Time–200m s/divHEF ModeVIN=3.3VIOUT=0AEN(5V/div)VOUT(1V/div)PGD(5V/div)t–Time–200m s/div0.5V pre-biasedHEF Mode VIN=3.3VI OUT =0AEN(5V/div)VOUT(1V/div)PGD(5V/div)t–Time–4ms/div20304050607080900.00.5 1.0 1.5 2.0 2.5 3.0Output Current(A)Temperature(C)TPS53311SLUSA41A–JUNE2010–REVISED TYPICAL CHARACTERISTICS(continued)Inductor IN06142(1µH,5.4mΩ)is used.Figure9.Normal Start Up Waveform Figure10.Pre-Bias Start Up Waveform Figure11.Soft-Stop Waveform Figure12.Safe Operating Area10Submit Documentation Feedback Copyright©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311L1ENSYNC V INTPS53311SLUSA41A –JUNE 2010–REVISED MARCH 2011APPLICATION INFORMATIONAPPLICATION CIRCUIT DIAGRAMFigure 13.Typical 3.3-V input Application Circuit DiagramOVERVIEWThe TPS53311is a high-efficiency switching regulator with two integrated N-channel MOSFETs and is capable of delivering up to 3A of load current.The TPS53311provides output voltage between 0.6V and 0.84×V IN from 2.9V to 6.0V wide input voltage range.This device employs five operation modes to fit various application needs.The master/slave mode enables a two-phase interleaved operation to reduce input ripple.The skip mode operation provides reduced power loss and increases the efficiency at light load.The unique,patented PWM modulator enables smooth light load to heavy load transition while maintaining fast load transient.OPERATION MODEThe TPS53311offers five operation modes determined by the PS pin connections listed in Table 1.Table 1.Operation Mode SelectionPS PIN CONNECTIONOPERATION MODEAUTO-SKIP AT LIGHT LOADMASTER/SLAVE SUPPORTGND FCCM Slave Slave 24.3k Ωto GND DE Slave √Slave57.6k Ωto GND HEF Mode √174k Ωto GND DE Master √Master Floating or pulled to VDDFCCM MasterMasterIn forced continuous conduction mode (FCCM),the high-side FET is ON during the on-time and the low-side FET is ON during the off-time.The switching is synchronized to the internal clock thus the switching frequency is fixed.In diode emulation mode (DE),the high-side FET is ON during the on-time and low-side FET is ON during the off-time until the inductor current reaches zero.An internal zero-crossing comparator detects the zero crossing of inductor current from positive to negative.When the inductor current reaches zero,the comparator sends a signal to the logic control and turns off the low-side FET.Copyright ©2010–2011,Texas Instruments IncorporatedSubmit Documentation Feedback11Product Folder Link(s):TPS53311TPS53311SLUSA41A–JUNE2010–REVISED When the load is increased,the inductor current is always positive and the zero-crossing comparator does not send a zero-crossing signal.The converter enters into continuous conduction mode(CCM)when no zero-crossing is detected for two consecutive PWM pulses.The switching synchronizes to the internal clock and the switching frequency is fixed.In high-efficiency mode(HEF),the operation is the same as diode emulation mode at light load.However,the converter does not synchronize to the internal clock during CCM.Instead,the PWM modulator determines the switching frequency.LIGHT LOAD OPERATIONIn skip modes(DE and HEF)when the load current is less than one-half of the inductor peak current,the inductor current becomes negative by the end of off-time.During light load operation,the low-side MOSFET is turned off when the inductor current reaches zero.The energy delivered to the load per switching cycle is increased compared to the normal PWM mode operation and the switching frequency is reduced.The switching loss is reduced,thereby improving efficiency.In both DE and HEF mode,the switching frequency is reduced in discontinuous conduction mode(DCM).When the load current is0A,the minimum switching frequency is reached.The difference between V VBST and V SW must be maintained at a value higher than2.4V.FORCED CONTINUOUS CONDUCTION MODEWhen the PS pin is grounded or greater than2.2V,the TPS53311is operating in forced continuous conduction mode in both light-load and heavy-load conditions.In this mode,the switching frequency remains constant over the entire load range,making it suitable for applications that need tight control of switching frequency at a cost of lower efficiency at light load.SOFT STARTThe soft-start function reduces the inrush current during the start up sequence.A slow-rising reference voltage is generated by the soft-start circuitry and sent to the input of the error amplifier.When the soft-start ramp voltage is less than600mV,the error amplifier uses this ramp voltage as the reference.When the ramp voltage reaches 600mV,the error amplifier switches to a fixed600-mV reference.The typical soft-start time is400µs.POWER GOODThe TPS53311monitors the voltage on the FB pin.If the FB voltage is between83%and117%of the reference voltage,the power good signal remains high.If the FB voltage falls outside of these limits,the internal open drain output pulls the power good pin(PGD)low.During start-up,the input voltage must be higher than1V in order to have valid power good logic,and the power good signal is delayed for400µs after the FB voltage falls to within the power good limits.There is also10-µs delay during the shut down sequence.UNDERVOLTAGE LOCKOUT(UVLO)FUNCTIONThe TPS53311provides undervoltage lockout(UVLO)protection for both power input(V IN)and bias input(VDD) voltage.If either of them is lower than the UVLO threshold voltage minus the hysteresis,the device shuts off. When the voltage rises above the threshold voltage,the device restarts.The typical UVLO rising threshold is2.8 V for both V IN and V VDD.A hysteresis voltage of130mV for V IN and75mV for V VDD is also provided to prevent glitch.OVERCURRENT PROTECTIONThe TPS53311continuously monitors the current flowing through the high-side and the low-side MOSFETs.If the current through the high-side FET exceeds4.5A,the high-side FET turns off and the low-side FET turns on until the next PWM cycle.An overcurrent(OC)counter starts to increment each occurrence of an overcurrent event.The converter shuts down immediately when the OC counter reaches four.The OC counter resets if the detected current is less4.5A after an OC event.12Submit Documentation Feedback Copyright©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311TPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011Another set of overcurrent circuitry monitors the current flowing through low-side FET.If the current through the low-side FET exceeds5.1A,the overcurrent protection is enabled and immediately turns off both the high-side and the low-side FETs and shuts down the converter.The device is fully protected against overcurrent during both on-time and off-time.This protection is latched.Please refer to the TPS53310data sheet(SLUSA68)for information on hiccup overcurrent protection.OVERVOLTAGE PROTECTIONThe TPS53311monitors the voltage divided feedback voltage to detect overvoltage and undervoltage conditions. When the feedback voltage is greater than117%of the reference,the high-side MOSFET turns off and the low-side MOSFET turns on.The output voltage then drops until it reaches the undervoltage threshold.At that point the low-side MOSFET turns off and the device enters a high-impedance state.UNDERVOLTAGE PROTECTIONWhen the feedback voltage is lower than83%of the reference voltage,the undervoltage protection timer starts. If the feedback voltage remains lower than the undervoltage threshold voltage after10μs,the device turns off both the high-side and the low-side MOSFETs and goes into a high-impedance state.This protection is latched. OVERTEMPERATURE PROTECTIONThe TPS53311continuously monitors the die temperature.If the die temperature exceeds the threshold value (140˚C typical),the device shuts off.When the device temperature falls to40˚C below the overtemperature threshold,it restarts and returns to normal operation.OUTPUT DISCHARGEWhen the enable pin is low,the TPS53311discharges the output capacitors through an internal MOSFET switch between SW and PGND while high-side and low-side MOSFETs remain off.The typical discharge switch-on resistance is60Ω.This function is disabled when V IN is less than1V.MASTER/SLAVE OPERATION AND SYNCHRONIZATIONTwo TPS53311can operate interleaved when configured as master/slave.The SYNC pins of the two devices are connected together for synchronization.In CCM,the master device sends the180°out-of-phase pulse to the slave device through the SYNC pin,which determines the leading edge of the PWM pulse.If the slave device does not receive the SYNC pulse from the master device or if the SYNC connection is broken during operation, the slave device continues to operate using its own internal clock.In DE mode,the master/slave switching node does not synchronize to each other if either one of them is operating in DCM.When both master and slave enters CCM,the switching nodes of master and slave synchronize to each other.The SYNC pin of the slave device can also connect to external clock source within±20%of the1.1-MHz switching frequency.The falling edge of the SYNC triggers the rising edge of the PWM signal.Copyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback13Product Folder Link(s):TPS53311OUT 0.6R2R1V 0.6=´-()()-´=´´f IN OUT OUT L ripple SW INV V V 1I L V ()()()=++RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL V V V V ()()=´´L ripple RIPPLE C OUT SW I V 8C f ()()=´RIPPLE ESR L ripple V I ESR ()´=IN RIPPLE ESL V ESLV L()()()()a ´-=´´´2OUTL ripple RIPPLE DCM OUT SW L ripple I I V 2C f I ()()a =ON DCM ON CCM t t TPS53311SLUSA41A –JUNE 2010–REVISED MARCH 2011EXTERNAL COMPONENTS SELECTION1.DETERMINE THE VALUE OF R1AND R2The output voltage is programmed by the voltage-divider resistor,R1and R2shown in Figure 13.R1is connected between the FB pin and the output,and R2is connected between the FB pin and GND.The recommended value for R1is from 1k Ωto 5k Ω.Determine R2using equation in Equation 1.(1)2.CHOOSE THE INDUCTORThe inductance value should be determined to give the ripple current of approximately 20%to 40%of maximumoutput current.The inductor ripple current is determined by Equation 2:(2)The inductor also needs to have low DCR to achieve good efficiency,as well as enough room above peakinductor current before saturation.3.CHOOSE THE OUTPUT CAPACITOR(S)The output capacitor selection is determined by output ripple and transient requirement.When operating in CCM,the output ripple has three components:(3)(4)(5)(6)When ceramic output capacitors are used,the ESL component is usually negligible.In the case when multiple output capacitors are used,ESR and ESL should be the equivalent of ESR and ESL of all the output capacitor in parallel.When operating in DCM,the output ripple is dominated by the component determined by capacitance.It also varies with load current and can be expressed as shown in Equation 7.where•αis the DCM on-time coefficient and can be expressed in Equation 8(typical value 1.25)(7)(8)14Submit Documentation FeedbackCopyright ©2010–2011,Texas Instruments IncorporatedProduct Folder Link(s):TPS53311UDG-10055()=OUTIN rippleI I=OUTINVDV()´=´OUTIN rippleSW INI DVf C+´´=´æö+´+´++´´ç÷+èøOUTCO2OUT OUTLOAD1s C ESRG4L1s C(ESR DCR)s L CDCR R=f DPTPS53311 SLUSA41A–JUNE2010–REVISED MARCH2011Figure14.DCM V OUT Ripple Calculation4.CHOOSE THE INPUT CAPACITORThe selection of input capacitor should be determined by the ripple current requirement.The ripple current generated by the converter needs to be absorbed by the input capacitors as well as the input source.The RMS ripple current from the converter can be expressed in Equation9.where•D is the duty cycle and can be expressed as shown in Equation10(9)(10) To minimize the ripple current drawn from the input source,sufficient input decoupling capacitors should be placed close to the device.The ceramic capacitor is recommended because it provides low ESR and low ESL. The input voltage ripple can be calculated as shown in Equation11when the total input capacitance is determined.(11) PENSATION DESIGNThe TPS53311uses voltage mode control.To effectively compensate the power stage and ensure fast transient response,Type III compensation is typically used.The control to output transfer function can be described in Equation12.(12) The output L-C filter introduces a double pole which can be calculated as shown in Equation13.(13) The ESR zero can be calculated as shown in Equation14.Copyright©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback15Product Folder Link(s):TPS53311。
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良率较高。
tsmc台积电工艺库
7. RF RESISTOR MODELThe measurement results from the testchip are listed below:(a)Film ValidWidthRshMean/RangeUnit TC1TC2VC1VC2deltaW(µm)P+ Poly w/i Silicide W≥2.07.8±2.5Ω/sq2.88E-3 5.01E-7-7.89E-4 6.19E-3-0.051P+ Poly w/i Silicide0.18≤W<2.0 6.7± 3.5Ω/sq2.88E-3 5.01E-7-7.89E-4 6.19E-3-0.051N+ Poly w/i Silicide W≥2.07.4± 2Ω/sq2.92E-3 2.66E-7 1.35E-37.15E-3-0.065N+ Poly w/i Silicide0.18≤W<2.0 5.7 ± 4.2Ω/sq2.92E-3 2.66E-7 1.35E-37.15E-3-0.065N+ diff. w/o Silicide-59±5.8Ω/sq1.47E-38.32E-77.55E-4 1.97E-4-P+ diff. w/o Silicide-133±19Ω/sq1.43E-37.82E-7-1.19E-3-1.80E-4-*RSH values for N+ and P+ diff. w/i silicide are geometry dependent.*Rint and Rgrain of N+/P+ poly w/o silicide are described in the section “Resistor Equivalent Circuit Model”.*The resistor values can be written as follows for the resistors: N+/P+ poly w/i silicide, N+ diff, P+ diff:R= R0*[1+ VC1 * dV + VC2 * (dV)2]*[1+ TC1 * dT + TC2 * (dT)2]; where dT = T - Tnominal (25 °C).The resistors are function of temperature and the valid range is -40 °C ~ 125 °C.Also, the resistors are function of voltage and the valid range: N+/P+ poly w/i silicide : -3.3 ~ 3.3VN+ diff : 0 ~ 3.3VP+ diff : -3.3 ~ 0 VThe resistance is measured with one node of resistor grounded, whereas the other node is applied by V and dV is the voltage across the resistor.R0 is layout-dependent and calculated from sheet resistance. The equation is:R0 = Rsh * (L –deltaL)/ ( W – deltaW ) ; L is the drawn Length and W is the drawn width.*The resistor values can be written as follows for the resistors: N+/P+ poly w/o silicide:R= 2*Rc+2*Rint+2*Rgrain+Rp;where Rint=R2*[1+ VCX1 * |dV| + VCX2 * (dV)2]*[1+ TCX1 * dT + TCX2 * (dT)2]Rgrain=R3*[1+VCG1 * |dv|+VCG2* (dV)2]*[1+ TCG1 * dT + TCG2 * (dT)2]Rp=R0*[1+ VCP1 * |dV| + VCP2 * (dV)2]*[1+ TCP1 * dT + TCP2 * (dT)2]where dT = T - Tnominal (25 °C).The resistors are function of temperature and the valid range is -40 °C ~ 125 °C.Also, the resistors are function of voltage and the valid biasing range: N+/P+ poly w/o silicide : 0~0.5mA/um(2) Circuit Model for Rs of N+ and P+ Poly w/o Silicide ResistorThis section is to explain the interface resistor between RPO and Silicide. There is anadditional resistor Rend due to the depletion of dopant near the interface between RPO and Silicide. The following figure describes the circuit model of P+ Poly w/o Silicide Resistor.n1n2CoSi2Cross section of P+ or N+ Poly w/o Silicide Resistorn1n2Rcon Rcon Rend Rend Rp Circuit modelResistor Size(drawn):L,WR=2*Rcon+2*Rend+RpRcon=Rc/nc (note 1)Rend=Rint/(W-DeltaW)+RgrainRp=Rsh*(L-DeltaL)/(W-DeltaW)Note1:nc is Number of Contact, and itsdefault value is 2.。
TSMF1040中文资料
Document Number 8106116758TSMF1000TSMF1030TSMF1040TSMF1020High Speed IR Emitting Diode in SMD PackageDescriptionTSMF1000 series are high speed infrared emitting diodes in GaAlAs/GaAs/GaAlAs double hetero tech-nology (DH) molded in clear SMD package with dome lens.DH chip technology represents best performance for speed, radiant power, forward voltage and longterm reliability.Features•High speed•Extra high radiant power •Low forward voltage •Suitable for high pulse current operation •Angle of half intensity ϕ = ± 17° •Peak wavelength λp = 870 nm •Longterm reliability•Matched with PIN Photodiode TEMD1000 •Versatile terminal configurationsApplicationsIrDA compatible data transmission Miniature light barrierFor control and drive circuits Photointerrupters Incremental sensorsAbsolute Maximum RatingsT amb = 25°C, unless otherwise specifiedBasic CharacteristicsT amb = 25°C, unless otherwise specified T amb = 25°C, unless otherwise specifiedParameterTest conditionSymbol Value Unit Reverse Voltage V R 5V Forward Current I F 100mA Peak Forward Current t p /T = 0.5, t p = 100 µs I FM 200mA Surge Forward Current t p = 100 µsI FSM 0.8A Power Dissipation P V 190mW Junction T emperature T j 100°C Operating T emperature Range T amb - 40 to + 85°C Storage T emperature Range T stg - 40 to + 100°C Soldering Temperaturet ≤ 5secT sd <260°C Thermal Resistance Junction/AmbientR thJA400K/WParameterTest conditionSymbol MinTyp.Max Unit Forward Voltage I F = 20 mAV F 1.3 1.5V I F = 1 A, t p = 100 µs V F 2.4V Temp. Coefficient of V F I F = 1.0mA TK VF - 1.7mV/K Reverse Current V R = 5 VI R 10µA Junction CapacitanceV R = 0 V , f = 1 MHz, E = 0C j160pFPackage Dimensions in mmTSMF1000TSMF1020 Document Number 81061Package Dimensions in mmTSMF1030TSMF1040Document Number Reel Dimensions Document Number 81061Taping TSMF1000Document Number Taping TSMF1030Ozone Depleting Substances Policy StatementIt is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution andoperatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendmentsrespectively2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the EnvironmentalProtection Agency (EPA) in the USA3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical designand may do so without further notice.Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyTelephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423Document Number 。
TSMC参与2010中国国际汽车半导体产业峰会
尼黑所举 行的 Ｐ ＲＯＤ ｕＣＴ ＮＩ Ａ展 会 上 ， ＩＬ Ｒ０ Ｃ Ｓ Ｐ ＡＣＥＳ Ｘ
新 受 到 了 由 市 场 专 家 组 成 的 独 立 评 委 团 的 青 睐 ，并 荣 获
种类 ，能够使客户从功率产 品封装的标准化 中获益 ，还能够
以相 较 上 一 代产 品更 小 的 占位 面 积 ， 来 提 升 效能 水 平 的 解 带 决 方 案 。 ” （ 本刊 通讯 员）
了众所期 待的 Ｓ ｈｎ 远 见奖 （ Ｓ ＯＮ Ａｗａｄ ）以 ＭＴ Ｃ ｉａ ＶＩ Ｉ ｒ ｓ
半导体和英飞凌实现 了引脚输 出的标准化 ， 并在性能水平方
面 相辅 相 成 ，为 客 户提 供 两 个供 货 来 源 以满 足 计 算 、电信 和
服务 器市场 对 高效率 设计 的需 求 。这些 协议 （ ａ ｋ ｇ Ｐｃａｅ ａｉ ｍｅｔ ｌｎ ｎ）的 目的是通过多个来源和行业标准封装，为客户 ｇ
Ｔ ＭＣ参 与 ２ Ｓ ０ １ ０中国国际汽 车
半 导 体 产 业 峰 会
Ｔ ＭＣ４月２ Ｓ ２日应邀参与 由工业和信息化部 指导 及中
国汽 车 工程 学 会 于北 京 举 办 的 ２ １ 中 国 国际 汽 车 半 导 体 产 ００ 业 峰 会 ，会 中针 对 近 几年 来 Ｔ ＭＣ在 汽 车 电子 之 品 质及 可 Ｓ 靠 度 方 面 的进 展 发表 演说 。 此 次 盛 会有 来 自数 百 位 全 球 主 要 的汽 车 电子 厂 商 ，半 导 体 业 者 ，知 名 研 究 机 构 及 学 术 机 构 的 代表 参 与 。 目前 中 国车 用 电 子 的 成 长 力 道 强 劲 ， 对 中 国半 导 体
2022考研英语阅读TSMC台积电
2022考研英语阅读TSMC台积电TSMC台积电A fab success一家晶圆厂的胜利之道The smartphone boom has been a boon for apioneer in semiconductors智能手机的大爆发让这个半导体行业的先锋获益不少WHEN he founded Taiwan SemiconductorManufacturing Company in 1987, Morris Changrecalls,张忠谋回忆起1987年创立台积电之初时说道：Nobody thought we were going anywhere.没人会料想到台积电会无处不在。
Back then the rule was that semiconductor companies both designed and made chips.当时半导体公司的业务都涉及了芯片的设计以及制造领域。
TSMC was the first pure foundry, making chips for designers with no factories, or fabs, oftheir own.台积电是第一家纯代工厂商为没有属于自己晶圆工厂的芯片设计公司代工生产芯片。
The doubts of others suited TSMC nicely.所以它们的产业模式也遭受过质疑。
Mr Chang, at 82 still chairman and in his second stint as chief executive, says that meant itsuffered no competition in its first eight years.年届82的张忠谋目前照旧是台积电的总裁，这也是他其次次担当台积电的首席执行官一职，他说正是由于这些质疑使得台积电在创立的头八年里所向披靡。
These days the idea is more popular.现如今这种产业模式已经越来越受到欢迎。
嵌入式系统
Window CE
– Windows 作業系統對於嵌入式系統來說太過於 肥大的產物，微軟推出精簡版的 Windows CE 作為進攻嵌入式系統的主力。目前主要應用於 PDA 上頭 – Windows CE也承襲了Windows 系統原有的缺 點：耗系統資源、不穩定、效率不佳..等毛病， 後來將整個架構重新改寫後推出 Windows CE 3.0 版，或稱為 Pocket PC – Windows CE 可應用於 PDA 、WebPAD、Thin Client等等。下圖 是採用 Windows CE 為作業 系統的 SIMPad
藍色家電
以傳統家電為基礎，融合電腦技術的新型家用電 器，性能更為強大的新一代電器。 藍色家電以家電廠商的角度更細分出許多不同的 領域，可分為四大類:
– – – –
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資訊藍色家電。 娛樂藍色家電。 通訊藍色家電。 家庭自動化產品。
一是以網路爲功能核心。 二是以嵌入式系統爲技術核心。
什麼是嵌入系統
嵌入式系統由僅限於工業用電腦普及到家電的領 域。這類系統的特性是沒有外接的零配件、具有 特定的功能、容積小、穩定性強的特點。系統軟 體的設計與規劃須兼顧上述的特性而研發。 嵌入式系統的另外一種延伸應用是PDA ，嚴格講 應該是多工的嵌入式系統，因為 PDA 上還有複雜 的 GUI 系統，有些系統是與 GUI 系統一起整合在 一起，有些則是分開的狀態。 另外還有上網機 ( Set Top Box )、WebPDA、手 機也都算是嵌入式系統的應用之一
什麼是嵌入系統
常見嵌入作業系統
DOS
– 微軟一開始選用了派特森的Q-DOS " QUICK AND DISK OPERATING SYSTEM " 為基礎然後 再擴充功能而成 MS-DOS , 主要是採用由IBM 提供的使用8088 微處理器的電腦作開發平臺, 它是以16 位元組單人單工作業系統。 – 由於系統陽春所以特別適合一些功能簡單裝置 使用，例如：LED 看版
物联网-曾岐峰
Proposal of the concept
• first put forward :
1999 USA
• formally proposed:
2005 Tunis(突尼斯) WSIS （信息社会世界峰
会） ITU（国际电信联盟） “ITU Internet Report 2005: Internet of things”, 《ITU互联网报告2005：物联网》 -----It is the second computer, the Internet and mobile communication network（移 动通信网） again after the wave of the information industry.
Application
Power grids电网, railways 铁路, bridges 桥梁, tunnels 隧道, roads 公路, buildings 建筑, dams 大坝, water supply systems 供水系统, oil and gas pipelines 油气管道
Study in
Beijing University of Posts and Telecommunications 北京邮电大学 Nanjing University of Posts and Telecommunications 南京邮电大学
Apply to
Shanghai Pudong International Airport 上海浦东国际机场 Shanghai World Expo 上海世博会
• Name：曾岐峰 • Class：政治0904班
Basic concepts
Proposal of the concept Application Study in China
DesignandVerificationofUSB3.0LinkLayer（LTSSM）
Design and Verification of USB 3.0 Link Layer(LTSSM)Rohit Kumar School of information Sciences Manipal UniversityManipal, IndiaHardik TrivediSchool of information SciencesManipal UniversityManipal, IndiaNitish AlokSchool of information SciencesManipal UniversityManipal, IndiaAbstract-In this proposed design it mainly includes USB 3.0, LTSSM. The Link Training and Status State Machine (LTSSM) have downstream and upstream ports. Transitions of all 12 link states and their subs -states of both downstream and upstream have been designed. The proposed model is implemented using Verilog HDL. Proposed model in this paper has been verified using SystemVerilog.1.INTRODUCTIONUSB is an industry standard developed in the mid-1990s, it defines the cables, connectors and protocols used in a bus for connection and communication between computers and electronic devices. The first USB technology began development in 1994, co-invented by Ajay Bhatt of Intel and the USB-IF (USB Implementers Forum, Inc).Before USB came into existence, computers used serial and parallel ports to plug devices into computers and transfer data. Expansion cards and custom drivers were often required to connect the devices. Parallel ports transferred data at approximately 100 kilobytes per second, where as serial ports ranged from 115 to more than 450 kilobits per second. The high extent of incompatibilities and the attempt to use multiple interfaces helped in the growth for a technology like USB. Immediate interaction between devices and a host computer without the need to disconnect or restart the computer also enables USB technology to furnish more efficient operation. Consequently, a single USB port can handle up to 127 devices while offering a collective compatibility.Versions of USB specification:∙Revision 1.0 released on January 15, 1996, introduced a low-speed transfer rate of 1.5 Mbit/sand a full-speed transfer rate of 12 Mbit/s.∙Revision 1.1 released on September 23, 1998, introduced the improved specification and was thefirst widely used version of USB.∙Revision 2.0 released on April 27, 2000. The major feature of revision 2.0 was the addition of ahigh-speed transfer rate of 480 Mbit/s.∙Revision 3.0 released on November 17, 2008, brings significant performance enhancements tothe USB standard while offering backwardcompatibility with the peripheral devices currentlyin use. Delivering data transfer rates up to tentimes faster (the raw throughput is up to 5.0Gbit/s) than Hi-Speed USB (USB 2.0).B3.0 LINK LAYERLink Layer helps in traffic management between the two links connected to each other. It manages the port to port flow of data between the host and the device.Fig 1: USB Layout Diagram [1]The Link Layer functions consist of:∙Effective power management for 4 link powerstate (U0, U1, U2, and U3).∙Packet and link command formation.∙Link training symbol lock and Rx-equalization.∙Packet header formation.∙Different types of error handling.B 3.0 LTSSMLTSSM (Link Training and Status State Machine) is the state machine used for link connectivity and link power management. LTSSM consist of 12 main link states and their sub-states. These states and sub-states are responsible for link training, power management and error testing.Fig 2: State diagram of LTSSM [1]B 3.0 LTSSM STATE DESIGNThe proposed USB3.0 LTSSM architecture is consisting of following states and their sub-states:4.1SS.DisabledIt is a state where a port’s SuperSpeed connectivity is disabled. It does not contain any sub-states in case of downstream port and hub upstream port but contain two sub-states for peripheral upstream port.∙SS.Disable.Default∙SS.Disable.ErrorFig 3: SS.Disabled Sub-state Machine [1]4.2SS.InactiveIt is a state where a link has failed SuperSpeed operation and USB is non-operable. It contains two sub-states: ∙SS.Inactive.Disconnect.Detect∙SS.Inactive.QuietFig 4: SS.Inactive Sub-state Machine [1]4.3Rx.DetectIt is the initial state after reset, called as power on state of LTSSM for both downstream port and upstream port. It detects the presence or absence of a device connected at far end of the link. It contains three sub-states:∙Rx.Detect.Reset∙Rx.Detect.Active∙Rx.Detect.QuietFig 5: Rx.Detect Sub-state Machine [1]4.4PollingIt is a state where link training starts. It contains five sub-states:∙Polling.LFPS∙Polling.RxEQ∙Polling.Active∙Polling.Configuration∙Polling.IdleFig 6: Polling Sub-state Machine [1]4.5Compliance ModeIt is used to test the transmitter as per given voltage and timing specification. It does not contain any sub-state.4.6U0It is normal power state and does not conation any sub-state.4.7U1It is low power state where no transmission of packets is done.Fig 7: Transition to other state from U1 [1]4.8U2It is even low power state than U1 but exit latency increased in this state.Fig 8: Transition to other state from U2 [1]4.9U3It is lowest power state, where device is put into a suspend state.Fig 9: Transition to other state from U3 [1]4.10RecoveryRetraining of the link is done in this state. It contains three sub-states:∙Recovery.Active∙Recovery.Configuration∙Recovery.IdleFig 10: Recovery Sub-state machine [1]4.11LoopbackIt is used as test and fault isolation state. It contains two sub-states:∙Loopback.Active∙Loopback.ExitFig 11: Loopback Sub-state machine [1]4.12Hot ResetThis state is entered when it is directed to do so by a device’s higher layer. It contains two sub-states:∙Hot Reset.Active∙Hot Reset.ExitFig 12: Hot Reset Sub-state machine [1]5.VERIFICATIONThe verification of above LTSSM design for Upstream port is carried out to check that if all the states and sub-states are covered or not. There are 18 different signal which drives LTSSM. All 18 different signals have been given as input to design and respected state has been monitored. These states have been assigned asoutput. Verification is done using SystemVerilog.Fig 13: Test Bench Architecture5.1 InterfaceIt consists of bundle of signals which can be referenced throughout a design to simplify hierarchical connections and module instantiation i.e. used to connect the testbench to the DUT.5.2 StimulusUsing SystemVerilog randomization, stimulus is generated automatically. SystemVerilog high-level data structures helps in storing and processing of stimulus in an efficient way.5.3 Stimulus GeneratorIt generates stimulus which are sent to DUT by driver.Randomization of stimulus has been done in this block. Automaticrandomization didn’t cover all the states of LTSSM, so somedirected random testcases is written here. Mailbox sg2dr is createdto send the generated stimulus to the driver block.5.4 DriverIt repeatedly receives a data items from mailbox sg2dr and drives it to DUT by sampling and driving the DUT signals. The driver also sends the stimulus to scoreboard using drv2sb mailbox.5.5 MonitorThis block receives the output of the DUT i.e. output of LTSSM design. The output is sent to the scoreboard using mailbox rcv2sb.5.6 ScoreboardThis block receives the stimulus from the driver through the mailbox drv2sb and also receives the DUT output from monitor through the mailbox rcv2sb. In LTSSM design, for different stimulus there will be different states, so in scoreboard expected state for all the combination of stimulus has been written and compared with DUT output receives from mailbox rcv2sb. If it matches then LTSSM design is working correctly.5.7 EnvironmentIt contains the instances of the entire verification componentMethods defined in Environment class:-build(): all the objects like driver, monitor etc areconstructed.reset(): reset the DUT.start(): To call the methods which are declared in theother components like driver and monitor.run(): This method calls all the above declared methodsin a sequence order.Report(): Its main function is to detect the errors in thedesign and report the errors. .6.SIMULATION RESULTThe output Link_state changes with change in the input signal.LTSSM design for Downstream portFig 14: Downstream port simulation LTSSM design for Upstream port LTSSM design for upstream port consists of SS.Disabled sub-states.Fig 15: Upstream port simulation7.VERIFICATION RESULT7.1 ScoreboardFig 16: Scoreboard7.2Coverage ReportFig 17: Coverage resultFig 18: Full FSM coverage report8.CONCLUSIONThis design explains the concept of USB 3.0 LTSSM and their different states and sub-states. Since the data received by scoreboard same as the expected state of the design, therefore proposed design of LTSSM is functionally correct. As shown in figure 16 states are correctly matched. Figure 17 shows the different types of coverage report of the design i.e. toggle coverage, expression coverage, and functional coverage and toggle coverage. Figure 18 shows that all the states of proposed design is successfully covered.9.ACKNOWLEDGMENTSWe would like to thank our professors Mr. Sunderasan C. and Asst. Prof Samarendranath Bhattacharya for being our advisor and guide. We are grateful to them for their continuous support and help throughout the development of the project. We would also like to thank our friends Ashwin K Rao and Ronak Tank who helped us during this project. Besides, we would like to thank our department School Of Information Science for providing us with a good environment and facilities to complete this project. At last but not least gratitude goes to all of my friends who directly or indirectly helped me to complete this project.REFERENCES[1]“Universal Serial Bus 3.0 Specification”, Revision 1.0,November 12, 2008.[2]“Universal Serial Bus 2.0 Specification”, Revision 1.0,March 13, 2006.[3]PCI Express Base Specification, Revision 2.0, December2006[4]M. Aguilar, A. Veloz and M. Guzman, "Proposal ofimplementation of the" data link layer" of PCI-express", Proceedings of 1st International Conference on Electrical and Electronics Engineering, pp. 64, June 2004.[5]Ravi Budruk, Don Anderson & Tom Sanely, 2004. “ PCIExpress System Architecture” , Mindshare Inc., pp 419-434.[6]Chris Spears, “System Verilog for Design, “A Guide toUsing System Verilog for Hardware Design and Modeling,”Springer Second edition.[7]/files/resources/MindShare_Intro_to_USB_3.0.pdf.[8]Verilog HDL by Sameer Palnitkar.。
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Collaborated Transaction
CASD Marketing, R&D Demand Planning
PAR
Credit Order/Lot
Invoice
CCDR
SDCR
Feedback Customer Service
Head Quarter
Corp. Finance Production Accou Quality Accou Pricing Planning nting nting
Supplier
Enterprise Planning Workforce Management & Control
© 2007 TSMC, Ltd Mar. 2007 P. 13
Sales
Planning FIN
Audit HR
Logistics
Customer
Supplier
完整的銷售服務系統支援全球性業務
System
Supply Chain Management
Capability
Demand Planning Allocation Planning Capacity Modeling ATP, MPS Price Guide, Price Adjustment Quotation ASP Forecast Order Entry / Fulfillment Credit Management Order Release Customer Claim/Issues/Feedback SDCR, RMA Customer Data Management
© 2007 TSMC, Ltd Mar. 2007 P. 3
主要資料來源: 主要資料來源 IC Insights
晶圓製造服務成長預測
晶圓製造服務之年成長率高於半導體業平均成長值 台積電市佔率佔全球晶圓製造服務 50%
‘06 Source: IC insights, WSTS, TSMC
© 2007 TSMC, Ltd Mar. 2007 P. 4
最頂尖的企業資訊系統，以滿足企業快速成長的需求，並降低成本。 最頂尖的企業資訊系統，以滿足企業快速成長的需求，並降低成本。
© 2007 TSMC, Ltd Mar. 2007 P. 11
台積電電子商務系統
© 2007 TSMC, Ltd Mar. 2007 P. 12
End-to-End商務系統趨勢與應用
© 2007 TSMC, Ltd Mar. 2007 P. 8
內容大綱
台積電與半導體產業分工的演進 資訊技術在台積電的應用 資訊技術人才在台積電
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台積電資訊技術團隊與多元的應用領域
陣容堅強的資訊技術團隊
由海內外各類資訊技術精英及專才所組成 正職員工 500 名, 外包人員 370 名
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運用資訊技術強化公司經營績效
藉由自動化提高生產力
透過高度的數位化工作環境以大幅提昇員工的生產力、降低人力運作成本， 透過高度的數位化工作環境以大幅提昇員工的生產力、降低人力運作成本，並 藉由不斷的改善督促企業成長並創造價值。 藉由不斷的改善督促企業成長並創造價值。
ATP - Available To Promise
Customer Relationship Management
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MPS - Master Production Schedule RMA - Return Material Authorization
Sales Offices
Account Manager
Customer Engageme nt Supply Chain Planning
Sales Design, Logistics & Services R&D, & Finance Manufacturing
Enterprise Workforce Planning Management & Control
半導體產業水平分工將繼續進行，但虛擬垂直整合的必要性也愈來愈高。 半導體產業水平分工將繼續進行，但虛擬垂直整合的必要性也愈來愈高。台積電 使用大量資訊技術以eFoundrySM創造新的商業模式“Virtual Fab” 。 創造新的商業模式“ 使用大量資訊技術以 物流
E2E商務系統平台支援全公司四大領域商務運作。 商務系統平台支援全公司四大領域商務運作。 商務系統平台支援全公司四大領域商務運作 提供電子商務服務平台，與廠商及客戶上下游結合成IC產業完整的價值鏈 產業完整的價值鏈。 提供電子商務服務平台，與廠商及客戶上下游結合成 產業完整的價值鏈。
採用全世界最具領導地位的ERP套裝軟體 套裝軟體SAP，以整合企業內部財務會計及後勤支援 採用全世界最具領導地位的 套裝軟體 ， 作業，透過物流與金流緊密整合來支援銷售與製造另外二大主要領域商務作業。 作業，透過物流與金流緊密整合來支援銷售與製造另外二大主要領域商務作業。
並提供企業複雜的商業模式，包括：跨國企業內部運作 並提供企業複雜的商業模式，包括：跨國企業內部運作(Cross-country,inter-company)、 、 全球接單、集中議價、集中產能規畫、跨國生產、外包管理、企業併購等服務。 全球接單、集中議價、集中產能規畫、跨國生產、外包管理、企業併購等服務。 因應公司高度成長除了頻繁商業模式改變外也必須迅速反應公司經營的切割與合併(Split & 因應公司高度成長除了頻繁商業模式改變外也必須迅速反應公司經營的切割與合併 Merge)，目前旗下己有 家子公司。 家子公司。 ，目前旗下己有15家子公司
Customer Support
Pricing & Quotation Order Taking & Fulfillment
Field Tech Support
Shipping & Billing
Customer Complaint & Sales Return
Customer Satisfactio n Manageme nt
IT Technology
i2/Java/VB
Price and Quotation
CASD - Capacity Allocation Supported Demand
Order Management
PAR - Price Adjustment Request CCDR - Customer Claim Description Report SDCR - Sales Debit/Credite Requisition
SSMC (新加坡 新加坡) 新加坡
台積電願景
成為全球最先進及最大的專業積體電路技術及製造服務 業者， 業者，並且與我們無晶圓廠設計公司及整合元件製造商 的客戶群共同組成半導體產業中堅強的競爭團隊。 的客戶群共同組成半導體產業中堅強的競爭團隊。
為了實現此一願景，我們必須擁有三位一體的能力 為了實現此一願景， (1)是技術領導者，能與整合原件製造商中的佼佼者匹敵； (1)是技術領導者，能與整合原件製造商中的佼佼者匹敵； (2)是最具成本優勢的製造者 的製造者； (2)是最具成本優勢的製造者； (3)是最具聲譽、 服務為導向，以及客戶最大整體利益的提供者。 客戶最大整體利益的提供者 (3)是最具聲譽、以服務為導向，以及客戶最大整體利益的提供者。
2006 世界十五大半導體公司
(依 2006 營收排行 ) 依
台積電 主要資料來源: 主要資料來源 IC Insights & 電子時報 (1997年 第一家掛牌紐約證交所之台灣公司 (1997年) 第一家在美國設廠並轉移半導體製程技術至美國之台灣公司 © 2007 TSMC, Ltd 億台幣。 2006 年營收約達 3,174 億台幣。稅後盈餘約 1,270 億台幣 Mar. 2007 P. 5
金流
建構在整合的物流之上，才能快速反應全球營運與企業績效， 建構在整合的物流之上，才能快速反應全球營運與企業績效，並且及時作出財務預測 提供經營決策的資訊。 提供經營決策的資訊。
Customer
Sales & Services
Design, R&; Finance
台積電改變世界半導體業遊戲規則
減少自有晶圓廠的投資, 傳統的整合晶圓製造公司 (IDM)減少自有晶圓廠的投資 減少自有晶圓廠的投資 並提昇委外製造服務的比重已越來越高。 並提昇委外製造服務的比重已越來越高。
TI, Intel TI, Intel 矽統
創意、智原 創意、 nVidia 聯發科, 聯發科, 威盛
藉由流程整合改善經營績效與公司治理
透過知識管理平台整合綿密及精確的工作流程與寶貴的企業知識， 透過知識管理平台整合綿密及精確的工作流程與寶貴的企業知識， 全面性提昇公司營運績效及核心競爭力。 全面性提昇公司營運績效及核心競爭力。
藉由標準化因應企業的快速成長並降低成本
運用最佳化方法(BKM, Best Known Method)及標準化過程將企業流程建置成 運用最佳化方法 及標準化過程將企業流程
年的73 73億美金成長至 無晶圓廠半導體公司的產值由 1998 年的73億美金成長至 2006 年 的 423 億美金 (成長 6 倍) 同時期自有晶圓廠半導體公司的產值僅由 1,091 億美金成長至 2,110 億美金 (僅成長 93% )
2007 主要半導體終端產品
無線網路 (含藍芽與 Wi-Fi) Wi手機 (含智慧型手機和 PDA) 數位相機與多媒體播放器 (如 iPod) 車用電子 X電腦遊戲機 (PS3, X-BOX, Wii..) 數位電視與機上盒 DVD 播放器與錄影機 個人電腦與相關資訊產品 RFID, 智慧型晶片卡