45nm工艺库的版图规则

35
50
PS=PD =105n×2+W AS=AD =105n×W
55
重要
单位：nm
90 3 50
50 50
W L Poly伸出有源区 扩散层伸出poly
最小尺寸 90 50 50 105 50
Poly与有源区间距
扩散层与阱边缘间距
55
50
55
Contact hole and Via hole (接触孔和通孔)
Rule ACTIVE.1 ACTIVE.2 ACTIVE.3 ACTIVE.4
Value 90 nm 80 nm 55 nm none
Description Minimum width of active Minimum spacing of active Minimum enclosure/spacing of nwell/pwell to active saveDerived: active must be inside nwell or pwell
Rule VIA1.1 VIA1.2 VIA1.3 VIA1.4
Value 65 nm 75 nm none none
Description Minimum width of via1 Minimum spacing of via1 saveDerived: via1 must be inside metal1 saveDerived: via1 must be inside metal2
Rule METALINT.1
Value 70 nm
Description Minimum width of intermediat e metal Minimum spacing of intermedi ate metal Minimum enclosure around via 1 on two opposite sides Minimum enclosure around via [2-3] on two opposite sides Minimum spacing of metal wider than 90 nm and longer than 900 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um Minimum spacing of metal wider than 900 nm and longer than 2.7 um
um 0.070 0.070 0.035/0
Rule IMPLANT.1 IMPLANT.2 IMPLANT.3/4 IMPLANT.5
Value 70 nm 25 nm 45 nm none
Description Minimum spacing of nimplant/ pimplant to channel Minimum spacing of nimplant/ pimplant to contact Minimum width/ spacing of nimplant/ pimplant Nimplant and pimplant must not overlap
Contact to Poly
Rule 5.1 5.2 5.3 Description Exact contact size Minimum poly overlap Minimum contact spacing um 0.065x0.065 0.005 0.075
5.4
Minimum spacing to gate of transistor
METAL1.6
METAL1.7 METAL1.8 METAL1.9
270 nm
500 nm 900 nm 1500 nm
Minimum spacing of metal wider than 270 nm and longer than 300 nm
Minimum spacing of metal wider than 500 nm and longer than 1.8um Minimum spacing of metal wider than 900 nm and longer than 2.7 um Minimum spacing of metal wider than 1500 nm and longer than 4.0 um
相同阱
0 or 135
不同阱
0 or 225
gatepolys fieldpolys 140
Poly
50
Well 200
75
80
Active N+，P+ 90
75
Metal1
Poly 35 Metal2 65 M1 or M2 35 35 65
65
con/via1
70
Implant可与well同样大小
Select
Rule
4.1 4.2 4.3 4.4
Description
Minimum select spacing to channel of transistor to ensure adequate source/drain width Minimum select overlap of active Minimum select overlap of contact Minimum select width and spacing (Note: P-select and N-select may be coincident, but must not overlap) (not illustrated)
NCSU PDK45nm 版图规则
工艺流程
• 与版图的对应关系 • 了解一定的工艺流程背景知识有助于画好 版图
gate-oxide TiSi2 AlCu SiO2 Tungsten
poly
p-well n-well
SiO2 p+
n+
p-epi p+
VDD M2Leabharlann Baidu
VDD
M4 Vin Vout Vout2
0.035
Contact to Active
Rul e 6.1 6.2 6.3 6.4 Description Exact contact size Minimum active overlap Minimum contact spacing Minimum spacing to gate of transistor um 0.065x0.065 0.005 0.075 0.035
POLY.6
75 nm
Minimum Minimum spacing of field poly
50 50
140
70
50
75
Rule WEL L.1 WEL L.2 WEL L.3 WEL L.4
Valu e none 225 nm 135 nm 200 nm
Description saveDerived: nwell/pwell must not overlap Minimum spacing of nwell/pwell at different potential Minimum spacing of nwell/pwell at the same potential Minimum width of nwell/pwell
Lambda
3 2 1.5 4
Metal2
Rule 9.1 9.2 9.3 9.4
Description Minimum width Minimum spacing Minimum overlap of via1 Minimum spacing when either metal line is wider than 10 lambda
Metal1
Rule 7.1 7.2 7.3 7.4 Description Minimum width Minimum spacing Minimum overlap of any contact Minimum spacing when either metal line is wider than 10 lambda um 0.065 0.065 0.035/0
M1
M3
设计规则
• lamda规则
– 最小尺寸以lamda的倍数来规定
• 微米规则
– 直接用具体的微米、纳米等单位来规定
• Grid
– 由具体工艺规定 – 分辨率 – 0.18mm工艺为45nm，45nm工艺为2.5nm – 版图中所绘制的矩形、互连线等尺寸必须是它 的倍数
1）Intra-Layer Design Rules 层内设计规则 单位：nm
可获得的Contact hole and Via hole metal1/diff 接触孔 metal1/poly 接触孔 metal1/metal2 通孔 metal2/metal3 通孔
通孔尺寸 Cut(通孔): overlap (复盖) : 65 x 65 5 65 35/90
minimum spacing(间距): diff接触孔与poly间距：
METALINT.2
70 nm
METALINT.3
35 nm
METALINT.4
35 nm
METALINT.5
90 nm
METALINT.6
270 nm
METALINT.7
500 nm
METALINT.8
900 nm
METALINT.9
1500 nm
Minimum spacing of metal wider than 1500 nm and longer than 4.0 um
Description Minimum width of metal1 Minimum spacing of metal1 Minimum enclosure around contact on two opposite sides Minimum enclosure around via1 on two opposite sides Minimum spacing of metal wider than 90 nm and longer than 900 nm
Rule POLY.1 POLY.2 POLY.3 POLY.4 POLY.5
Value 50 nm 140 nm 50nm 70 nm 50 nm
Description Minimum width of poly Minimum spacing of poly AND active Minimum poly extension beyond active Minimum enclosure of active around gate Minimum spacing of field poly to active
CONTACT.6
CONTACT.7
35 nm
90 nm
Minimum spacing of contact and gate
Minimum spacing of contact and poly
Rule METAL1.1 METAL1.2 METAL1.3 METAL1.4 METAL1.5
Value 65 nm 65 nm 35 nm 35 nm 90 nm
70
重要
最小宽度 Poly 50 metal1 65 有源区（扩散区，N+，P+） 90 Contact or Via Hole 65
最小间距 75/140 65 80 65
2）Inter-Layer Design Rules 层间设计规则
Transistors
单位： nm
50 70 50 65 90 5
Rule CONTACT.1 CONTACT.2 CONTACT.3 CONTACT.4 CONTACT.5
Value 65 nm 75 nm none 5 nm 5 nm
Description Minimum width of contact Minimum spacing of contact saveDerived: contact must be inside active or poly or metal1 Minimum enclosure of active around contact Minimum enclosure of poly around contact