02-Transistors and Layout

11
Transistor structure

N-type transistor:
12
Simple Cross Section
SiO2
metal3
metal2
transistor poly n+ p+
metal1
via
n+ substrate substrate
13
Photolithography

28
Metal Migration
Current-carrying capacity of metal wire depends on cross-section Height is fixed, so width determines current limit Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire
gate oxide
silicide
source/ drain
poly
19
Fabrication Services

Educational services:

MOSIS (US):

/

EuroPractice (Europe):

Vgs = 2V:
Id
= 0.5k’(W/L)(Vgs-Vt)2= 93 A

Vgs = 5V:
Id
= 1 mA
5
NMOS

When VGS (VIN) is 0, ID= 0 and VOUT = VDD When VGS (VIN) increases, ID increases linearly and VOUT = VDD-ID*R When VGS (VIN) is very large (cutoff), ID=VDD/R (ID=IR) and VOUT close to 0

UMC (United Microelectronics Corp.)


Taiwan, Market Cap.: 12.38B, P/E: 12.89
China, Market Cap.: 2.6B, P/E: NA Singapore, Market Cap.: 2.15B, P/E: 52.88
8
CMOS
9
CMOS

Transfer function:
10
Fabrication Processes

IC built on silicon substrate:
Some structures diffused into substrate Other structures built on top of substrate

29
Metal Migration Problems and Solutions Marginal wires will fail after a small operating period—infant mortality Normal wires must be sized to accommodate maximum current flow:
EIE511 VLSI System Design Lecture 2
Transistors and Layout
1
Introduction
Transistor structures and fabrication Characteristics of transistors and wires Design rules Layout design

Mask patterns are put on wafer using photo-sensitive material:
14
Process Steps

First place tubs to provide properlydoped substrate for n-type, p-type transistors:

27
Circuit Simulation
Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior Numerical solution allows more sophisticated models, non-functional (table-driven) models, etc

Imax
= 1.5 mA/m of metal width

Mainly applies to VDD/VSS lines
30
Diffusion Wire Capacitance

Capacitances formed by p-n junctions:
sidewall capacitances n+ (ND) depletion region

Substrate regions are doped with n-type and p-type impurities (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal) Silicon dioxide (SiO2) is insulator

What are the ICs produced from those companies?

Which companies are their equipment providers?

What are the equipments provided from those companies?
2NMOS Linear region (Vds < Vgs - Vt):
Id
= k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2) = 0.5k’ (W/L)(Vgs - Vt) 2
D
Saturation region (Vds >= Vgs - Vt):
Id
G
S
22
Class Discussions 2.1

Customers

Equipment providers
23
Channel Length Modulation Length Parameter
describes small dependence of drain corrent on Vds in saturation Factor is measured empirically New drain current equation:

26
The Modern MOSFET

Features of deep submicron MOSFETs:
Epitaxial layer (a crystalline layer grown on top of the wafer during process) for heavilydoped channel Reduced area source/drain contacts for lower capacitance Lightly-doped drains to reduce hot electron effects Silicided poly, diffusion to reduce resistance

SMI (Semiconductor Manufacturing International Corp.)


CHRT (Chartered Semiconductor Manufacturing Ltd.)

21
Class Discussions 2.1

Which companies are their customers?
A variety of leakage currents draw current away from the main logic path The sub-threshold current (weak inversion current) is one particularly important type of leakage current
poly n+ p-tub n+ p+
poly n-tub p+
17
Process Steps

Start adding metal layers:
metal 1 poly n+ p-tub n+ vias p+
metal 1 poly n-tub p+
18
0.25 micron transistor (Bell Labs)

Id
= 0.5k’ (W/L)(Vgs - Vt) 2(l - Vds)

Equation has a discontinuity between linear and saturation regions---small enough to be ignored
24
Gate Voltage and The Channel