AD9959数据手册部分内容中文翻译

AD9959数据手册（部分）

GENERAL DESCRIPTION概述

The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

AD9959含有四个直接数字频率合成器（DDS），提供各通道独立的频率、相位和振幅控制。这种灵活性可以用来纠正信号之间的不平衡，这种不平衡是由于模拟处理，如滤波，放大，或PCB布局相关的不匹配导致。因为所有通道共用一个系统时钟，因此固有的同步。也支持多个设备的同步。AD9959可以执行16级频率、相位、振幅（FSK，PSK，ASK）调制，通过将数据传到配置引脚执行。此外，AD9959还支持频率、线性扫频、相位或振幅的应用，如雷达和仪表。

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation.

AD9959的串行I/O端口提供了多种配置，提供显著的灵活性。串行I / O端口提供了一个SPI兼容的操作模式，SPI操作与较早的模拟设备公司DDS产品几乎相同。灵活性是通过四个数据引脚（sdio_0 / sdio_1 /sdio_2 / sdio_3）允许四可编程串行I/O操作模式来实现的。

The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.

AD9959采用先进的DDS技术，提供低高性能低功耗。该器件集成了四个高速10位DAC 具有优良的宽带和窄带SFDR。每个通道有一个专门的32位频率调谐字，14位相位偏移，和一个10位幅度调节输出。

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to all channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier.