EDA8位二进制并行加法器

实验二：8位加法器的设计1．实验目的（1）学习Quartus Ⅱ/ISE Suite/ispLEVER软件的基本使用方法。

（2）学习GW48-CK或其他EDA实验开发系统的基本使用方法。

（3）了解VHDL程序的基本结构。

2.实验内容设计并调试好一个由两个4位二进制加法器级联而成的8位二进制并行加法器，并用GW48-CK或其他EDA实验开发系统（事先应选定拟采用的实验芯片的型号）进行硬件验证。

3．实验要求（1）画出系统的原理图，说明系统中各主要组成部分的功能。

（2）编写各个VHDL源程序。

（3）根据系统的功能，选好测试用例，画出测试输入信号波形或编号测试程序。

（4）根据选用的EDA实验开发装置编好用于硬件验证的管脚锁定表格或文件。

（5）记录系统仿真、逻辑综合及硬件验证结果。

（6）记录实验过程中出现的问题及解决办法。

4.实验条件（1）开发条件：Quartus Ⅱ 8.0。

（2）实验设备：GW48-CK实验开发系统。

（3）拟用芯片：EPM7128S-PL84。

5.实验设计1）系统原理图为了简化设计并便于显示，本加法器电路ADDER8B的设计分为两个层次，其中底层电路包括两个二进制加法器模块ADDER4B，再由这两个模块按照图2.1所示的原理图构成顶层电路ADDER8B。

ADDER4B图2.1 ADDER4B电路原理图A8[7..0]图 2.1 ADDER8B电路原理图2）VHDL程序加法器ADDER8B的底层和顶层电路均采用VHDL文本输入，有关VHDL程序如下。

ADDER4B的VHDL源程序：--ADDER4B.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER4B ISPORT(C4:IN STD_LOGIC;A4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);B4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CO4: OUT STD_LOGIC);END ENTITY ADDER4B;ARCHITECTURE ART OF ADDER4B ISSIGNAL S5:STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL A5,B5:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINA5<='0'&A4;B5<='0'&B4;S5<=A5+B5+C4;S4<=S5(3 DOWNTO 0);CO4<=S5(4);END ARCHITECTURE ART;ADDER8B的VHDL源程序：--ADDER8B.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER8B ISPORT(C8: IN STD_LOGIC;A8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);B8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);S8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);CO8: OUT STD_LOGIC );END ENTITY ADDER8B;ARCHITECTURE ART OF ADDER8B ISCOMPONENT ADDER4B ISPORT(C4: IN STD_LOGIC;A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CO4: OUT STD_LOGIC );END COMPONENT ADDER4B;SIGNAL SC: STD_LOGIC;BEGINU1:ADDER4B PORT MAP(C4=>C8,A4=>A8(3 DOWNTO 0),B4=>B8(3 DOWNTO 0),S4=>S8(3 DOWNTO 0),CO4=>SC);U2:ADDER4B PORT MAP(C4=>SC,A4=>A8(7 DOWNTO 4),B4=>B8(7 DOWNTO 4),S4=>S8(7 DOWNTO 4),CO4=>CO8);END ARCHITECTURE ART;CTRLS的VHDL程序--CTRLS.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CTRLS ISPORT(CLK: IN STD_LOGIC;SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));END ENTITY CTRLS;ARCHITECTURE ART OF CTRLS ISSIGNAL CNT:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(CLK) ISBEGINIF CLK'EVENT AND CLK='1' THENIF CNT="111" THENCNT<="000";ELSECNT<=CNT+'1';END IF;END IF;END PROCESS;SEL<=CNT;END ARCHITECTURE ART;DISPLAY的VHDL程序--DISPLAY.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DISPLAY ISPORT( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- DATAIN: IN STD_LOGIC_VECTOR(15 DOWNTO 0); DATAIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0); COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY DISPLAY;ARCHITECTURE ART OF DISPLAY ISSIGNAL DATA: STD_LOGIC_VECTOR(3 DOWNTO 0);-- SIGNAL DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINP1:PROCESS(SEL) ISBEGINCASE SEL ISWHEN"000"=>COM<="11111110";WHEN"001"=>COM<="11111101";WHEN"010"=>COM<="11111011";WHEN"011"=>COM<="11110111";WHEN"100"=>COM<="11101111";WHEN"101"=>COM<="11011111";WHEN"110"=>COM<="10111111";WHEN"111"=>COM<="01111111";WHEN OTHERS=>COM<="11111111";END CASE;END PROCESS P1;--LEDW<=SEL;P2:PROCESS(SEL)BEGINCASE SEL ISWHEN"000"=>DATA<=DATAIN(3 DOWNTO 0);WHEN"001"=>DATA<=DATAIN(7 DOWNTO 4);-- WHEN"010"=>DATA<=DATAIN(11 DOWNTO 8);-- WHEN"011"=>DATA<=DATAIN(15 DOWNTO 12); WHEN OTHERS=>DATA<="0000";END CASE;CASE DATA ISWHEN"0000"=>SEG<="00111111";WHEN"0001"=>SEG<="00000110";WHEN"0010"=>SEG<="01011011";WHEN"0011"=>SEG<="01001111";WHEN"0100"=>SEG<="01100110";WHEN"0101"=>SEG<="01101101";WHEN"0110"=>SEG<="01111101";WHEN"0111"=>SEG<="00000111";WHEN"1000"=>SEG<="01111111";WHEN"1001"=>SEG<="01101111";WHEN OTHERS=>SEG<="00000000";END CASE;END PROCESS P2;END ARCHITECTURE ART;ADDER8B动态扫描的VHDL程序--ADDER8B.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER8B ISPORT(C8: IN STD_LOGIC;A8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);B8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK:IN STD_LOGIC;-- S8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); S8: BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0); CO8: OUT STD_LOGIC ;COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY ADDER8B;ARCHITECTURE ART OF ADDER8B IS--COMPONENT ADDER4BCOMPONENT ADDER4B ISPORT(C4: IN STD_LOGIC;A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CO4: OUT STD_LOGIC );END COMPONENT ADDER4B;--COMPONENT CTRLSCOMPONENT CTRLS ISPORT(CLK: IN STD_LOGIC;SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END COMPONENT CTRLS;--COMPONENT DISPLAYCOMPONENT DISPLAY ISPORT(SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);--DATAIN: IN STD_LOGIC_VECTOR(15 DOWNTO 0);DATAIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT DISPLAY;SIGNAL SC: STD_LOGIC;SIGNAL SB: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINU1:ADDER4B PORT MAP(C4=>C8,A4=>A8(3 DOWNTO 0),B4=>B8(3 DOWNTO 0),S4=>S8(3 DOWNTO 0),CO4=>SC);U2:ADDER4B PORT MAP(C4=>SC,A4=>A8(7 DOWNTO 4),B4=>B8(7 DOWNTO 4),S4=>S8(7 DOWNTO 4),CO4=>CO8);U3:CTRLS PORT MAP(CLK,SB);U4:DISPLAY PORT MAP(SB,S8(7 DOWNTO 0),COM(7 DOWNTO 0),SEG(7 DOWNTO 0));END ARCHITECTURE ART;3）仿真波形设置本设计包括两个层次，因此先进行底层的二进制加法器ADDER4B的仿真，再进行顶层ADDER8B的仿真。