STM32F103VC初始化程序
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#include"ST_M3_header.h"
/************* APB2ʱÖÓʹÄÜ ****************/ #define AFIO_EN (uint32_t)1 << 0
#define IOPA_EN (uint32_t)1 << 2
#define IOPB_EN (uint32_t)1 << 3
#define IOPC_EN (uint32_t)1 << 4
#define IOPD_EN (uint32_t)1 << 5
#define IOPE_EN (uint32_t)1 << 6
#define IOPF_EN (uint32_t)1 << 7
#define IOPG_EN (uint32_t)1 << 8
#define ADC1_EN (uint32_t)1 << 9
#define ADC2_EN (uint32_t)1 << 10
#define TIM1_EN (uint32_t)1 << 11
#define SPI1_EN (uint32_t)1 << 12
#define TIM8_EN (uint32_t)1 << 13
#define USART1_EN (uint32_t)1 << 14
#define ADC3_EN (uint32_t)1 << 15
/************* APB1ʱÖÓʹÄÜ ****************/ #define TIM2_EN (uint32_t)0x01
#define TIM3_EN (uint32_t)0x02
#define TIM4_EN (uint32_t)0x04
#define TIM5_EN (uint32_t)0x08
#define TIM6_EN (uint32_t)0x10
#define TIM7_EN (uint32_t)0x20
#define WWDG_EN (uint32_t)0x800
#define SPI2_EN (uint32_t)0x4000
#define SPI3_EN (uint32_t)0x8000
#define USART2_EN (uint32_t)0x20000
#define USART3_EN (uint32_t)0x40000
#define USART4_EN (uint32_t)0x80000
#define USART5_EN (uint32_t)0x100000
#define I2C1_EN (uint32_t)0x200000
#define I2C2_EN (uint32_t)0x400000
#define USB_EN (uint32_t)0x800000
#define CAN_EN (uint32_t)0x2000000
#define BKP_EN (uint32_t)0x8000000
#define PWR_EN (uint32_t)0x10000000
#define DAC_EN (uint32_t)0x20000000
/************* APBʱÖÓʹÄÜ ****************/
#define DMA1_EN (uint32_t)1 << 0
#define DMA2_EN (uint32_t)1 << 1
#define SRAM_EN (uint32_t)1 << 2
#define FLITF_EN (uint32_t)1 << 4
#define CRC_EN (uint32_t)1 << 6
#define FSMC_EN (uint32_t)1 << 8
#define SDIO_EN (uint32_t)1 << 10
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
void init_rcc(void) {
/************* ³õʼ»¯ÍⲿʱÖÓ ****************/
RCCP -> CR.HSEON = 0 ;
RCCP -> CR.HSEBYP = 0 ;
RCCP -> CR.HSERDY = 0 ;
RCCP -> CR.HSEON = 1 ;
while(!(RCCP -> CR.HSERDY));
/************** Íⲿ³ÜÏßÅäÖà ***************/
RCCP -> CFGR.HPRE = 0 ; //AHBÔ¤²ÖƵ
RCCP -> CFGR.PPRE2 = 0 ; //¸ßËÙAPBÔ¤²ÖƵ£¨APB2£©
RCCP -> CFGR.PPRE1 = 4 ; //µÍËÙAPBÔ¤²ÖƵ£¨APB1£©
RCCP -> CFGR.ADCPRE = 2 ; /* ADCCLK = PCLK2/6 ADC³ª»»ËÙÂÊ£º72M/6 = 12MHZ */
/************** FLASH´æ´¢ÉèÖà ***************/
FLASH -> ACR &= ((u32)0x00000038); //ÇåÁãijЩλ/* Flash 2 wait state */
FLASHP -> TENCY = 2; //72mhz,2ÖÜÆÚÑÓʱ
FLASHP -> ACR.PRFTBE = 1; //Ԥȡ»º³åÇøʹÄÜ
/************** PLLʱÖÓÉèÖà ***************/
RCCP -> CFGR.PLLXTPRE = 0 ; //HSE³ðΪʱÖÓÊäÈ룬²»²ÖƵ
RCCP -> CFGR.PLLSRC = 1 ; //PLLʱÖÓÔ´Ñ¡Ôñ
RCCP -> CFGR.PLLMUL = 4 ; //PLL±¶Æµ
/************** PLLʱÖÓʹÄÜ ***************/
RCCP -> CR.PLLON = 1 ;
while(!(RCCP -> CR.PLLRDY));
/************** ϵͳʱÖÓÇл»***************/
RCCP -> CFGR.SW = 0 ;
RCCP -> CFGR.SW = 2 ;
while((RCCP -> CFGR.SWS) != 2);
/************** ÍâÉèʱÖÓʹÄÜ ***************/
RCC -> APB2ENR |=
TIM1_EN
| ADC1_EN
| AFIO_EN
| IOPA_EN
| IOPB_EN
| IOPC_EN