数字秒表实验报告

EDA课程设计

题目：基于VHDL的数字秒表设计

学生姓名

学号

学院电子信息学院

专业 10通信工程

指导教师

二零一二年十二月

基于VHDL的数字秒表设计

摘要

当前电子系统的设计正朝着速度快，容量大，体积小，质量轻，省电的方向发展。推动该潮流迅速发展的决定性因素就是使用了现代化的EDA设计工具。此次课程设计先确定了系统的逻辑功能，选择电路结构，然后确定并设计电路所需的数据处理以及控制模块，在Quartus II上以超高速硬件描述语言VHDL为系统逻辑描述方法完成了数字秒表所需的分频模块，十进制计数控制模块，六进制计数控制模块与顶层设计和引脚分配，对其进行编译仿真，并下载到实验板上实际验证，通过本设计锻炼了计算机应用能力、VHDL语言的编程能力和Quartus II 的使用能力，此次设计圆满完成了用VHDL语言设计1/1000秒数字秒表并仿真和实际下载到ALTERA公司的ACEX1K系列的EP1K30TC144-3中实现。

关键词：EDA、Quartus II、VHDL、模块、仿真、ACEX1K

Abstract

The electronic system design is moving speed, large capacity, small volume, light weight, energy saving direction. The trend of rapid development of determinant is the use of modern EDA design tools. This course is designed to determine the logic function of the system, establish the algorithm process, selection of circuit structure and circuit design, and then determine the desired data processing and control module, in the Quartus II to very high speed hardware description language VHDL as the system logical description method for completing the digital stopwatch desired frequency module, decimal counting control module, base six counting control module with top design and pin assignment, the compiled simulation, and downloaded to the experiments on actual test and verify, through the design of exercise ability of computer application and VHDL programming language and Quartus II using capability, the design was completed by VHDL language design 1\/1000 seconds stopwatch and simulation and the actual download to ALTERA company's ACEX1K series EP1K30TC144-3 implementation.

Key Words：EDA、Quartus II、VHDL、Module、Simulation、ACEX1K

目录

摘要----------------------------------------------------------------2 Abstract------------------------------------------------------------2

一、设计要求--------------------------------------------------------4

二、设计思想与方案论证----------------------------------------------4

2.1 设计思想----------------------------------------------------4

2.2 方案论证----------------------------------------------------4

三、系统设计--------------------------------------------------------5

3.1 顶层电路设计------------------------------------------------5

3.2时钟分频电路模块---------------------------------------------6

3.3十进制计数控制模块-------------------------------------------7

3.4六进制计数控制模块-------------------------------------------7

四、系统仿真--------------------------------------------------------8

4.1 模块仿真----------------------------------------------------8

4.1.1 时钟分频电路模块仿真 ----------------------------------8

4.1.2 十进制计数控制模块仿真---------------------------------9

4.1.3 六进制计数控制模块仿真---------------------------------9

4.2 总体仿真---------------------------------------------------10

五、下载实现--------------------------------------------------------10

5.1 引脚分配---------------------------------------------------11

5.2 下载验证---------------------------------------------------11

六、问题与不足-----------------------------------------------------13

七、心得体会-------------------------------------------------------13

参考文献-----------------------------------------------------------14

附录---------------------------------------------------------------14

附录1 ：本设计各模块代码-------------------------------------------14