超大规模集成电路第八次作业2016秋,段成华

Assignment 8

1.Access relevant reference books or technical data books and give accurate

definitions for the following timing parameters:

(1)design entity,

(2)signal driver,

(3)transaction,

(4)event,

(5)time queue,(6)delta delay,

(7)simulation time,

(8)simulation cycle,

(9)inertial time,

(10)transport time.

(1)design entity: In VHDL a given logic circuit represented as a design entity. A

design entity, in return , consists of two different types of description: the interface description and one or more architectural bodies. The interface description declares the entity and describes its inputs and outputs.

(2)signal driver: If a process contains one or more signal assignment statement

that schedule future values for some signal X, the VHDL simulator creates a single value holder called a signal driver.

(3)transaction:A pair consisting of a value and time. The value part represents a

future value of the driver; the time part represents the time at which the value part becomes the current value of driver.

(4)event: It’s a kind of signal property and presents signal jump. Such as

if(clk'event and clk='1).

(5)time queue: It’s used to keep some signal transactions in the simulator. Time

queue entries are represented as a two-tuple of the form(SN,V), where SN is a signal name and V is the value the signal is scheduled to assume at the scheduled time. Each time queue entry is called a signal transaction.

(6)delta delay: A period of time greater than 0, but less than any standard time unit

no number of delta delay added together can cause simulation time to advance.

(7)simulation time: The elapsed time in standard time units during simulation.

(8)simulation cycle: Every time simulation time advances, a simulation cycle

occurs, which we now define more formally. The execution of a model consists of an initialization phase followed by the repetitive execution of processes in the process network. Each repetition is said to be a simulation cycle.

(9)inertial time: Example: Z <= I after 10ns; The signal propagation will take

place if and only if input I persists at a given level for 10ns-the amount of time specified in the after clause.

(10)transport time: Z <= transport I after 10ns; All changes on I will propagate to

Z, regardless of how long the value of I stays at the new level.

2.Construct VHDL models for 74-139 dual 2-to-4-line decoders using three

description types, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.