VHDL流水灯简单实例
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--此例编译通过，瑕疵难免。
libraryieee;
use ieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitylianxi is
generic(fpbz:integer:=98000000);
port(clk:instd_logic;
rst:instd_logic;
fclk:outstd_logic);
endlianxi;
architecture behave of lianxi is
signalcounter:integer range 0 to fpbz-1;
begin
fclk<='1'when(counter process(clk,rst) begin if(counter=fpbz-1 or rst='0')then counter<=0; elsif(counter end if; end process; end behave; libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; entityjs is port(fclk:instd_logic; rst:instd_logic; A:outstd_logic_vector(2 downto 0)); endjs; architecture behave of js is signalcounter:std_logic_vector(2 downto 0); begin A<=counter; process(fclk,rst) begin if(rst='0')then counter<=(others=>'0'); elsif(fclk'event and fclk='1')then if(counter(2 downto 0)="111")then counter<=(others=>'0'); else counter<=counter+1; end if; end if; end process; end behave; libraryieee; use ieee.std_logic_1164.all; entityym is port(A:instd_logic_vector(2 downto 0); led:outstd_logic_vector(7 downto 0)); endym; architecture behave of ym is begin with A select led<= "00000000"when"000", "10000001"when"001", "11000011"when"010", "11100111"when"011", "11111111"when"100", "00011000"when"101", "00111100"when"110", "01111110"when"111", "11011011"when others; end behave;