HIGH SPEED AND LOW POWER DYNAMIC LATCH COMPARATOR
UCC2813D-1中文资料
UCC2813-0/-1/-2/-3/-4/-5UCC3813-0/-1/-2/-3/-4/-5FEATURES100µA Typical Starting Supply Current 500µA Typical Operating Supply Current Operation to 1MHz Internal Soft Start Internal Fault Soft StartInternal Leading-Edge Blanking of the Current Sense Signal 1 Amp Totem-Pole Output70ns Typical Response fromCurrent-Sense to Gate Drive Output 1.5% Tolerance Voltage Reference Same Pinout as UCC3802, UC3842, and UC3842ADESCRIPTIONThe UCC3813-0/-1/-2/-3/-4/-5family of high-speed,low-power inte-grated circuits contain all of the control and drive components required for off-line and DC-to-DC fixed frequency current-mode switching power supplies with minimal parts count.These devices have the same pin configuration as the UC3842/3/4/5family,and also offer the added features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input.The UCC3813-0/-1/-2/-3/-4/-5family offers a variety of package options,temperature range options,choice of maximum duty cycle,and choice of critical voltage levels.Lower reference parts such as the UCC3813-3and UCC3813-5fit best into battery operated systems,while the higher reference and the higher UVLO hysteresis of the UCC3813-2and UCC3813-4 make these ideal choices for use in off-line power supplies.The UCC2813-x series is specified for operation from –40°C to +85°C and the UCC3813-x series is specified for operation from 0°C to +70°C.BLOCK DIAGRAMLow Power Economy BiCMOSCurrent Mode PWMUDG-96134Part Number Maximum Duty CycleReference VoltageTurn-On ThresholdTurn-Off ThresholdUCCx813-0100%5V 7.2V 6.9V UCCx813-150%5V 9.4V 7.4V UCCx813-2100%5V 12.5V 8.3V UCCx813-3100%4V 4.1V 3.6V UCCx813-450%5V 12.5V 8.3V UCCx813-550%4V4.1V3.6VORDERING INFORMATIONCONNECTION DIAGRAMSVCC Voltage (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . .12.0V VCC Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30.0mA OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0A OUT Energy (Capacitive Load). . . . . . . . . . . . . . . . . . .20.0µJ Analog Inputs (FB, CS). . . . . . . . . . . . . . . . . . . .–0.3V to 6.3V Power Dissipation at T A < +25°C (N Package). . . . . . . . . 1.0W Power Dissipation at T A < +25°C (D Package). . . . . . . .0.65W Storage Temperature . . . . . . . . . . . . . . . . . . .–65C to +150°C Junction Temperature. . . . . . . . . . . . . . . . . . .–55C to +150°C Lead Temperature (Soldering, 10 Seconds). . . . . . . . .+300°CABSOLUTE MAXIMUM RATINGS (Note 1)Note 1:All voltages are with respect to GND.All currents are positive into the specified terminal.Consult Unitrode Integrated Circuits databook for information regarding thermal specifica-tions and limitations of packages.Note 2:In normal operation VCC is powered through a current limiting resistor.Absolute maximum of 12V applies when VCC is driven from a low impedance source such that ICC does not exceed 30mA.UCCPACKAGETEMPERATURE RANGEPRODUCT OPTION ORDERING INFORMATIONTEMPERATURE RANGEPACKAGES UCC2813–40°C TO +85°C N, D,PW UCC38130°C TO +70°CN, D,PWELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –40°C ≤T A ≤+85°C forUCC2813-x; 0°C ≤T A ≤+70°C for UCC3813-x;VCC = 10V (Note 3); RT = 100k from REF to RC; CT=330pF from RC to GND;0.1µF capacitor from VCC to GND; 0.1µF capacitor from VREF to GND. T A =T J .PARAMETERTEST CONDITIONSUCC2813-x UCC3813-xUNITSMINTYPMAXReference Section Output Voltage T J = +25°C, I = 0.2mA, UCCx813-0/-1/-2/-4 4.925 5.00 5.075V T J = +25°C, I = 0.2mA, UCCx813-5 3.944.00 4.06V Load Regulation 0.2mA <I <5mA1030mV Total Variation UCCx813 -0-1/-2/-4 (Note 7) 4.84 5.00 5.10V UCCx813-5 (Note 7)3.844.00 4.08V Output Noise Voltage 10Hz ≤f ≤10kHz,T J = +25°C (Note 9)70µV Long Term Stability T A = +125C, 1000 Hours (Note 9)5mV Output Short Circuit –5–35mAOscillator Section Oscillator Frequency UCCx813-0/-1/-2/-4 (Note 4)404652kHz UCCx813-5 (Note 4)263136kHz Temperature Stability (Note 9)2.5%Amplitude Peak-to-Peak 2.25 2.40 2.55V Oscillator Peak Voltage2.45VELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –40°C≤T A≤+85°C for UCC2813-x; 0°C≤T A≤+70°C for UCC3813-x;VCC= 10V (Note 3); RT = 100k from REF to RC; CT=330pF from RC to GND;0.1µF capacitor from VCC to GND; 0.1µF capacitor from VREF to GND. T A=T J.PARAMETER TEST CONDITIONSUCC2813-xUCC3813-x UNITS MIN TYP MAXError Amplifier SectionInput Voltage COMP= 2.5V; UCCx813-0/-1/-2/-4 2.42 2.50 2.56VCOMP= 2.0V; UCCx813-3/-5 1.92 2.0 2.05V Input Bias Current–22µA Open Loop Voltage Gain6080dB COMP Sink Current FB = 2.7V,COMP= 1.1V0.4 2.5mA COMP Source Current FB = 1.8V,COMP= REF – 1.2V–0.2–0.5–0.8mA Gain Bandwidth Product(Note 9)2MHz PWM SectionMaximum Duty Cycle UCCx813-0/-2/-39799100%UCCx813-1/-4/-5484950 Minimum Duty Cycle COMP= 0V0% Current Sense SectionGain(Note 5) 1.10 1.65 1.80V/V Maximum Input Signal COMP= 5V (Note 6)0.9 1.0 1.1V Input Bias Current–200200nA CS Blank Time50100150ns Over-Current Threshold 1.32 1.55 1.70V COMP to CS Offset CS = 0V0.450.90 1.35V Output SectionOUT Low Level I = 20mA, all parts0.10.4VI = 200mA, all parts0.350.90VI = 50mA,VCC= 5V, UCCx813-3/-50.150.40VI = 20mA,VCC= 0V, all parts0.7 1.2VOUT High V SAT (V CC-OUT)I = –20mA, all parts0.150.40V I = –200mA, all parts 1.0 1.9V I = –50mA,VCC= 5V, UCCx813-3/-50.40.9VRise Time C L= 1nF4170ns Fall Time C L= 1nF4475ns Undervoltage Lockout SectionStart Threshold (Note 8)UCCx813-0 6.67.27.8VUCCx813-18.69.410.2VUCCx813-2/-411.512.513.5VUCCx813-3/-5 3.7 4.1 4.5V Stop Threshold (Note 8)UCC1813-0 6.3 6.97.5VUCC1813-1 6.87.48.0VUCCx813-2/-47.68.39.0VUCCx813-3/-5 3.2 3.6 4.0V Start to Stop Hysteresis UCCx813-00.120.30.48VUCCx813-1 1.62 2.4VUCCx813-2/-4 3.5 4.2 5.1VUCCx813-3/-50.20.50.8VELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –40°C≤T A≤+85°C for UCC2813-x; 0°C≤T A≤+70°C for UCC3813-x;VCC= 10V (Note 3); RT = 100k from REF to RC; CT=330pF from RC to GND;0.1µF capacitor from VCC to GND; 0.1µF capacitor from VREF to GND. T A=T J.PARAMETER TEST CONDITIONSUCC2813-xUCC3813-x UNITS MIN TYP MAXSoft Start SectionCOMP Rise Time FB = 1.8V, Rise from 0.5V to REF–1V4ms Overall SectionStart-up Current VCC< Start Threshold0.10.23mA Operating Supply Current FB = 0V, CS = 0V, RC = 0V0.5 1.2mA VCC Internal Zener Voltage ICC = 10mA (Note 8)1213.515V VCC Internal Zener Voltage Minus StartThreshold VoltageUCCx813-2/-40.5 1.0VNote 3: Adjust VCC above the start threshold before setting at 10V.Note 4: Oscillator frequency for the UCCx813-0, UCCx813-2 and UCCx813-3 is the output frequency.Oscillator frequency for the UCCx813-1, UCCx813-4 and UCCx813-5 is twice the output frequency.Note 5: Gain is defined by:A VVV V COMPCSCS≤≤008..Note 6: Parameter measured at trip point of latch with Pin 2 at 0V.Note 7: Total Variation includes temperature stability and load regulation.Note 8: Start Threshold, Stop Threshold and Zener Shunt Thresholds track one another. Note 9: Guaranteed by design. Not 100% tested in production.COMP:COMP is the output of the error amplifier and the input of the PWM comparator.Unlike other devices,the error amplifier in the UCC3813 family is a true,low output-impedance,2MHz operational amplifier.As such,the COMP terminal can both source and sink current.However,the error amplifier is internally current limited,so that you can command zero duty cycle by externally forcing COMP to GND.The UCC3813family features built-in full cycle Soft Start. Soft Start is implemented as a clamp on the maximum COMP voltage.FB:FB is the inverting input of the error amplifier.For best stability,keep FB lead length as short as possible and FB stray capacitance as small as possible.CS:CS is the input to the current sense comparators. The UCC3813family has two different current sense comparators:the PWM comparator and an over-current comparator.The UCC3813family contains digital current sense filter-ing,which disconnects the CS terminal from the current sense comparator during the100ns interval immediately following the rising edge of the OUT pin.This digital filter-ing,also called leading-edge blanking,means that in most applications,no analog filtering(RC filter)is re-quired on pared to an external RC filter tech-nique,the leading-edge blanking provides a smaller effective CS to OUT propagation delay.Note,however, that the minimum non-zero On-Time of the OUT signal is directly affected by the leading-edge-blanking and the CS to OUT propagation delay.The over-current comparator is only intended for fault sensing,and exceeding the over-current threshold will cause a soft start cycle.RC:RC is the oscillator timing pin.For fixed frequency operation,set timing capacitor charging current by con-necting a resistor from REF to RC.Set frequency by con-necting a timing capacitor from RC to GND.For best performance,keep the timing capacitor lead to GND as short and direct as possible.If possible,use separate ground traces for the timing capacitor and all other func-tions.PIN DESCRIPTIONSThe frequency of oscillation can be estimated with the following equations:UCCx813-0/-1/-2/-4:F R C=•15.UCCx813-3, UCCx813-5:F R C=•10.where frequency is in Hz,resistance is in Ω,and capaci-tance is in farads.The recommended range of timing re-sistors is between 10k and 200k and timing capacitor is 100pF to 1000pF .Never use a timing resistor less than 10k.GND:GND is reference ground and power ground for all functions on this part.OUT:OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750mA.OUT is actively held low when VCC is below the UVLO threshold.The high-current power driver consists of FET output de-vices,which can switch all of the way to GND and all of the way to VCC.The output stage also provides a very low impedance to overshoot and undershoot.This means that in many cases,external schottky clamp diodes are not required.VCC:VCC is the power input connection for this device.In normal operation VCC is powered through a current limiting resistor.Although quiescent VCC current is verylow,total supply current will be higher,depending on OUT current.Total VCC current is the sum of quiescent VCC current and the average OUT current.Knowing the operating frequency and the MOSFET gate charge (Qg),average OUT current can be calculated from:I Q F OUT g =•.To prevent noise problems,bypass VCC to GND with a ceramic capacitor as close to the VCC pin as possible.An electrolytic capacitor may also be used in addition to the ceramic capacitor.REF:REF is the voltage reference for the error amplifier and also for many other functions on the IC.REF is also used as the logic power supply for high speed switching logic on the IC.When VCC is greater than 1V and less than the UVLO threshold,REF is pulled to ground through a 5k Ωresis-tor.This means that REF can be used as a logic output indicating power system status.It is important for refer-ence stability that REF is bypassed to GND with a ce-ramic capacitor as close to the pin as possible.An electrolytic capacitor may also be used in addition to the ceramic capacitor.A minimum of 0.1µF ceramic is re-quired.Additional REF bypassing is required for external loads greater than 2.5mA on the reference.To prevent noise problems with high speed switching transients,bypass REF to ground with a ceramic capaci-tor very close to the IC package.PIN DESCRIPTIONS (cont.)APPLICATION INFORMATION4.003.983.963.943.923.903.883.863.843.8244.24.44.64.855.25.45.65.86V (V)CC V (V )R E F Figure 5.UCC3813-3/-5V REF vs.V CC ;I LOAD= 0.5mA.APPLICATION INFORMATION (cont.)T and C T.R T and C T .oscillator frequency.oscillator frequency.CC APPLICATION INFORMATION (cont.)CCCS = 0V.T T UNITRODE CORPORA TION7 CONTINENTAL BLVD.• MERRIMACK, NH 03054TEL.(603) 424-2410 • FAX (603) 424-3460IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。
IRS2003STRPbF中文资料
Data Sheet No. PD60269Typical ConnectionProduct SummaryV OFFSET 200 V max.I O +/-130 mA/270 mA V OUT 10 V - 20 V t on/off (typ.)680 ns/150 nsDeadtime (typ.)520 nsHALF-BRIDGE DRIVERFeatures•Floating channel designed for bootstrap operation •Fully operational to +200 V•Tolerant to negative transient voltage, dV/dtimmune•Gate drive supply range from 10 V to 20 V •Undervoltage lockout•3.3 V, 5 V, and 15 V logic compatible •Cross-conduction prevention logic•Matched propagation delay for both channels •Internal set deadtime•High -side output in phase with HIN input •Low -side output out of phase with LIN input DescriptionThe IRS2003 is a high voltage, high speed power MOSFE T and IGBT drivers wi th dependent high - and low -side referenced output channels. Proprietary HVICand latch immune CMOS technologies enable rugge-dized monolithic construction. The logic input iscompatible with standard CMOS or LSTTL output, downto 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high -side configuration which operates up to 200 V. 1IRS2003(S)PbFPackages8-Lead PDIP IRS20038-Lead SOIC IRS2003S • RoHS compliantIRS2003(S)PbFAbsolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.Note 1: Logic operational for V S of -5 V to +200 V. Logic state held for V S of -5 V to -V BS . (Please refer to the Design Tip DT97-3 for more details).IRS2003(S)PbFStatic Electrical CharacteristicsV BIAS (V CC, V BS) = 15 V and T A = 25 °C unless otherwise specified. The V IN, V TH, and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Dynamic Electrical CharacteristicsV BIAS (V CC, V BS) = 15 V, C L = 1000 pF and T A = 25 °C unless otherwise specified.IRS2003(S)PbFLead DefinitionsSymbol DescriptionHIN Logic input for high -side gate driver output (HO), in phase Logic input for low-side gate driver output (LO), out of phase V B High -side floating supply HO High -side gate drive output V S High -side floating supply return V CC Low-side and logic fixed supply LO Low -side gate drive output COMLow -side returnLIN Lead Assignments8 Lead PDIP 8 Lead SOICIRS2003PbF IRS2003SPbF12348765V CC HIN LIN COMV B HO V S LO12348765V CC HIN LIN COMV B HO V S LOIRS2003(S)PbFLINHOLOHINFigure 3. Deadtime Waveform DefinitionsFigure 2. Switching Time Waveform DefinitionsLOIRS2003(S)PbFIRS2003(S)PbF8-50-250255075100125Temperature (oC)Figure 10A. Logic "0"(HIN) & Logic "1" ( )Input Voltage vs. TemperatureLINIRS2003(S)PbFIRS2003(S)PbFIRS2003(S)PbF10vs. Temperaturevs. VoltageFigure 17A. Logic "0" Input Bias Currentvs. TemperatureFigure 17B. Logic "0" Input Bias Currentvs. VoltageL o g i c “0” I n p u t B i a s C u r r e n t (µA )0123456-50-250255075100125Temperature (°C)F ig u r e 17A. L o g ic "0" I n p u t B ia s C u r r e n t 0123456101214161820Supply Voltage (V)Case OutlinesCTape & Reel 8-lead SOICPer SCOP 200-002The SOIC-8 is MSL 2 qualified.This product has been designed and qualified for the industrial level.Qualification standards can be found at Data and specifications subject to change without notice. 11/27/2006。
IR2110.PDF
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation
Fully operational to +500V or +600V
14-Lead PDIP IR2110/IR2113
16-Lead SOIC IR2110S/IR2113S
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
Product Summary
VOFFSET (IR2110) 500V max. (IR2113) 600V max.
IO+/-
2A / 2A
VOUT
10 - 20V
ton/off (typ.)
120 & 94 ns
Delay Matching (IR2110) 10 ns max. (IR2113) 20ns max.
Symbol
ton toff tsd tr tf MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Shutdown propagation delay
74LVC245A_04中文资料
1/12July 2004s 5V TOLERANT INPUTSs HIGH SPEED: t PD = 6.3ns (MAX.) at V CC = 3V sPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN) at V CC = 3Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 1.65V to 3.6V (1.2V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245sLATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)sESD PERFORMANCE:HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74LVC245A is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for 1.65 to 3.6V CC operations and low power and low noise applications.This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated.It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.All floating bus terminals during High Z State must be held HIGH or LOW.74LVC245ALOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(NOT INVERTED) HIGH PERFORMANCE.Table 1: Order CodesPACKAGE T & R SOP 74LVC245AMTR TSSOP74LVC245ATTR74LVC245A2/12Figure 2: Input And Output Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareZ : High ImpedanceTable 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied1) I O absolute maximum rating must be observed 2) V O< GNDPIN N°SYMBOL NAME AND FUNCTION 1DIR Directional Control 2, 3, 4, 5, 6, 7, 8, 9A1 to A8Data Inputs/Outputs 18, 17, 16, 15, 14, 13, 12, 11B1 to B8Data Inputs/Outputs19GOutput Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTS FUNCTION OUTPUT G DIR A BUSB BUSYn L L OUTPUT INPUT A = B L H INPUT OUTPUT B = A HXZ ZZSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage-0.5 to +7.0V V O DC Output Voltage (High Impedance or V CC = 0V)-0.5 to +7.0V V O DC Output Voltage (High or Low State) (note 1)-0.5 to V CC + 0.5V I IK DC Input Diode Current- 50mA I OK DC Output Diode Current (note 2)- 50mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current per Supply Pin± 100mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°C74LVC245A3/12Table 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.2V to 3.6V 2) V IN from 0.8V to 2V at V CC = 3.0VTable 6: DC SpecificationsSymbol ParameterValue Unit V CC Supply Voltage (note 1) 1.65 to 3.6V V I Input Voltage0 to 5.5V V O Output Voltage (High Impedance or V CC = 0V)0 to 5.5V V O Output Voltage (High or Low State)0 to V CC V I OH , I OL High or Low Level Output Current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or Low Level Output Current (V CC = 2.7 to 3.0V)± 12mA I OH , I OL High or Low Level Output Current (V CC = 2.3 to 2.7V)±8mA I OH , I OL High or Low Level Output Current (V CC = 1.65 to 2.3V)±4mA T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2)0 to 10ns/VSymbolParameterTest ConditionValueUnitV CC (V)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.V IHHigh Level Input Voltage 1.65 to 1.950.65V CC0.65V CC V2.3 to 2.7 1.7 1.72.7 to3.622V ILLow Level Input Voltage1.65 to 1.950.35V CC0.35V CC V 2.3 to 2.70.70.72.7 to 3.60.80.8V OHHigh Level Output Voltage1.65 to 3.6I O =-100 µA V CC -0.2V CC -0.2V1.65I O =-4 mA 1.2 1.22.3I O =-8 mA 1.7 1.72.7I O =-12 mA 2.2 2.23.0I O =-18 mA 2.4 2.43.0I O =-24 mA 2.22.2V OLLow Level Output Voltage1.65 to 3.6I O =100 µA 0.20.2V 1.65I O =4 mA 0.450.452.3I O =8 mA 0.70.72.7I O =12 mA 0.40.43.0I O =24 mA 0.550.55I I Input Leakage Current 3.6V I = 0 to 5.5V ± 5± 5µA I off Power Off Leakage Current0V I or V O = 5.5V 1010µA I OZHigh Impedance Output Leakage Current3.6V I = V IH orV IL V O = 0 to 5.5V ± 10± 10µA I CCQuiescent Supply Current3.6V I = V CC or GND1010µA V I or V O = 3.6 to5.5V± 10± 10∆I CCI CC incr. per Input2.7 to3.6V IH = V CC -0.6V500500µA74LVC245A4/12Table 7: Dynamic Switching Characteristics1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.Table 8: AC Electrical Characteristics1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |2) Parameter guaranteed by designTable 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /n (per circuit)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.V OLP Dynamic Low Level Quiet Output (note 1)3.3C L = 50pFV IL = 0V, V IH = 3.3V0.8V V OLV-0.8SymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.t PLH t PHLPropagation Delay Time1.65 to 1.953010002.0 2.09.0 2.012ns2.3 to 2.730500 2.0 2.08.0 2.010.52.750500 2.5 1.57.3 1.58.83.0 to 3.650500 2.5 1.0 6.3 1.07.6t PZL t PZHOutput Enable Time 1.65 to 1.95301000 2.0 2.012 2.016ns2.3 to 2.730500 2.0 2.09.5 2.012.52.750500 2.5 1.09.0 1.0113.0 to 3.650500 2.5 1.08.5 1.010t PLZ t PHZOutput Disable Time 1.65 to 1.95301000 2.0 2.011 2.014ns2.3 to 2.730500 2.0 2.09.0 2.0122.750500 2.5 2.08.5 2.0103.0 to 3.6505002.52.07.5 2.09.0t OSLH t OSHLOutput To Output Skew Time (note1, 2)2.7 to3.611nsSymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.C IN Input Capacitance4pF C PDPower Dissipation Capacitance (note 1)1.8f IN = 10MHz28pF 2.5303.33474LVC245A5/12Figure 3: Test CircuitR T = Z OUT of pulse generator (typically 50Ω)Table 10: Test Circuit And Waveform Symbol ValueFigure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)SymbolV CC1.65 to 1.95V2.3 to 2.7V 2.7V3.0 to 3.6V C L 30pF 30pF 50pF 50pF R L = R 11000Ω500Ω500Ω500ΩV S 2 x V CC 2 x V CC 6V 6V V IH V CC V CC 2.7V 2.7V V M VCC /2V CC /2 1.5V 1.5V V OH V CC V CC 3.0V 3.0V V X V OL + 0.15V V OL + 0.15V V OL + 0.3V V OL + 0.3V VY V OH - 0.15V V OH - 0.15V V OH - 0.3V V OH - 0.3V t r = t r<2.0ns<2.0ns<2.5ns<2.5ns74LVC245AFigure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)6/1274LVC245A7/12DIM.mm.inch MIN.TYPMAX.MIN.TYP.MAX.A 2.35 2.650.0930.104A10.10.300.0040.012B 0.330.510.0130.020C 0.230.320.0090.013D 12.6013.000.4960.512E 7.47.60.2910.299e 1.270.050H 10.0010.650.3940.419h 0.250.750.0100.030L 0.4 1.270.0160.050k 0°8°0°8°ddd0.1000.004SO-20 MECHANICAL DATA0016022D74LVC245A8/12DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 6.4 6.5 6.60.2520.2560.260E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP20 MECHANICAL DATAcEbA2AE1D1PIN 1 IDENTIFICATIONA1LK e0087225C74LVC245A Tape & Reel SO-20 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T30.4 1.197Ao10.8110.4250.433Bo13.213.40.5200.528Ko 3.1 3.30.1220.130Po 3.9 4.10.1530.161P11.912.10.4680.4769/1274LVC245ATape & Reel TSSOP20 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T22.40.882 Ao 6.870.2680.276 Bo 6.97.10.2720.280 Ko 1.7 1.90.0670.075 Po 3.9 4.10.1530.161 P11.912.10.4680.47610/1274LVC245A Table 11: Revision HistoryDate Revision Description of Changes26-Jul-20044Ordering Codes Revision - pag. 1.11/1274LVC245AInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America12/12。
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New Logic Family Achieves Highest Speeds at Lower Voltagesby Stephen Nolan and Ji Park, Texas InstrumentsWorkstations, servers, and other high-performance systems are reaching new heights in innovation daily. As these productsimprove, bus- and memory-interface devices must keep paceand must advance to greater speeds as well. Moreover, thesesystems require that this increased speed be coupled with lower power consumption. This imperative usually means a lowervoltage node. Also to function as viable solutions, these logicdevices must reach these faster and faster speeds withoutsacrificing signal integrity.Texas Instruments’ new logic family, the AVC (AdvancedVery-low-voltage CMOS) family, delivers both high speed and low power without reducing signal quality. AVC logic follows on the heels of TI’s ALVC (Advanced Low Voltage CMOS) logic, which helped engineers make the transition from 5-V to 3.3-Vdesigns beginning in 1994. Many designs are now migratingfrom 3.3-V to 2.5-V, creating new design challenges.Complicating this transition is the industry’s appetite for higher system speeds, which has driven bus speeds above the125-MHz mark (Figure 1). The AVC logic family is the firstlogic family in the industry with propagation delays of less than two nanoseconds (2 ns).High-speed logic usually generates significant undershoot andovershoot noise from the very fast signal transitions. Seriesdamping resistors are sometimes used to reduce electrical noise; but resistors, whether they are internal or external to the logic,also slow the speed of the signals through the circuitry. TheAVC family does not require series damping resistors to reduce electrical noise (Figure 2).TI has developed a unique innovation called Dynamic OutputControl (DOC™) (patent pending), which gives AVC logic "the best of both worlds." Specifically, AVC logic achieves very high signaling speeds because the circuitry behaves as though therewere no resistors in the output when a signal transition is taking place. Then, as the signal transition nears completion, circuitry is automatically activated that behaves as though there were series damping resistors on the output. This capability dramaticallyminimizes the signal undershoot or overshoot and effectivelymuffles electrical noise.In addition to high-speed and low electrical noise, AVCconsumes little power and is easy to design into a mixed-voltage system. Although AVC is very low power with its optimization for 2.5-V systems, it remains compatible with 3.3-V or even1.8-V components as well. In fact, AVC is operational from1.65 V to 3.6 V. Moreover, AVC logic can save battery lifesince it has a feature that supports partial power off--thusallowing the power to be turned off to portions of a systemwhen those sections are not in use.The AVC family is over-voltage tolerant at both the inputs and the outputs--a feature which helps the engineer who is facedwith a mixed voltage mode design. For example, if a design calls for interfacing a 2.5-V memory controller with 3.3-V memories, all the designer needs to do is place an AVC transceiver inbetween the memory controller and the memories. The AVCdevice, powered at 2.5 V, will provide reliable bi-directionaldata communication between the devices at these two voltagenodes. The data from the 3.3-V memories are accepted at theinputs of the AVC transceiver without any problems, since the transceiver’s inputs are over-voltage tolerant. Also, an AVCdriver or register device, powered at 1.8 V, can be used toprovide uni-directional data communication from devices at the 3.3-V or the 2.5-V nodes to devices at 1.8 V.Dynamic Output Control (DOC)The way the AVC family’s DOC circuitry handles high-speedsignals is similar to the way a race car driver negotiates an oval track. On the straight-aways, the driver can accelerate tomaximum speed. But, as he approaches a curve in the track, the driver must slow down or risk losing control of the car. In much the same way, DOC circuitry (Figure 3) allows the signaling to accelerate to its maximum speed during the transition from a low to a high state (or from a high to a low). Then, in much the same way that a race car driver eases off the accelerator as henegotiates a curve, the DOC circuitry reduces the power of the electrical signal when the transition nears completion. Thisreduction minimizes overshoot and undershoot noise that would otherwise be generated by a high-speed signal transition.Specifically, DOC lowers the output impedance of the circuitry at the beginning of a signal transition to drive the load at highspeeds. Then, as the end of transition is near, DOCautomatically raises the impedance to roll-off the signal and toreduce noise.(figure 4)The DOC effectively consists oftwo parallel drivers and animpedance control circuit (ZCC)that monitors the output signal.When the impedance controlcircuit senses that more current isneeded, the outputs of both theparallel drivers are enabled,thereby reducing the outputimpedance. As the signal passes through the threshold during a transition, the impedance control circuit disables the output ofone of the drivers, thereby increasing the output impedance.Obviously, the driver that is disabled does not contribute anyadditional drive current or loading to the output.Bus Hold™(figure 5)The bus hold feature was alsoincluded in the AVC family of logicdevices. Bus hold helps solve theproblem of floating inputs andeliminates the need for pull-up orpull-down resistors. With thetotem-pole structure that characterizesthe inputs of CMOS devices, theinput must be held as close to VCC orGND rails as possible. Precautions should be taken to preventthe input voltage from floating near the threshold voltagebecause this eventuality would bias both input transistors on and would create undesirably high ICC currents at the VCC pin of the device. One possible method would be to use pull-up orpull-down resistors, but these are costly and take up additionalcircuit-board area. An alternative solution is to use devices in the AVC family that utilize the optional bus-hold circuit at the inputs. AVC devices with bus-hold circuitry are designated AVCH.The bus-hold circuit consists of two series inverters with theoutput fed back to the input through a resistor. This arrangement provides a weak positive feedback by sinking or sourcingcurrent to the input node. The bus-hold circuit consists of twoseries inverters with the output fed back to the input through aresistor. This arrangement provides a weak positive feedbackby sinking or sourcing current to the input node. The bus-holdcell holds the input at its last known valid logic state until thisstate is forcibly changed by a driving circuit.A Full Family of LogicA comprehensive selection of AVC devices is planned forintroduction over the next two years. The AVC productportfolio will be comprised of gate, octal, Widebus™, andWidebus+™ logic devices. A complete selection of differentdevice types such as bus drivers and transceivers, buffers,flip-flops, latches, and address drivers will eventually find their way into the AVC family. Samples of the first four members of the AVC logic family should be available from TexasInstruments and its authorized distributors in the fourth quarter of 1998. Part numbers and anticipated resale pricing in quantitiesof 1000 are as follows: AVC16244 16-bit buffer $2.92,AVC16245 16-bit transceiver $2.92, AVC16373 16-bitD-type transparent latch $2.92, and AVC16374 16-bit D-typeflip-flop $2.92. Military versions of selected AVC functions are also planned.Top of PageAbout the AuthorsStephen Nolan is the senior applications engineer for TexasInstruments' CBT and CBTLV bus switches and the AVC(Advanced Very-low-voltage CMOS) logic family. Nolan hadpreviously worked in TI's BiPolar wafer fabrication family as a photo lithography engineer. He has a BS in electronicsengineering technology and a MS in electronics engineeringtechnology from Southeastern Oklahoma State University.Ji Park's Advanced Computing Solutions team at TI isresponsible for the strategic development of advanced logicdevices for PCs, workstations, and servers. Park received aBSEE from the University of Texas.。
比较器小信号延迟小信号仿真结果如...
东南大学模拟实训MPW流片报告课题名称:预放大再生比较器设计姓名:学号:指导老师:摘要比较器是电子系统中应用较为广泛的电路之一。
比较器的设计以开环高增益放大器的设计为基础。
虽然和运算放大器相比,比较器的应用范围相对狭窄,但比较器仍在很多应用中不可或缺,尤其在模数转换器(Analog-to-digital converters,简称ADC)中。
比较器作为流水线型ADC的关键模块,其速度、功耗等性能对整个模数转换器的速度和功耗都有着至关重要的影响。
在各种比较器结构中,预放大再生比较器速度快、功耗低、失调电压小,被广泛应用于高速比较器。
本文基于预放大再生理论,采用TSMC 3.3V 0.35μm CMOS 工艺,设计一种适用于流水线型ADC 的高速低功耗比较器电路。
该比较器由前置放大器,比较器和SR锁存电路构成。
经过Cadence软件下的Virtuoso 平台对电路进行前仿真,比较器工作电压为3.3V,共模输入电压1.6V,在500MHZ 的时钟频率下,能够实现精度为30uV的比较,功耗为5.6mW,传输时延为4ns,翻转电压0.4mV。
关键词:比较器,预放大锁存,高速低功耗AbstractComparator is one of the most important units widely used in electronic systems. The design of a comparator is based on loop gain amplifier. Compared with amplifiers, comparators are not that widely used, but it is really necessary especially in Analog-to-digital converters (ADC). The comparator is a crucial part of ADC. Its speed and power have great impact on the characteristic of the whole ADC.Being one of various architectures, preamplifier-latch is widely used as high-speed comparator due to its high-speed, low-power and small offset voltage. Based on preamplifier-latch comparator, adopted TSMC 0.13μm CMOS process, a high-speed, low-power comparator applied for pipelined-ADC is proposed in this paper. This comparator consists of three blocks:pre-amplifier, comparator and SR latch. The pre-simulations use Virtuoso simulation of Cadence, the comparator’s work voltage is 1.8V, and common input voltage is 1.6V, the simulation results indicate that the resolution of the comparator is 30uV, transmission delay is less than 4ns and power dissipation is about 5.6mW under the 500MHZ clock.Key W ords: Comparator, Preamplifier-latch, High-speed low-power目录摘要 (I)Abstract (II)第一章绪论 (1)1.1 背景 (1)1.2 本文的研究内容和结构安排 (1)第二章比较器电路的基本模型 (2)2.1 比较器电路的系统参数分析 (2)2.1.1 主要性能参数 (3)2.1.2 比较器静态分析 (5)2.1.3 比较器动态特性 (6)2.2 比较器的电路结构与分析模型 (7)2.2.1 开环比较器 (8)2.2.2 离散时间比较器 (9)2.2.3 高速比较器 (13)2.3 几种常见的比较器结构 (15)2.3.1 电阻分配式比较器 (15)2.3.2 差分对比较器 (16)2.3.3电荷分配型比较器 (16)2.4 小结 (17)第三章高速低功耗比较器设计 (18)3.1 前置放大器设计 (18)3.1.1 二极管负载差分放大器 (18)3.1.2 差分放大器的级联 (22)3.2 锁存比较器的结构 (24)3.2.1 两种锁存比较器的结构对比 (24)3.2.2 锁存器优化 (26)3.3 输出缓冲级设计 (28)3.4 比较器整体结构和参数 (30)3.5 小结 (31)第四章比较器电路功能仿真 (32)4.1 比较器的逻辑仿真 (32)4.2 比较器的速度与精度 (33)4.3 比较器的传输延迟 (35)4.4 比较器的翻转电压 (37)4.5 比较器的功耗 (38)4.6 小结 (38)第五章比较器的版图设计和后仿 (40)5.1 比较器的版图设计 (40)5.2 比较器的版图验证 (44)5.3 比较器的后仿真 (45)5.4 小结 (47)第六章总结和心得 (48)致谢 (50)参考文献 (51)第一章绪论1.1 背景从国际和国内发展情况来看,比较器的研究趋势就是高速度、低功耗和高温度等。
高速低功耗双尾比较器的设计
高速低功耗双尾比较器的设计任志德;郭春生【摘要】In order to optimize the speed and power of comparator,a new double tail comparator has been proposed based on an existing one.We increase the speed of the comparator by additional positive feedback path of cross-cou⁃pling. But the number of branches of the power to the ground the number of devices in the circuit are reduced to save power consumption.Simulation results show that the maximum operating frequency can be processed from the original 1.7 GHz to 2.5 GHz. The power consumption can be saved significantly with the increasing operating fre⁃quency.When the operating frequency is at 1.7 GHz,the consumption can save on 41.45%,and power delay product can increase 62.33%. The proposed two-tailed comparator is more suitable for high-speed,low-power analog-to-digi⁃tal conversion circuit.%针对比较器速度和功耗两大指标的优化,对一款新提出的双尾比较器进行了改善和提高。
高速低功耗CMOS动态锁存比较器的设计
高速低功耗CMOS动态锁存比较器的设计李靖坤;杨骁;陈国晏;娄付军;邱伟彬【摘要】A high-speed low-power dynamic latched comparator including a pre-amplifier,a latched compara-tor and a SR-latch is presented.A novel reset circuit that only has one PMOS transistor is adopted for the latched comparator,which can realize the electric charge reusing.As a result,the delay and power consump-tion are reduced.The parasitic capacitance of input transistors of the SR-latch acts as the load capacitance of the latched comparator.An improved method for the SR-latch is adopted to avoid shifting of the input offset voltage caused by the load capacitance mismatch of the latched comparator.The comparator is implemented with TSMC 0.18 μm complementary metal-oxide-semiconductor(CMOS)technology.Simulation results show that a sensitivity of 0.3 mV and a maximum input offset of 8 mV are achieved with the operating frequency of 1 GHz,and the power consumption is 0.2 mW with 1 .8 V supply.The dynamic latched comparator is concise and simple to implement,and has features of low power.%提出一种高速低功耗动态锁存比较器,电路包含预放大器、锁存比较器和SR 锁存器 3 部分.采用一种新的锁存比较器复位电路,该电路仅由一个P沟道金属氧化物半导体(PMOS)管构成,实现电荷的再利用,减小了延迟,降低了功耗.SR锁存器输入端口的寄生电容为锁存比较器的负载电容,对 SR 锁存器的输入端口进行改进,避免由于锁存比较器的负载电容失配导致的输入失调电压偏移的问题.电路采用TSMC 0.18 μm 互补金属氧化物半导体(CMOS)工艺实现.结果表明:电源电压为1 .8 V,时钟频率为1 GHz时,比较器精度达0.3 mV;最大输入失调电压为8 mV,功耗为0.2 mW;该比较器具有电路简单易实现、功耗低的特点.【期刊名称】《华侨大学学报(自然科学版)》【年(卷),期】2018(039)004【总页数】5页(P618-622)【关键词】动态锁存比较器;互补金属氧化物半导体;高速低功耗;失调电压【作者】李靖坤;杨骁;陈国晏;娄付军;邱伟彬【作者单位】华侨大学信息科学与工程学院,福建厦门 361021;厦门市ASIC与系统重点实验室,福建厦门 361008;华侨大学信息科学与工程学院,福建厦门361021;厦门市ASIC与系统重点实验室,福建厦门 361008;华侨大学信息科学与工程学院,福建厦门 361021;厦门市ASIC与系统重点实验室,福建厦门 361008;华侨大学信息科学与工程学院,福建厦门 361021;厦门市ASIC与系统重点实验室,福建厦门 361008;华侨大学信息科学与工程学院,福建厦门 361021;厦门市ASIC与系统重点实验室,福建厦门 361008【正文语种】中文【中图分类】TN432随着现代通信和信号处理技术的广泛应用,高速低功耗的电子设备成为市场的主流.比较器作为模数转换器、数据接收器等系统不可缺少的模块,对其系统的性能指标有着重要的影响[1].常见的比较器有静态锁存比较器[2-3]和动态锁存比较器[4-8].其中,静态锁存比较器无论是在复位阶段还是再生阶段都存在静态电流,速度较慢、功耗较大[3].动态锁存比较器采用一对背靠背交叉耦合的反相器构成正反馈,使小的差分输入信号迅速放大到满摆幅的数字信号输出,具有速度快、功耗低、高输入阻抗、满输出摆幅等优点,在高速电路中得到了广泛地应用[6].然而,传统动态锁存比较器存在失调电压高、回踢噪声大的缺点.在锁存比较器之前,增加一级预放大器可以减小失调电压、回踢噪声的影响.本文在传统动态锁存比较器的基础上,设计一种高速低功耗互补金属氧化物半导体(CMOS)动态锁存比较器.图1 预放大器和锁存比较器电路Fig.1 Pre-amplifier and latched comparator circuit1 比较器电路分析与设计在文献[5]的基础上提出的预放大器和锁存比较器电路,如图1所示.用P沟道金属氧化物半导体(PMOS)管MP5替代原来的复位管MN8,MN9(虚线所示),实现电荷再利用,减小延迟时间并降低功耗.图1中:MN1~MN3及MP1,MP2构成预放大器;MN4~MN7及MP3~MP7构成锁存比较器;MP5为复位管;时钟(CLK)为低电平时,MP5导通,使M,N两点的电压相等,避免M,N两点残余电荷不相等,从而影响比较器的精度.图2 SR锁存器电路Fig.2 SR latch circuitSR锁存器电路,如图2所示.SR锁存器是由两个首尾交叉连接的或非门构成.若采用图2中NOR1的A输入端和NOR2的B输入端作为SR锁存器的输入引脚,则会造成锁存比较器的两个输出节点out+和out-负载电容不同,这会产生比较器失调电压偏移的问题[9].文中采用两个或非门的同一端引脚B作为锁存比较器的负载,且B输入端连接的是或非门中两个不存在体效应的金属氧化物半导体场效应晶体(MOS)管MN1和MP2,从而避免比较器输入失调电压偏移的问题.文中比较器的工作原理如下所述.其中,N沟道金属氧化物半导体(NMOS)管的阈值电压为VTHN;PMOS管的阈值电压为VTHP.1) 复位阶段.CLK为低电平,MOS管MN1截止,MP1,MP2导通,预放大器将节点Di(Di+和Di-)充电至VDD;MP6,MP7截止,MN4,MN7导通,节点out+,out-被下拉至零电位(GND),SR锁存器处于保持状态,比较器的输出保持上一个状态不变;复位管MP5导通,使节点M,N的电压相等,MP3,MN5和MP4,MN6为交叉耦合的反相器,此时均截止.2) 再生阶段.CLK为高电平,MOS管MN1导通,MP1,MP2截止,节点Di-和Di+根据输入信号VIP和VIN的不同,以不同的速率放电.记节点Di放电到VDD-|VTHP|的时间为T1,这段时间,MN2,MN3工作在饱和区.假设比较器的差模输入信号很小,则流过MN2,MN3的电流近似相等,记为ID1,忽略二级效应,有(1)式(1)中:(W/L)1为MN2,MN3的宽长比;VIP,VIN为输入电压信号;VS为MN1导通时节点S的电压.节点Di的电压随时间变化可表示为(2)因此,时间T1为T1=(|VTHP|CDi)/ID1.(3)式(3)中:CDi为节点Di+和Di-的寄生电容,CDi=CDi+=CDi-.当VDi下降到VDD-|VTHP|,MP6,MP7管开始导通并工作在饱和区,忽略二级效应,流过MP6,MP7的电流为(4)式(4)中:(W/L)2为MP6,MP7的宽长比.MP6,MP7以电流ID2分别对节点M,N进行充电.此时,MP3,MP4仍然截止,Vout(Vout+和Vout-)等于GND,MN4,MN7工作在深线性区,电流几乎为0.当VM,VN充电到|VTHP|时,MP3,MP4导通,记VM,VN达到|VTHP|的时间为T2,同理有(5)式(5)中:CM,N为节点M,N的寄生电容,CM,N=CM=CN.MP3,MP4导通后,MN4,MN7工作在线性区,流过MN4和MN7的电流为(6)式(6)中:(W/L)3为MN4,MN7的宽长比.节点out+和out-以电流ID2-ID3充电,记Vout达到VTHN的时间为T3,即T3=VTHNCout/(ID2-ID3).(7)式(7)中:Cout为节点out+和out-的寄生电容,Cout=Cout+=Cout-.Vout达到VTHN后,MN5,MN6开始导通,由MP3,MN5和MP4,MN6构成的锁存器开始工作.由于节点Di-和Di+以不同的速率放电,同一时间VDi-和VDi+必然会有一个微小的差值,进而造成Vout+和Vout-产生压差,记为ΔVout,这个压差作为锁存器的初始压差,会被迅速放大到VDD-GND,驱动SR锁存器置0或置1,即比较器的输出.锁存器再生过程需要的时间记为T4[10],则有(8)τ为锁存器的时间常数,即(9)式(9)中:gm为锁存器的跨导.由以上的分析可知,比较器总的延迟时间约为Tdelay=T1+T2+T3+T4.(10)3) 比较器再次复位.CLK跳变为低电平,MN1截止,MP1,MP2导通,节点Di被充电至VDD;MP6,MP7截止,MN4,MN7导通,节点out+和out-通过MN4和MN7放电到GND;节点M,N的电压因为复位管MP5的导通而相等,且分别通过MP3,MN4支路及MP4,MN7支路放电;当节点M,N的电压放电至|VTHP|时,MP3,MP4截止,忽略亚阈值导电特性,M,N的电压最终保持在|VTHP|不变.当比较器再次处于再生状态,由于节点M,N的电压已经为|VTHP|,所以比较器在再生阶段节约了时间T2,且避免再次对节点M,N进行充电.因此,相较于文献[5]将M,N两点的电压放电到0的做法,文中实现了电荷的再利用,减小了比较器的延迟时间.比较器总的延迟时间缩减为Td=T1+T3+T4.(11)比较器每个周期节约电荷量,即Q=C×V=2×CM,N×|VTHP|.(12)2 电路仿真结果对文中提出的比较器和文献[5]的架构进行设计与仿真.两个电路都采用TSMC 0.18μm CMOS工艺实现,复位管MP5采用的尺寸和文献[5]中复位管MN8,MN9采用的尺寸均为600 nm/180 nm,其他晶体管一一对应.仿真条件:电源电压VDD为1.8 V;时钟频率CLK为1 GHz;温度为27 ℃;工艺角为TT;比较器输入共模电压VCM为0.9 V,输出电容负载为5 fF.比较器的延迟时间(t)和功耗与输入电压的关系(VDD=1.8 V,VCM=0.9 V),如图3所示.以输入电压ΔVIN=50 mV为例,文献[5]架构比较器的延迟时间为282.85 ps,文中比较器的延时为246.13 ps,改进后的比较器延迟时间减小了36.72 ps,速度提升约13%;文献[5]架构比较器的平均动态功耗为198.8 μW·GHz-1,文中为175.6 μW·GHz-1,平均动态功耗降低了11.7%(此处不包含SR锁存器的功耗).比较器延迟时间和功耗与电源电压的关系(ΔVIN= 50 mV,VCM= VDD -0.4 V),结果如图4所示.(a) 延迟时间与输入电压 (b) 功耗与输入电压图3 比较器延迟时间和功耗与输入电压的关系(VDD=1.8 V,VCM=0.9 V)Fig.3 Comparators′ delay and power consumption versus input voltage (VDD=1.8 V,VCM=0.9 V)(a) 延迟时间与电源电压 (b) 功耗与电源电压图4 比较器延迟时间和功耗与电源电压的关系(ΔVIN= 50 mV,VCM= VDD -0.4 V)Fig.4 Comparators′ delay and power consumption versus supply voltage (ΔVIN= 50 mV,VCM= VDD -0.4 V)图5 文中比较器最坏情况仿真波形Fig.5 Simulation waveform of proposed comparator in worst case在较低的电源电压下,文中比较器的延时相较于文献[5]架构的比较器最多减小了18.7%;随着电源电压的升高,文中比较器的低功耗优势逐渐增大.在不同温度(-40~125 ℃)和工艺角(FF,TT,SS,FS,SF)下对文中的比较器进行仿真.仿真结果表明:温度为125 ℃,工艺角为SS时,出现最坏情况.此时的瞬态仿真波形,如图5所示.由图5可知:比较器可分辨的最小电压为0.3 mV,延迟时间为729.595 ps.对整个比较器进行100次Monte carlo分析仿真,SR锁存器的输入引脚改进前后输入失调电压(Voffset)的仿真结果,如图6所示.图6中:Vmu为平均值;Vsd 为标准偏差;N为仿真次数;η为概率.由图6可知:SR锁存器的输入引脚改进前,比较器的输入失调电压呈现整体偏移的情况,最大达到14 mV;SR锁存器的输入引脚改进后,失调电压平均值为0.65 mV,标准偏差为3.96 mV,失调电压集中分布在-8~8 mV.(a) SR锁存器改进前 (b) SR锁存器改进后图6 比较器失调电压分布Fig.6 Distribution of comparator′s offset voltage文中比较器与部分文献比较器的性能指标对比,如表1所示.由表1可知:文中比较器在功耗、失调电压等方面有一定优势,适合于高速低功耗的应用.表1 比较器性能指标对比Tab.1 Performance index comparisons of comparators指标特征尺寸/μmVDD/V平均动态功耗/μW·GHz-1Voffset/mV文献[3]0.181.224 600.0 12.5文献[4]0.181.8610.012.0文献[7]0.181.8250.010.0文中0.181.8200.08.03 结束语提出一种高速低功耗动态锁存比较器.锁存比较器的复位电路仅由一个PMOS管组成,实现了电荷的再利用,减小了延迟,降低了功耗.对SR锁存器的输入端口改进后,避免了比较器输入失调电压偏移的问题.电路采用TSMC 0.18 μm CMOS工艺实现,在电源电压1.8 V,时钟频率1 GHz的条件下,比较器精度为0.3 mV,最大输入失调电压为8 mV,功耗为0.2 mW,适合于高速低功耗应用中.参考文献:【相关文献】[1] SCHINKEL D,MENSINK E,KLUMPERINK E A M,et al.A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects[J].Journal of Solid-State Circuits,2006,41(1):297-306.[2] SHEIKHAEI S,MIRABBASI S,IVANOV A.A 0.35 μm CMOS comparator circuit for high-speed ADC applications[C]∥International Symposium on Circuits and Systems.Kobe:IEEE Press,2005:6134-6137.[3] FAHMY G A,POKHAREL R K,KANAYA H,et al.A 1.2 V 246 μW CMOS latched comparator with neutralization technique for reducing kickback noise[C]∥IEEE Region 10 Conference.Fukuoka:IEEE Press,2010:1162-1165.DOI:10.1109/TENCON.2010.5686392. [4] 吴笑峰,刘红侠,石立春,等.新型高速低功耗CMOS动态比较器的特性分析[J].中南大学学报(自然科学版),2009,40(5):1354-1359.[5] MIYAHARA M,ASADA Y,PAIK D,et al.A low-noise self-calibrating dynamic comparator for high-speed ADCs[C]∥Asian Solid-State Circuits Conference.Fukuoka:IEEEPress,2008:269-272.[6] JEON H J,KIM Y B.A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator[J].Analog Integrated Circuits and Signal Processing,2012,70(3):337-346.DOI:10.1007/s10470-011-9687-5.[7] WONG K L J,YANG C K K.Offset compensation in comparators with minimum input-referred supply noise[J].Journal of Solid-State Circuits,2004,37(5):837-840.DOI:10.1109/JSSC.2004.826317.[8] SCHINKEL D,MENSINK E,KLUMPERINK E,et al.A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time[C]∥International S olid-State Circuits Conference.California:IEEE Press,2007:314-605.[9] NIKOOZADEH A,MURMANN B.An analysis of latch comparator offset due to load capacitor mismatch[J].Transactions on Circuits and Systems Ⅱ: ExpressBriefs,2006,53(12):1398-1402.[10] RAZAVI B,WOOLEY B A.Design techniques for high-speed, high-resolution comparators[J].Journal of Solid-State Circuits,1993,27(12):1916-1926.DOI:10.1109/4.173122.。
SmartFusion2_Brief_v15
• High-Performance DSP Signal Processing
– Up to 240 Fast Mathblocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit Accumulator
SmartFusion2 Family
Reliability
• Single Event Upset (SEU) Immune – Zero FIT FPGA Configuration Cells
• Junction Temperature: 125°C – Military Temperature, 100°C – Industrial Temperature, 85°C – Commercial Temperature
Integrated Analog PLLs
– Output Clock with 8 Output Phases and 45° Phase Difference (Multiply/Divide, and Delay Capabilities)
– Frequency: Input 1 MHz to 200 MHz, Output 20 MHz to 400 MHz
On, Retains Configuration When Powered Off
Security
• Design Security Features (Available on all Devices)
XC2C32A-6QFG32I中文资料
© 2004-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.Features•Optimized for 1.8V systems-As fast as 3.8ns pin-to-pin logic delays -As low as 12 μA quiescent current •Industry’s best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis -Multi-voltage I/O operation: 1.5V through 3.3V •Available in multiple package options -32-land QFN with 21 user I/O -44-pin PLCC with 33 user I/O -44-pin VQFP with 33 user I/O -56-ball CP BGA with 33 user I/O -Pb-free available for all packages •Advanced system features-Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface -IEEE1149.1 JTAG Boundary Scan Test -Optional Schmitt-trigger input (per pin)-Two separate I/O banks-RealDigital 100% CMOS product term generation -Flexible clocking modes-Optional DualEDGE triggered registers -Global signal options with macrocell control·Multiple global clocks with phase selection permacrocell ·Multiple global output enables ·Global set/reset-Efficient control term clocks, output enables andset/resets for each macrocell and shared across function blocks-Advanced design security-Open-drain output option for Wired-OR and LEDdrive-Optional configurable grounds on unused I/Os -Optional bus-hold, 3-state or weak pullup onselected I/O pins-Mixed I/O voltages compatible with 1.5V, 1.8V,2.5V, and3.3V logic levels -PLA architecture·Superior pinout retention ·100% product term routability across functionblock-Hot pluggableRefer to the CoolRunner™-II family data sheet for architec-ture description.DescriptionThe CoolRunner ™-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli-ability is improvedThis device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configura-tion bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up,open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to stor-ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.Clocking is available on a global or Function Block basis.Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.A global set/reset control line is also available to asynchro-nously set or reset selected registers during operation.Additional local clock, synchronous clock-enable, asynchro-nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.The CoolRunner-II 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O com-patible with the use of Schmitt-trigger inputs.Another feature that eases voltage translation is I/O bank-ing. Two I/O banks are available on the CoolRunner-II 32A macrocell device that permit easy interfacing to 3.3V, 2.5V,1.8V, and 1.5V devices.XC2C32A CoolRunner-II CPLDDS310 (v2.0) March 8, 2007Product Specification2DS310 (v2.0) March 8, 2007RealDigital Design TechnologyXilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology.RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.Supported I/O StandardsThe CoolRunner-II 32 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O stan-dard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. TheLVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs.Table 1: I/O Standards for XC2C32A IOSTANDARD Attribute Output V CCIO Input V CCIO Input V REF BoardTermination Voltage V T LVTTL 3.3 3.3N/A N/A LVCMOS33 3.3 3.3N/A N/A LVCMOS25 2.5 2.5N/A N/A LVCMOS18 1.8 1.8N/A N/A LVCMOS15(1)1.51.5N/AN/A(1) LVCMOS15 requires Schmitt-trigger inputs.Figure 1: I CC vs FrequencyTable 2: I CC vs Frequency (LVCMOS 1.8V T A = 25°C)(1)Frequency (MHz)255075100150175200225250300Typical I CC (mA)0.0160.871.752.613.445.165.996.817.638.369.93Notes:1.16-bit up/down, resettable binary counter (one counter per function block).Recommended Operating ConditionsDC Electrical Characteristics (Over Recommended Operating Conditions)Absolute Maximum RatingsSymbol DescriptionValue Units V CC Supply voltage relative to ground –0.5 to 2.0V V CCIO Supply voltage for output drivers –0.5 to 4.0V V JTAG (2)JTAG input voltage limits –0.5 to 4.0V V CCAUX JTAG input supply voltage –0.5 to 4.0V V IN (1)Input voltage relative to ground –0.5 to 4.0V V TS (1)Voltage applied to 3-state output –0.5 to 4.0V T STG (3)Storage Temperature (ambient)–65 to +150°C T JJunction Temperature+150°CNotes:1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA.2.Valid over commercial temperature range.3.For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb freepackages, see XAPP427.Symbol ParameterMin Max Units V CC Supply voltage for internal logic and input buffersCommercial T A = 0°C to +70°C 1.7 1.9V Industrial T A = –40°C to +85°C1.7 1.9V V CCIOSupply voltage for output drivers @ 3.3V operation 3.0 3.6V Supply voltage for output drivers @ 2.5V operation 2.3 2.7V Supply voltage for output drivers @ 1.8V operation 1.7 1.9V Supply voltage for output drivers @ 1.5V operation1.4 1.6V V CCAUXJTAG programming pins1.73.6VSymbol ParameterTest ConditionsTypical Max.Units I CCSB Standby current Commercial V CC = 1.9V, V CCIO = 3.6V 2290μA I CCSB Standby current Industrial V CC = 1.9V, V CCIO = 3.6V38150μA I CC (1)Dynamic current f = 1 MHz -0.25mA f = 50 MHz - 2.5mA C JTAG JTAG input capacitance f = 1 MHz -10pF C CLK Global clock input capacitance f = 1 MHz -12pF C IO I/O capacitance f = 1 MHz-10pF I IL (2)Input leakage current V IN = 0V or V CCIO to 3.9V -+/-1μA I IH (2)I/O High-Z leakageV IN = 0V or V CCIO to 3.9V-+/-1μANotes:1.16-bit up/down resettable binary counter (one per Function Block) tested at V CC = V CCIO = 1.9V.2.See Quality and Reliability section of the CoolRunner-II family data sheet.LVCMOS 3.3V and LVTTL 3.3V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.UnitsV CCIO Input source voltage 3.0 3.6VV IH High level input voltage2 3.9VV IL Low level input voltage–0.30.8VV OH High level output voltage I OH = –8 mA, V CCIO = 3V V CCIO – 0.4V-VI OH = –0.1 mA, V CCIO = 3V V CCIO – 0.2V-VV OL Low level output voltage I OL = 8 mA, V CCIO = 3V-0.4VI OL = 0.1 mA, V CCIO = 3V-0.2VLVCMOS 2.5V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.UnitsV CCIO Input source voltage 2.3 2.7VV IH High level input voltage 1.7V CCIO + 0.3(1)VV IL Low level input voltage–0.30.7VV OH High level output voltage I OH = –8 mA, V CCIO = 2.3V V CCIO – 0.4V-VI OH = –0.1 mA, V CCIO = 2.3V V CCIO – 0.2V-VV OL Low level output voltage I OL = 8 mA, V CCIO = 2.3V-0.4VI OL = 0.1mA, V CCIO = 2.3V-0.2V(1) The V IH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.LVCMOS 1.8V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.Units V CCIO Input source voltage 1.7 1.9VV IH High level input voltage0.65 x V CCIO V CCIO + 0.3(1)VV IL Low level input voltage–0.30.35 x V CCIO VV OH High level output voltage I OH = –8 mA, V CCIO = 1.7V V CCIO – 0.45-VI OH = –0.1 mA, V CCIO = 1.7V V CCIO – 0.2-VV OL Low level output voltage I OL = 8 mA, V CCIO = 1.7V-0.45VI OL = 0.1 mA, V CCIO = 1.7V-0.2V(1) The V IH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.LVCMOS1.5V DC Voltage Specifications(1)Symbol Parameter Test Conditions Min.Max.Units V CCIO Input source voltage 1.4 1.6VV T+Input hysteresis threshold voltage0.5 x V CCIO0.8 x V CCIO VV T-0.2 x V CCIO0.5 x V CCIO VV OH High level output voltage I OH = –8 mA, V CCIO = 1.4V V CCIO – 0.45-VI OH = –0.1 mA, V CCIO = 1.4V V CCIO – 0.2-V4DS310 (v2.0) March 8, 2007Schmitt Trigger Input DC Voltage SpecificationsAC Electrical Characteristics Over Recommended Operating ConditionsV OLLow level output voltageI OL = 8 mA, V CCIO = 1.4V -0.4V I OL = 0.1 mA, V CCIO = 1.4V-0.2VNotes:1.Hysteresis used on 1.5V inputs.Symbol ParameterTest ConditionsMin.Max.Units V CCIO Input source voltage1.4 3.9V V T+Input hysteresis threshold voltage0.5 x V CCIO 0.8 x V CCIO V V T-0.2 x V CCIO0.5 x V CCIOVSymbol Parameter-4-6Units Min.Max.Min.Max.T PD1Propagation delay single p-term - 3.8- 5.5ns T PD2Propagation delay OR array - 4.0- 6.0ns T SUD Direct input register clock setup time 1.7- 2.2-ns T SU1Setup time fast (single p-term) 1.9- 2.6-ns T SU2Setup time (OR array) 2.1- 3.1-ns T HD Direct input register hold time 0.0-0.0-ns T H P-term hold time 0.0-0.0-ns T CO Clock to output - 3.7- 4.7ns F TOGGLE (1)Internal toggle rate-500-300MHz F SYSTEM1(2)Maximum system frequency -323-200MHz F SYSTEM2(2)Maximum system frequency -303-182MHz F EXT1(3)Maximum external frequency -179-137MHz F EXT2(3)Maximum external frequency-172-128MHz T PSUD Direct input register p-term clock setup time 0.4-0.9-ns T PSU1P-term clock setup time (single p-term)0.6- 1.3-ns T PSU2P-term clock setup time (OR array)0.8- 1.8-ns T PHD Direct input register p-term clock hold time 1.5- 1.6-ns T PH P-term clock hold 1.3- 1.2-ns T PCO P-term clock to output- 5.0- 6.0ns T OE /T OD Global OE to output enable/disable - 4.7- 5.5ns T POE /T POD P-term OE to output enable/disable- 6.2- 6.7ns T MOE /T MOD Macrocell driven OE to output enable/disable - 6.2- 6.9ns T PAO P-term set/reset to output valid - 5.5- 6.8ns T AO Global set/reset to output valid - 4.5- 5.5ns T SUEC Register clock enable setup time 2.0- 3.0-ns T HEC Register clock enable hold time 0.0-0.0-ns T CW Global clock pulse width High or Low 1.4- 2.2-ns T PCWP-term pulse width High or Low4.0- 6.0-nsSymbol ParameterTest ConditionsMin.Max.Units6DS310 (v2.0) March 8, 2007T APRPW Asynchronous preset/reset pulse width (High or Low)4.0- 6.0-ns T CONFIG (4)Configuration time-50-50μsNotes:1.F TOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).2.F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term permacrocell while F SYSTEM2 is through the OR array .3.F EXT1 (1/T SU1+T CO ) is the maximum external frequency using one p-term while F EXT2 is through the OR array .4.Typical configuration current during T CONFIG is 500 μA.Symbol Parameter-4-6Units Min.Max.Min.Max.Internal Timing ParametersSymbol Parameter(1)-4-6Units Min.Max.Min.Max.Buffer DelaysT IN Input buffer delay- 1.3- 1.7ns T DIN Direct register input delay- 1.5- 2.4ns T GCK Global Clock buffer delay- 1.3- 2.0ns T GSR Global set/reset buffer delay- 1.6- 2.0ns T GTS Global 3-state buffer delay- 1.1- 2.1ns T OUT Output buffer delay- 1.8- 2.0ns T EN Output buffer enable/disable delay- 2.9- 3.4ns P-term DelaysT CT Control term delay- 1.3- 1.6ns T LOGI1Single p-term delay adder-0.4- 1.1ns T LOGI2Multiple p-term delay adder-0.2-0.5ns Macrocell DelayT PDI Input to output valid-0.3-0.7ns T LDI Setup before clock (transparent latch)- 1.5- 2.5ns T SUI Setup before clock 1.5- 1.8-ns T HI Hold after clock0.0-0.0-ns T ECSU Enable clock setup time 0.7- 1.7-ns T ECHO Enable clock hold time 0.0-0.0-ns T COI Clock to output valid-0.6-0.7ns T AOI Set/reset to output valid- 1.1- 1.5ns Feedback DelaysT F Feedback delay-0.6- 1.4ns T OEM Macrocell to global OE delay-0.7-0.8ns I/O Standard Time Adder Delays 1.5V CMOST HYS15Hysteresis input adder- 3.0- 4.0ns T OUT15Output adder-0.8- 1.0ns T SLEW15Output slew rate adder- 4.0- 5.0ns I/O Standard Time Adder Delays 1.8V CMOST HYS18Hysteresis input adder- 3.0- 4.0ns T OUT18Output adder-0.0-0.0ns T SLEW Output slew rate adder- 4.0- 5.0ns8DS310 (v2.0) March 8, 2007Switching CharacteristicsAC Test CircuitI/O Standard Time Adder Delays 2.5V CMOS T IN25Standard input adder -0.5-0.6ns T HYS25Hysteresis input adder - 3.0- 4.0ns T OUT25Output adder-0.6-0.7ns T SLEW25Output slew rate adder- 4.0- 5.0ns I/O Standard Time Adder Delays 3.3V CMOS/TTL T IN33Standard input adder -0.5-0.6ns T HYS33Hysteresis input adder - 3.0- 4.0ns T OUT33Output adder- 1.0- 1.2ns T SLEW33Output slew rate adder- 4.0- 5.0nsNotes:1. 1.5 ns input pin signal rise/fall.Internal Timing Parameters (Continued)Symbol Parameter (1)-4-6Units Min.Max.Min.Max.Figure 2: Derating Curve for T PDFigure 3: AC Load CircuitTypical I/O Output CurvesFigure 4: Typical I/V Curve for XC2C32APin DescriptionsFunction Block Macrocell QFG32PC44VQ44CP56I/O Bank 114438F1Bank 2124337E3Bank 2134236E1Bank 2 1(GTS1)434034D1Bank21(GTS0)523933C1Bank21(GTS3)613832A3Bank 21(GTS2)7323731A2Bank 21(GSR)8313630B1Bank 221 9303529A1Bank21 10293428C4Bank111283327C5Bank2112242923C8Bank21132822A10Bank2114232721B10Bank21152620C10Bank21162519E8Bank2215139G1Bank 122240F3Bank123341H1Bank124442G3Bank1 2(GCK0)56543J1Bank 12(GCK1)67644K1Bank 12(GCK2)7871K2Bank 110DS310 (v2.0) March 8, 2007XC2C32A Global, JTAG, Power/Ground and No Connect Pins28982K3Bank1291093H3Bank1210115K5Bank 1211126H5Bank 121213148H8Bank 1213171812K8Bank1214181913H10Bank1215192014G10Bank 12162216F10Bank1Notes:1.GTS = global output enable, GSR = global set reset, GCK = global clock2.GTS, GSR, and GCK pins can also be used for general purpose I/O.Pin TypeQFG32PC44(1)VQ44(1)CP56(1)TCK 161711K10TDI 14159J10TDO 253024A6TMS 151610K9Input Only22 (bank 2)24 (bank 2)18 (bank 2)D10 (bank 2)V CCAUX (JTAG supply voltage)44135D3Power internal (V CC )Power bank 1 I/O (V CCIO1)Power bank 2 I/O (V CCIO2)202115G812137H6273226C6Ground 11, 21, 2610,23,314,17,25H4, F8, C7No connects--K4, K6, K7, H7, E10, A7, A9, D8, A5, A8,A4, C3Total user I/O (includes dual function pins)21333333Notes:1.All packages pin compatible with larger macrocell densitiesPin Descriptions (Continued)Function BlockMacrocellQFG32PC44VQ44CP56I/O BankOrdering InformationPart Number Pin/BallSpacingθJA(C/Watt)θJC(C/Watt)Package TypePackage BodyDimensions I/OComm.(C)Ind. (I)(1)XC2C32A-4QFG32C0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21CXC2C32A-6QFG32C0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21CXC2C32A-4PC44C 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33CXC2C32A-6PC44C 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33CXC2C32A-4VQ44C0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33CXC2C32A-6VQ44C0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33C XC2C32A-4CP56C0.5mm66.014.9Chip Scale Package6mm x 6mm33C XC2C32A-6CP56C0.5mm66.014.9Chip Scale Package6mm x 6mm33C XC2C32A-4PCG44C 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33CXC2C32A-6PCG44C 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33CXC2C32A-4VQG44C0.8mm47.78.2Very Thin Quad FlatPack; Pb-free10mm x 10mm33CXC2C32A-6VQG44C0.8mm47.78.2Very Thin Quad FlatPack; Pb-free10mm x 10mm33CXC2C32A-4CPG56C0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33CXC2C32A-6CPG56C0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33CXC2C32A-6QFG32I0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21IXC2C32A-6PC44I 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33IXC2C32A-6VQ44I0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33I XC2C32A-6CP56I0.5mm66.014.9Chip Scale Package6mm x 6mm33I XC2C32A-6PCG44I 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33I12DS310 (v2.0) March 8, 2007Device Part MarkingFigure 5: Sample Package with Part MarkingNote: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale and quad flat no lead packages by line are:•Line 1 = X (Xilinx logo) then truncated part number •Line 2 = Not related to device part number •Line 3 = Not related to device part number•Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C3 = CP56, C4 = CPG56, Q1 = QFG32.XC2C32A-6VQG44I 0.8mm 47.78.2Very Thin Quad Flat Pack; Pb-free 10mm x 10mm 33I XC2C32A-6CPG56I0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33INotes:1. C = Commercial (T= 0°C to +70°C); I = Industrial (T = –40°C to +85°C)Part Number Pin/Ball Spacing θJA (C/Watt)θJC (C/Watt)Package Type Package Body Dimensions I/O Comm. (C)Ind. (I)(1)Figure 6: QFG32 PackageFigure 7: VQ44 PackageFigure 8: PC44 PackageFigure 9: CP56 PackageWarranty DisclaimerTHESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT /warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.14DS310 (v2.0) March 8, 2007Additional InformationAdditional information is available for the following CoolRunner-II topics:•XAPP784: Bulletproof CPLD Design Practices •XAPP375: Timing Model•XAPP376: Logic Engine•XAPP378: Advanced Features•XAPP382: I/O Characteristics•XAPP389: Powering CoolRunner-II•XAPP399: Assigning VREF Pins To access these and all application notes with their associ-ated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device PackagesRevision HistoryThe following table shows the revision history for this document.Date Version Revision6/15/04 1.0Initial Xilinx release.8/30/04 1.1Pb-free documentation10/01/04 1.2Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.11/08/04 1.3Product Release. No changes to documentation.11/22/04 1.4Changes to output enable/disable specifications; changes to I CCSB.02/17/05 1.5Changes to f TOGGLE, t SLEW25, and t SLEW3303/07/05 1.6Improvement of pin-to-pin logic delay, page 1. Modifications to Table 1, IOSTANDARDs.06/28/05 1.7Move to Product Specification. Change to T IN25, T OUT25, T IN33, and T OUT33.03/20/06 1.8Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can alsobe used for general purpose I/O.02/15/07 1.9Change to V IH specification for 2.5V and 1.8V LVCMOS. Change to T OEM for -4 speedgrade.03/08/07 2.0Fixed typo in note for V IL for LVCMOS18; removed note for V IL for LVCMOS33.16DS310 (v2.0) March 8, 2007。
10bit500MS_sPipeline-SARADC的设计
摘要模数转换器(ADC)作为现代通信系统中的关键电路,其性能直接决定了通信系统的整体性能。
在需要中等精度高速ADC的应用场合,如无线网802.11ac通信协议等,流水线逐次逼近型模数转换器(Pipeline-SAR ADC)以其兼顾高速和低功耗的结构特点、对先进工艺兼容良好等优良特性被广泛使用。
针对现代高速通信系统的应用场合,论文设计了一款10bit 500MS/s的Pipeline-SAR ADC,其系统架构为两级结构,两级SAR ADC都实现6bit的数据量化,级间放大器提供4倍增益,设置2bit 级间冗余。
在第一级SAR ADC中,提出了一种基于自关断比较器的非环路(Loop-unrolled)结构,在每位比较完成后,通过自关断信号将当前位比较器关断,在不影响比较器锁存级保持数据的前提下,极大减小了Loop-unrolled结构的功耗;同时,针对Loop-unrolled结构多个比较器之间的失调失配,采用了一种基于参考比较器的后台失调校准方法,参考比较器的引入使得该校准方法可以在不增加额外校准时间的前提下完成后台校准,保证了系统的高速特性。
级间放大器采用了一种增益稳定的动态放大器,通过将动态放大器的增益构造为同种参数比例乘积的形式,实现增益稳定,并对其工作时序进行了优化,避免了额外时钟相的引入。
第二级SAR ADC采用了两路交替比较器结构,同时对两个比较器采用了前台失调校准,以避免引入额外的校准时间。
由于级间放大器仅提供4倍增益,第二级的量化范围较小,本文在第二级电容阵列的设计上使用了非二进制冗余,以减小DAC建立误差造成的影响。
本文还设计了数字码整合电路、全局时钟产生电路,以保证整个Pipeline-SAR ADC设计的完整性。
本文基于TSMC 40nm CMOS工艺设计了具体的电路与版图。
后仿真结果表明,在1.1V电源电压下,采样率为500MS/s时,输入近奈奎斯特频率的信号,在tt工艺角下,有效位数(ENOB)达到9.2位,无杂散动态范围(SFDR)达到64.5dB,功耗为7.52mW,FoM值为25.76fJ/conv.step,达到设计指标要求。
第7章 CMOS比较器
refV ⎪⎩⎪⎨⎧<>=in in V V ,0 ,1预放大判决驱动One stage buffer Two or more stage buffers The polarity of comparator is changed when one more INV used.wujinCross pair: M5/M8, Positive Feedback induced in DP load;Mainly to boost gain and small signal Speed.Fully symmetric & Differential OTA,N/P complimentary DPwujin-i gIf W/L of CP (M21,M23) large than that of MOS diode (M20,M22), Hysteric comparator is formed.wujinTo shift or switch reference based on comparator statutefor positive scanning, V applied first, when V+, switch to V for negative scanning, V applied first, when V, switch to VReference switch methodsexternal feedback control, analog mode & digital mode;internal feedback control, positive FB to introduce unsymmetrical.14wujin+V refNMOS switchPMOS switchBetterOutput as digital controlin configuring actual V refV DD /V ref ?; *i SPH V V +=+Modified CMOSHysterics comp should be firstly scaled down VDDwujin26302×=26302×==V B when V CC in to make I 2CC , V in and thus V A low, V B , V o , keep in CC , V A high, V , toggle.V A ?23wujinϕFor output upper level limitRecharge: initial staterecharge & evaluation mode.in +1ref −ΔωΔϕUnsymmetrical of each stage, C1/C2 charging-discharging carrier out alternately [separated by (N-1)/2=3 stage for each other], for setting frequency & duty cycle , VN-CS?RS Latch needed to hole the statue33wujinINV3ClkClkBis under constant current, a small35。
ST 74LCX74 数据手册
July 2006Rev 81/1774LCX74Low voltage CMOS dual D-Type Flip Flopwith 5V tolerant inputsFeatures■5V tolerant inputs■High speed:–f MAX = 150MHz (Max) at V CC = 3V ■Power down protection on inputs and outputs ■Symmetrical output impedance:–|I OH | = I OL = 24mA (Min) at V CC = 3V ■PCI bus levels guaranteed at 24mA ■Balanced propagation delays:–t PLH ≅ t PHL■Operating voltage range:–V CC (Opr) = 2.0V to 3.6V ■Pin and function compatible with 74 series 74■Latch-up performance exceeds 500mA (JESD 17)■ESD performance: –HBM > 2000V(MIL STD 883 method 3015); MM > 200VDescriptionThe 74LCX74 is a low voltage CMOS dual D-type flip flop with preset and clear non inverting fabricated with sub-micron silicon gate anddouble-layer metal wiring C 2MOS technology. It is ideal for low power and high speed 3.3Vapplications; it can be interfaced to 5V signal environment for inputs.A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse.CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input.It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs and outputs are equipped withprotection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.Order codesPart number Package Packaging 74LCX74MTR SO-14T ape and reel 74LCX74TTRTSSOP14T ape and reelContents74LCX74Contents1Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 31.1Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.1Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162/1774LCX74Logic symbols and I/O equivalent circuit3/171 Logic symbols and I/O equivalent circuit1.1 Logic diagramNote:This logic diagram has not to be used to estimate propagation delaysPin settings 74LCX744/172 Pin settings2.1 Pin connection2.2 Pin description2.3 Truth tableTable 1. Pin descriptionPin N°Symbol Name and function1, 131CLR, 2CLR Asynchronous reset - direct input2, 121D, 2D Data inputs3, 111CK, 2CK Clock input (LOW to HIGH, Edge Triggered)4, 101PR, 2PR Asynchronous set - direct input 5, 91Q, 2Q True Flip-Flop outputs 6, 81Q, 2Q Complement Flip-Flop outputs 7GND Ground (0V)14V CCPositive supply voltage1.X do not care74LCX74Maximum rating5/173 Maximum ratingstressing the device above the rating listed in the “absolute maximum ratings” table maycause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the STMicroelectronics sure program and other relevant quality documents.3.1 Recommended operating conditionsTable 3. Absolute maximum ratingsSymbol ParameterValue Unit V CC Supply voltage -0.5 to +7.0V V I DC input voltage-0.5 to +7.0V V O DC output voltage (V CC = 0V)-0.5 to +7.0V V O DC output voltage (high or low state) (1)1.I O absolute maximum rating must be observed -0.5 to V CC + 0.5V I IK DC input diode current -50mA I OK DC output diode current (2)2.V O < GND-50mA I O DC output current± 50mA I CC DC supply current per supply pin ± 100mA I GND DC ground current per supply pin ± 100mA T stg Storage temperature -65 to +150°C T LLead temperature (10 sec)300°CTable 4. Recommended operating conditionsSymbol ParameterValue Unit V CC Supply voltage (1)1.Truth table guaranteed: 1.5V to 3.6V 2.0 to 3.6V V I Input voltage0 to 5.5V V O Output voltage (V CC = 0V)0 to 5.5V V O Output voltage (high or low state)0 to V CC V I OH , I OL High or low level output current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or low level output current (V CC = 2.7V)± 12mA T op Operating temperature -40 to 85°C dt/dvInput Rise and Fall Time (2)2.V IN from 0.8V to 2V at V CC =3.0V0 to 10ns/V6/174 Electrical characteristicsTable 5. DC specificationsSymbolParameterTest conditionValue UnitV CC (V)-40 to 85°C Min MaxV IH High level input voltage 2.7 to 3.62.0V V ILLow level input voltage0.8VV OHHigh level output voltage2.7 to3.6I O =-100 µA V CC -0.2V 2.7I O =-12 mA 2.23.0I O =-18 mA 2.4I O =-24 mA 2.2V OLLow level output voltage2.7 to3.6I O =100 µA 0.2V 2.7I O =12 mA 0.43.0I O =16 mA 0.4I O =24 mA 0.55I I Input leakage current 2.7 to 3.6V I = 0 to 5.5V ± 5µA I off Power OFF leakage currentV I or V O = 5.5V 10µA I CC Quiescent supply current 2.7 to 3.6V I = V CC or GND 10µA V I or V O = 3.6 to 5.5V ± 10∆I CCI incr. per Input2.7 to3.6V IH = V CC - 0.6V500µA Table 6. Dynamic switching characteristicsSymbolParameterTest conditionValue UnitV CC (V)T A = 25 °C MinTyp MaxV OLP Dynamic low level quiet output (1)1.Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW toHIGH. The remaining output is measured in the LOW state.3.3C L = 50pFV IL = 0V , V IH = 3.3V0.8V V OLV-0.87/17Table 7. AC electrical characteristicsSymbolParameterTest conditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C Min Max t PLH t PHL Propagation delaytime (CK to Q orQ) 2.7505002.51.58.0ns 3.0 to 3.6 1.57.0t PLH t PHL Propagation delaytime (PR or CLRto Q or Q)2.750500 2.51.58.0ns 3.0 to 3.6 1.57.0t SSetup time, HIGHor LOW level D to CK2.750500 2.52.5ns3.0 to 3.6 2.5t hHold time, HIGH or LOW level D to CK2.750500 2.51.5ns3.0 to 3.6 1.5t WCK Pulse width, HIGH or LOW PR or CLR Pulse Width, LOW2.750500 2.53.0ns3.0 to 3.63.0t rec Recovery time PRor CLR to CK 2.750500 2.50ns 3.0 to 3.60f MAX Clock pulse frequency 2.750500 2.5150MHz t OSLH t OSHLOutput to output skew time (1) (2)1.Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |)2.Parameter guaranteed by design3.0 to 3.6505002.51.0nsTable 8. Capacitive characteristicsSymbol ParameterTest conditionValue UnitV CC (V)T A = 25 °CMinTyp MaxC IN Input capacitance 3.3V IN = 0 to V CC 6pF C PDPower dissipation capacitance (1)1.C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from theoperating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /2 (per gate)3.3f IN = 10MHz V IN = 0 or V CC40pFTest circuit 74LCX748/175 Test circuitC L = 50pF or equivalent (includes jig and probe capacitance)R L = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)6 Waveforms74LCX74Waveforms9/17Waveforms74LCX7410/177 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in ECOPACK®packages. These packages have a Lead-free second level interconnect . The category ofsecond level interconnect is marked on the package and on the inner box label, incompliance with JEDEC Standard JESD97. The maximum ratings related to solderingconditions are also marked on the inner box label. ECOPACK is an ST trademark.ECOPACK specifications are available at: 11/1712/1713/1714/1715/17Revision history 74LCX7416/178 Revision historyTable 9. Revision historyDate RevisionChanges15-Sep-20047Ordering codes revision - pag. 1.10-Jul-20068New template, temperature ranges updated74LCX74Please Read Carefully:Information in this document is provided solely in connection with ST products. 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Lecture_4 Special emSRAM
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Process variation from Moore’ law scaling by Design-Tricks
– – –
•
Process Innovation with Design-Tricks
– – – – –
(1) Higher Speed : Dual port (read/write from both independent I/O set)
Higher Speed vs Lower Power Cache
affordable cost trade-off for the specific applications • Embedded SRAM on specific CPU die
– PRO • • • • CON • • Very high bandwidth for parallelism No power and silicon area burden by I/O driver No cache-related package pin cost 1 path test’ low cost Need most advanced CMOS Technology nodes Otherwise, 50~80% emSRAM have extremely big System on Chip die size – Very hard to have high SoC chip yield – High price of big SoC chip
Adding Higher Vt (> 0.6V) implant masks (nFET channel Vt and pFET channel Vt) for repeatable (so many) SRAM cells
XC2C32A-6VQG44C中文资料
© 2004-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.Features•Optimized for 1.8V systems-As fast as 3.8ns pin-to-pin logic delays -As low as 12 μA quiescent current •Industry’s best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis -Multi-voltage I/O operation: 1.5V through 3.3V •Available in multiple package options -32-land QFN with 21 user I/O -44-pin PLCC with 33 user I/O -44-pin VQFP with 33 user I/O -56-ball CP BGA with 33 user I/O -Pb-free available for all packages •Advanced system features-Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface -IEEE1149.1 JTAG Boundary Scan Test -Optional Schmitt-trigger input (per pin)-Two separate I/O banks-RealDigital 100% CMOS product term generation -Flexible clocking modes-Optional DualEDGE triggered registers -Global signal options with macrocell control·Multiple global clocks with phase selection permacrocell ·Multiple global output enables ·Global set/reset-Efficient control term clocks, output enables andset/resets for each macrocell and shared across function blocks-Advanced design security-Open-drain output option for Wired-OR and LEDdrive-Optional configurable grounds on unused I/Os -Optional bus-hold, 3-state or weak pullup onselected I/O pins-Mixed I/O voltages compatible with 1.5V, 1.8V,2.5V, and3.3V logic levels -PLA architecture·Superior pinout retention ·100% product term routability across functionblock-Hot pluggableRefer to the CoolRunner™-II family data sheet for architec-ture description.DescriptionThe CoolRunner ™-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli-ability is improvedThis device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configura-tion bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up,open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to stor-ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.Clocking is available on a global or Function Block basis.Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.A global set/reset control line is also available to asynchro-nously set or reset selected registers during operation.Additional local clock, synchronous clock-enable, asynchro-nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.The CoolRunner-II 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O com-patible with the use of Schmitt-trigger inputs.Another feature that eases voltage translation is I/O bank-ing. Two I/O banks are available on the CoolRunner-II 32A macrocell device that permit easy interfacing to 3.3V, 2.5V,1.8V, and 1.5V devices.XC2C32A CoolRunner-II CPLDDS310 (v2.0) March 8, 2007Product Specification2DS310 (v2.0) March 8, 2007RealDigital Design TechnologyXilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology.RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.Supported I/O StandardsThe CoolRunner-II 32 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O stan-dard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. TheLVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs.Table 1: I/O Standards for XC2C32A IOSTANDARD Attribute Output V CCIO Input V CCIO Input V REF BoardTermination Voltage V T LVTTL 3.3 3.3N/A N/A LVCMOS33 3.3 3.3N/A N/A LVCMOS25 2.5 2.5N/A N/A LVCMOS18 1.8 1.8N/A N/A LVCMOS15(1)1.51.5N/AN/A(1) LVCMOS15 requires Schmitt-trigger inputs.Figure 1: I CC vs FrequencyTable 2: I CC vs Frequency (LVCMOS 1.8V T A = 25°C)(1)Frequency (MHz)255075100150175200225250300Typical I CC (mA)0.0160.871.752.613.445.165.996.817.638.369.93Notes:1.16-bit up/down, resettable binary counter (one counter per function block).Recommended Operating ConditionsDC Electrical Characteristics (Over Recommended Operating Conditions)Absolute Maximum RatingsSymbol DescriptionValue Units V CC Supply voltage relative to ground –0.5 to 2.0V V CCIO Supply voltage for output drivers –0.5 to 4.0V V JTAG (2)JTAG input voltage limits –0.5 to 4.0V V CCAUX JTAG input supply voltage –0.5 to 4.0V V IN (1)Input voltage relative to ground –0.5 to 4.0V V TS (1)Voltage applied to 3-state output –0.5 to 4.0V T STG (3)Storage Temperature (ambient)–65 to +150°C T JJunction Temperature+150°CNotes:1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA.2.Valid over commercial temperature range.3.For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb freepackages, see XAPP427.Symbol ParameterMin Max Units V CC Supply voltage for internal logic and input buffersCommercial T A = 0°C to +70°C 1.7 1.9V Industrial T A = –40°C to +85°C1.7 1.9V V CCIOSupply voltage for output drivers @ 3.3V operation 3.0 3.6V Supply voltage for output drivers @ 2.5V operation 2.3 2.7V Supply voltage for output drivers @ 1.8V operation 1.7 1.9V Supply voltage for output drivers @ 1.5V operation1.4 1.6V V CCAUXJTAG programming pins1.73.6VSymbol ParameterTest ConditionsTypical Max.Units I CCSB Standby current Commercial V CC = 1.9V, V CCIO = 3.6V 2290μA I CCSB Standby current Industrial V CC = 1.9V, V CCIO = 3.6V38150μA I CC (1)Dynamic current f = 1 MHz -0.25mA f = 50 MHz - 2.5mA C JTAG JTAG input capacitance f = 1 MHz -10pF C CLK Global clock input capacitance f = 1 MHz -12pF C IO I/O capacitance f = 1 MHz-10pF I IL (2)Input leakage current V IN = 0V or V CCIO to 3.9V -+/-1μA I IH (2)I/O High-Z leakageV IN = 0V or V CCIO to 3.9V-+/-1μANotes:1.16-bit up/down resettable binary counter (one per Function Block) tested at V CC = V CCIO = 1.9V.2.See Quality and Reliability section of the CoolRunner-II family data sheet.LVCMOS 3.3V and LVTTL 3.3V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.UnitsV CCIO Input source voltage 3.0 3.6VV IH High level input voltage2 3.9VV IL Low level input voltage–0.30.8VV OH High level output voltage I OH = –8 mA, V CCIO = 3V V CCIO – 0.4V-VI OH = –0.1 mA, V CCIO = 3V V CCIO – 0.2V-VV OL Low level output voltage I OL = 8 mA, V CCIO = 3V-0.4VI OL = 0.1 mA, V CCIO = 3V-0.2VLVCMOS 2.5V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.UnitsV CCIO Input source voltage 2.3 2.7VV IH High level input voltage 1.7V CCIO + 0.3(1)VV IL Low level input voltage–0.30.7VV OH High level output voltage I OH = –8 mA, V CCIO = 2.3V V CCIO – 0.4V-VI OH = –0.1 mA, V CCIO = 2.3V V CCIO – 0.2V-VV OL Low level output voltage I OL = 8 mA, V CCIO = 2.3V-0.4VI OL = 0.1mA, V CCIO = 2.3V-0.2V(1) The V IH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.LVCMOS 1.8V DC Voltage SpecificationsSymbol Parameter Test Conditions Min.Max.Units V CCIO Input source voltage 1.7 1.9VV IH High level input voltage0.65 x V CCIO V CCIO + 0.3(1)VV IL Low level input voltage–0.30.35 x V CCIO VV OH High level output voltage I OH = –8 mA, V CCIO = 1.7V V CCIO – 0.45-VI OH = –0.1 mA, V CCIO = 1.7V V CCIO – 0.2-VV OL Low level output voltage I OL = 8 mA, V CCIO = 1.7V-0.45VI OL = 0.1 mA, V CCIO = 1.7V-0.2V(1) The V IH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.LVCMOS1.5V DC Voltage Specifications(1)Symbol Parameter Test Conditions Min.Max.Units V CCIO Input source voltage 1.4 1.6VV T+Input hysteresis threshold voltage0.5 x V CCIO0.8 x V CCIO VV T-0.2 x V CCIO0.5 x V CCIO VV OH High level output voltage I OH = –8 mA, V CCIO = 1.4V V CCIO – 0.45-VI OH = –0.1 mA, V CCIO = 1.4V V CCIO – 0.2-V4DS310 (v2.0) March 8, 2007Schmitt Trigger Input DC Voltage SpecificationsAC Electrical Characteristics Over Recommended Operating ConditionsV OLLow level output voltageI OL = 8 mA, V CCIO = 1.4V -0.4V I OL = 0.1 mA, V CCIO = 1.4V-0.2VNotes:1.Hysteresis used on 1.5V inputs.Symbol ParameterTest ConditionsMin.Max.Units V CCIO Input source voltage1.4 3.9V V T+Input hysteresis threshold voltage0.5 x V CCIO 0.8 x V CCIO V V T-0.2 x V CCIO0.5 x V CCIOVSymbol Parameter-4-6Units Min.Max.Min.Max.T PD1Propagation delay single p-term - 3.8- 5.5ns T PD2Propagation delay OR array - 4.0- 6.0ns T SUD Direct input register clock setup time 1.7- 2.2-ns T SU1Setup time fast (single p-term) 1.9- 2.6-ns T SU2Setup time (OR array) 2.1- 3.1-ns T HD Direct input register hold time 0.0-0.0-ns T H P-term hold time 0.0-0.0-ns T CO Clock to output - 3.7- 4.7ns F TOGGLE (1)Internal toggle rate-500-300MHz F SYSTEM1(2)Maximum system frequency -323-200MHz F SYSTEM2(2)Maximum system frequency -303-182MHz F EXT1(3)Maximum external frequency -179-137MHz F EXT2(3)Maximum external frequency-172-128MHz T PSUD Direct input register p-term clock setup time 0.4-0.9-ns T PSU1P-term clock setup time (single p-term)0.6- 1.3-ns T PSU2P-term clock setup time (OR array)0.8- 1.8-ns T PHD Direct input register p-term clock hold time 1.5- 1.6-ns T PH P-term clock hold 1.3- 1.2-ns T PCO P-term clock to output- 5.0- 6.0ns T OE /T OD Global OE to output enable/disable - 4.7- 5.5ns T POE /T POD P-term OE to output enable/disable- 6.2- 6.7ns T MOE /T MOD Macrocell driven OE to output enable/disable - 6.2- 6.9ns T PAO P-term set/reset to output valid - 5.5- 6.8ns T AO Global set/reset to output valid - 4.5- 5.5ns T SUEC Register clock enable setup time 2.0- 3.0-ns T HEC Register clock enable hold time 0.0-0.0-ns T CW Global clock pulse width High or Low 1.4- 2.2-ns T PCWP-term pulse width High or Low4.0- 6.0-nsSymbol ParameterTest ConditionsMin.Max.Units6DS310 (v2.0) March 8, 2007T APRPW Asynchronous preset/reset pulse width (High or Low)4.0- 6.0-ns T CONFIG (4)Configuration time-50-50μsNotes:1.F TOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).2.F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term permacrocell while F SYSTEM2 is through the OR array .3.F EXT1 (1/T SU1+T CO ) is the maximum external frequency using one p-term while F EXT2 is through the OR array .4.Typical configuration current during T CONFIG is 500 μA.Symbol Parameter-4-6Units Min.Max.Min.Max.Internal Timing ParametersSymbol Parameter(1)-4-6Units Min.Max.Min.Max.Buffer DelaysT IN Input buffer delay- 1.3- 1.7ns T DIN Direct register input delay- 1.5- 2.4ns T GCK Global Clock buffer delay- 1.3- 2.0ns T GSR Global set/reset buffer delay- 1.6- 2.0ns T GTS Global 3-state buffer delay- 1.1- 2.1ns T OUT Output buffer delay- 1.8- 2.0ns T EN Output buffer enable/disable delay- 2.9- 3.4ns P-term DelaysT CT Control term delay- 1.3- 1.6ns T LOGI1Single p-term delay adder-0.4- 1.1ns T LOGI2Multiple p-term delay adder-0.2-0.5ns Macrocell DelayT PDI Input to output valid-0.3-0.7ns T LDI Setup before clock (transparent latch)- 1.5- 2.5ns T SUI Setup before clock 1.5- 1.8-ns T HI Hold after clock0.0-0.0-ns T ECSU Enable clock setup time 0.7- 1.7-ns T ECHO Enable clock hold time 0.0-0.0-ns T COI Clock to output valid-0.6-0.7ns T AOI Set/reset to output valid- 1.1- 1.5ns Feedback DelaysT F Feedback delay-0.6- 1.4ns T OEM Macrocell to global OE delay-0.7-0.8ns I/O Standard Time Adder Delays 1.5V CMOST HYS15Hysteresis input adder- 3.0- 4.0ns T OUT15Output adder-0.8- 1.0ns T SLEW15Output slew rate adder- 4.0- 5.0ns I/O Standard Time Adder Delays 1.8V CMOST HYS18Hysteresis input adder- 3.0- 4.0ns T OUT18Output adder-0.0-0.0ns T SLEW Output slew rate adder- 4.0- 5.0ns8DS310 (v2.0) March 8, 2007Switching CharacteristicsAC Test CircuitI/O Standard Time Adder Delays 2.5V CMOS T IN25Standard input adder -0.5-0.6ns T HYS25Hysteresis input adder - 3.0- 4.0ns T OUT25Output adder-0.6-0.7ns T SLEW25Output slew rate adder- 4.0- 5.0ns I/O Standard Time Adder Delays 3.3V CMOS/TTL T IN33Standard input adder -0.5-0.6ns T HYS33Hysteresis input adder - 3.0- 4.0ns T OUT33Output adder- 1.0- 1.2ns T SLEW33Output slew rate adder- 4.0- 5.0nsNotes:1. 1.5 ns input pin signal rise/fall.Internal Timing Parameters (Continued)Symbol Parameter (1)-4-6Units Min.Max.Min.Max.Figure 2: Derating Curve for T PDFigure 3: AC Load CircuitTypical I/O Output CurvesFigure 4: Typical I/V Curve for XC2C32APin DescriptionsFunction Block Macrocell QFG32PC44VQ44CP56I/O Bank 114438F1Bank 2124337E3Bank 2134236E1Bank 2 1(GTS1)434034D1Bank21(GTS0)523933C1Bank21(GTS3)613832A3Bank 21(GTS2)7323731A2Bank 21(GSR)8313630B1Bank 221 9303529A1Bank21 10293428C4Bank111283327C5Bank2112242923C8Bank21132822A10Bank2114232721B10Bank21152620C10Bank21162519E8Bank2215139G1Bank 122240F3Bank123341H1Bank124442G3Bank1 2(GCK0)56543J1Bank 12(GCK1)67644K1Bank 12(GCK2)7871K2Bank 110DS310 (v2.0) March 8, 2007XC2C32A Global, JTAG, Power/Ground and No Connect Pins28982K3Bank1291093H3Bank1210115K5Bank 1211126H5Bank 121213148H8Bank 1213171812K8Bank1214181913H10Bank1215192014G10Bank 12162216F10Bank1Notes:1.GTS = global output enable, GSR = global set reset, GCK = global clock2.GTS, GSR, and GCK pins can also be used for general purpose I/O.Pin TypeQFG32PC44(1)VQ44(1)CP56(1)TCK 161711K10TDI 14159J10TDO 253024A6TMS 151610K9Input Only22 (bank 2)24 (bank 2)18 (bank 2)D10 (bank 2)V CCAUX (JTAG supply voltage)44135D3Power internal (V CC )Power bank 1 I/O (V CCIO1)Power bank 2 I/O (V CCIO2)202115G812137H6273226C6Ground 11, 21, 2610,23,314,17,25H4, F8, C7No connects--K4, K6, K7, H7, E10, A7, A9, D8, A5, A8,A4, C3Total user I/O (includes dual function pins)21333333Notes:1.All packages pin compatible with larger macrocell densitiesPin Descriptions (Continued)Function BlockMacrocellQFG32PC44VQ44CP56I/O BankOrdering InformationPart Number Pin/BallSpacingθJA(C/Watt)θJC(C/Watt)Package TypePackage BodyDimensions I/OComm.(C)Ind. (I)(1)XC2C32A-4QFG32C0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21CXC2C32A-6QFG32C0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21CXC2C32A-4PC44C 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33CXC2C32A-6PC44C 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33CXC2C32A-4VQ44C0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33CXC2C32A-6VQ44C0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33C XC2C32A-4CP56C0.5mm66.014.9Chip Scale Package6mm x 6mm33C XC2C32A-6CP56C0.5mm66.014.9Chip Scale Package6mm x 6mm33C XC2C32A-4PCG44C 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33CXC2C32A-6PCG44C 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33CXC2C32A-4VQG44C0.8mm47.78.2Very Thin Quad FlatPack; Pb-free10mm x 10mm33CXC2C32A-6VQG44C0.8mm47.78.2Very Thin Quad FlatPack; Pb-free10mm x 10mm33CXC2C32A-4CPG56C0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33CXC2C32A-6CPG56C0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33CXC2C32A-6QFG32I0.5mm35.524.0Quad Flat No Lead;Pb-free5mm x 5mm21IXC2C32A-6PC44I 1.27mm55.135.3Plastic Leaded ChipCarrier16.5mm x 16.5mm33IXC2C32A-6VQ44I0.8mm47.78.2Very Thin Quad FlatPack10mm x 10mm33I XC2C32A-6CP56I0.5mm66.014.9Chip Scale Package6mm x 6mm33I XC2C32A-6PCG44I 1.27mm55.135.3Plastic Leaded ChipCarrier; Pb-free16.5mm x 16.5mm33I12DS310 (v2.0) March 8, 2007Device Part MarkingFigure 5: Sample Package with Part MarkingNote: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale and quad flat no lead packages by line are:•Line 1 = X (Xilinx logo) then truncated part number •Line 2 = Not related to device part number •Line 3 = Not related to device part number•Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C3 = CP56, C4 = CPG56, Q1 = QFG32.XC2C32A-6VQG44I 0.8mm 47.78.2Very Thin Quad Flat Pack; Pb-free 10mm x 10mm 33I XC2C32A-6CPG56I0.5mm66.014.9Chip Scale Package;Pb-free6mm x 6mm33INotes:1. C = Commercial (T= 0°C to +70°C); I = Industrial (T = –40°C to +85°C)Part Number Pin/Ball Spacing θJA (C/Watt)θJC (C/Watt)Package Type Package Body Dimensions I/O Comm. (C)Ind. (I)(1)Figure 6: QFG32 PackageFigure 7: VQ44 PackageFigure 8: PC44 PackageFigure 9: CP56 PackageWarranty DisclaimerTHESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT /warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.14DS310 (v2.0) March 8, 2007Additional InformationAdditional information is available for the following CoolRunner-II topics:•XAPP784: Bulletproof CPLD Design Practices •XAPP375: Timing Model•XAPP376: Logic Engine•XAPP378: Advanced Features•XAPP382: I/O Characteristics•XAPP389: Powering CoolRunner-II•XAPP399: Assigning VREF Pins To access these and all application notes with their associ-ated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device PackagesRevision HistoryThe following table shows the revision history for this document.Date Version Revision6/15/04 1.0Initial Xilinx release.8/30/04 1.1Pb-free documentation10/01/04 1.2Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.11/08/04 1.3Product Release. No changes to documentation.11/22/04 1.4Changes to output enable/disable specifications; changes to I CCSB.02/17/05 1.5Changes to f TOGGLE, t SLEW25, and t SLEW3303/07/05 1.6Improvement of pin-to-pin logic delay, page 1. Modifications to Table 1, IOSTANDARDs.06/28/05 1.7Move to Product Specification. Change to T IN25, T OUT25, T IN33, and T OUT33.03/20/06 1.8Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can alsobe used for general purpose I/O.02/15/07 1.9Change to V IH specification for 2.5V and 1.8V LVCMOS. Change to T OEM for -4 speedgrade.03/08/07 2.0Fixed typo in note for V IL for LVCMOS18; removed note for V IL for LVCMOS33.16DS310 (v2.0) March 8, 2007。
FPGA可编程逻辑器件芯片XC2C256-7FTG256I中文规格书
Features•Optimized for 1.8V systems-As fast as 5.7 ns pin-to-pin delays-As low as 13 μA quiescent current•Industry’s best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis.Refer to the CoolRunner™-II family data sheet forarchitecture description.-Multi-voltage I/O operation — 1.5V to 3.3V •Available in multiple package options-100-pin VQFP with 80 user I/O-144-pin TQFP with 118 user I/O-132-ball CP (0.5mm) BGA with 106 user I/O-208-pin PQFP with 173 user I/O-256-ball FT (1.0mm) BGA with 184 user I/O-Pb-free available for all packages•Advanced system features-Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface -IEEE1149.1 JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-Unsurpassed low power management·DataGATE enable (DGE) signal control -Two separate I/O banks-RealDigital 100% CMOS product term generation -Flexible clocking modes·Optional DualEDGE triggered registers·Clock divider (divide by 2,4,6,8,10,12,14,16)·CoolCLOCK-Global signal options with macrocell control·Multiple global clocks with phase selection permacrocell·Multiple global output enables·Global set/reset-Advanced design security-PLA architecture·Superior pinout retention·100% product term routability across functionblock-Open-drain output option for Wired-OR and LED drive-Optional bus-hold, 3-state or weak pull-up on selected I/O pins-Optional configurable grounds on unused I/Os-Mixed I/O voltages compatible with 1.5V, 1.8V,2.5V, and3.3V logic levels·SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility -Hot pluggable DescriptionThe CoolRunner™-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli-ability is improvedThis device consists of sixteen Function Blocks inter-con-nected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to stor-ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.A global set/reset control line is also available to asynchro-nously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchro-nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.A DualEDGE flip-flop feature is also available on a per mac-rocell basis. This feature allows high performance synchro-nous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of theCPLD that are not of interest during certain points in time.XC2C256 CoolRunner-II CPLDAbsolute Maximum RatingsSymbol Description Value Units V CC Supply voltage relative to ground–0.5 to 2.0VV CCIO Supply voltage for output drivers–0.5 to 4.0V V JTAG(2)JTAG input voltage limits–0.5 to 4.0V V CCAUX JTAG input supply voltage–0.5 to 4.0VV IN(1)Input voltage relative to ground–0.5 to 4.0VV TS(1)Voltage applied to 3-state output–0.5 to 4.0V T STG(3)Storage Temperature (ambient)–65 to +150°C T J Junction Temperature+150°CXC2C256 CoolRunner-II CPLDPin Type VQ100CP132TQ144PQ208FT256 TCK48M106798P12TDI45M96394R11TDO83B9122176A10TMS47N106596N12V CCAUX (JTAG supplyvoltage)5D3811F4 Power internal (V CC)26, 57P1, K12, A21, 37, 841, 53, 124P3, K13, D12, D5Power Bank 1 I/O (V CCIO1)20, 38, 51J3, P7,G14, P1327, 55, 73, 9333, 59, 79, 92,105, 132J6, K6, L7, L8, J11,K11, L10, L9Power Bank 2 I/O (V CCIO2)88, 98A14, C4, A7109, 127, 14126, 133, 157,172, 181, 204 F7, F8, G6, H6, F10,F9, H11Ground 21, 25, 31,62, 69, 75,84, 100K2, N1, P4,N9, N12,J14, H14,E14, B14,A9, B329, 36, 47, 62,72, 89, 90, 99,108, 123, 14413, 24, 42, 52,68, 81, 93, 104,129, 130, 141,156, 177, 190,207F11, F6, G10, G7, G8,G9, H10, H7, H8, H9,J10, J7, J8, J9, K10,K7, K8, K9, L11, L6No connects----A1, C2, E6, D1, E1, G2,F1, G1, M4, T9, P9,M9, M10, T11, T12,T13, P11, T14, J16,K12, D16, G12, C15,D14, D6, C6, E7, C5 Total user I/O80106118173184Additional InformationAdditional information is available for the following CoolRunner-II topics:•XAPP784: Bulletproof CPLD Design Practices •XAPP375: Timing Model•XAPP376: Logic Engine•XAPP378: Advanced Features•XAPP382: I/O Characteristics•XAPP389: Powering CoolRunner-II•XAPP399: Assigning VREF Pins To access these and all application notes with their associ-ated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device PackagesRevision HistoryThe following table shows the revision history for this document.Date Version Revision05/09/02 1.0Initial Xilinx release.05/13/02 1.1Updated AC Electrical Characteristics and added new parameters.10/31/02 1.2Corrected package user I/O, added Voltage Referenced DC tables.03/17/03 2.0Added Characterization numbers for product release and device part marking04/02/03 2.1Updated T SOL max from 260 to 220. Changed I CCSB units from mA to μA.01/26/04 2.2Updated Device Part Marking. Updated links and Tsol.02/26/04 2.3Corrected Theta JC value on XC2C256-7TQ144.08/03/04 2.4Pb-free documentation08/19/04 2.5Changes to I CCSB maximum specifications in DC Electrical Characteristics table, on page 3.10/01/04 2.6Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.03/07/05 2.7Removed -5 speed grade. Changes to Table 1, I/O Standards.06/28/05 2.8Move to Product Specification. Change to T IN25, T OUT25, T IN33, and T OUT33 for -7 speedgrade.03/20/06 2.9Add Warranty Disclaimer. Add note to Pin Description table that GTS, GSR and GCK pins canbe used for general purpose I/O.5/20/06 3.0Moved T CONFIG specification values from MIN column to MAX column, page 7.02/15/07 3.1Corrections to timing parameters t AOI, t PSUD, t PSU1, t PSU2, t PHD, t PCO, t POE, t PAO, t AO,t SUEC, t CW, t CDRSU, and f TOGGLE for -6 speed grade. Corrections to t PSUD, t CW, and t CDRSUfor the -7 speed grade. Values now match the software. There were no changes to siliconor characterization. Change to V IH specification for 2.5V and 1.8V LVCMOS.03/08/07 3.2Fixed typo in note for V IL for LVCMOS18; removed note for V IL for LVCMOS33.。
74LCX125中文资料
1/12September 2004s 5V TOLERANT INPUTS AND OUTPUTS sHIGH SPEED:t PD = 5.2 ns (MAX.) at V CC = 3VsPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN) at V CC = 3Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2.0V to 3.6V (1.5V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125sLATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)sESD PERFORMANCE:HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74LCX125 is a low voltage CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power and highspeed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs.The device requires the 3-STATE control input G to be set high to place the output in to the high impedance state.It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74LCX125LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTSFigure 1: Pin Connection And IEC Logic SymbolsTable 1: Order CodesPACKAGE T & R SOP 74LCX125MTR TSSOP74LCX125TTR74LCX1252/12Figure 2: Input And Output Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareZ : High ImpedanceTable 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied1) I O absolute maximum rating must be observed 2) V O< GNDPIN N°SYMBOL NAME AND FUNCTION 1, 4, 10, 131G TO 4G Output Enable Input 2, 5, 9, 121A TO 4A Data Inputs 3, 6, 8, 111Y TO 4Y Data Outputs 7GND Ground (0V)14V CCPositive Supply VoltageA G Y X H Z L L L HLHSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage-0.5 to +7.0V V O DC Output Voltage (OFF State or High Impedance)-0.5 to +7.0V V O DC Output Voltage (High or Low State) (note 1)-0.5 to V CC + 0.5V I IK DC Input Diode Current- 50mA I OK DC Output Diode Current (note 2)- 50mA I O DC Output Current± 50mA I CC DC Supply Current per Supply Pin ± 100mA I GND DC Ground Current per Supply Pin ± 100mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°C74LCX1253/12Table 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.5V to 3.6V 2) V IN from 0.8V to 2V at V CC = 3.0VTable 6: DC SpecificationsSymbol ParameterValue Unit V CC Supply Voltage (note 1) 2.0 to 3.6V V I Input Voltage0 to 5.5V V O Output Voltage (OFF State or High Impedance)0 to 5.5V V O Output Voltage (High or Low State)0 to V CC V I OH , I OL High or Low Level Output Current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or Low Level Output Current (V CC = 2.7V)± 12mA T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2)0 to 10ns/VSymbolParameterTest ConditionValueUnitV CC (V)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.V IH High Level Input Voltage2.7 to3.62.02.0V V IL Low Level Input Voltage0.80.8VV OHHigh Level Output Voltage2.7 to3.6I O =-100 µA V CC -0.2V CC -0.2V2.7I O =-12 mA 2.2 2.23.0I O =-18 mA 2.4 2.4I O =-24 mA 2.22.2V OLLow Level Output Voltage2.7 to3.6I O =100 µA 0.20.2V 2.7I O =12 mA 0.40.43.0I O =16 mA 0.40.4I O =24 mA 0.550.55I I Input Leakage Current2.7 to3.6V I = 0 to 5.5V ± 5± 5µA I off Power Off Leakage Current0V I or V O = 5.5V 1010µA I OZ High Impedance Output Leakage Current2.7 to3.6V I = V IH or V IL V O = 0 to V CC ± 5± 5µA I CC Quiescent Supply Current2.7 to3.6V I = V CC or GND 1010µA V I or V O = 3.6 to 5.5V ± 10± 10∆I CCI CC incr. per Input2.7 to3.6V IH = V CC - 0.6V500500µA74LCX1254/12Table 7: Dynamic Switching Characteristics1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.Table 8: AC Electrical Characteristics1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |)2) Parameter guaranteed by designTable 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /4 (per gate)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.V OLP Dynamic Low Level Quiet Output (note 1)3.3C L = 50pFV IL = 0V, V IH = 3.3V0.8V V OLV-0.8SymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.t PLH t PHL Propagation Delay Time2.750500 2.5 6.0 6.9ns3.0 to 3.6 1.0 5.2 1.0 6.0t PZL t PZH Output Enable Time to HIGH and LOW level2.7505002.51.0 6.0 1.0 6.9ns 3.0 to 3.6 1.0 5.0 1.0 6.0t PLZ t PHZ Output Disable Time to HIGH and LOW level2.750500 2.5 1.0 6.0 1.0 6.9ns3.0 to 3.6 1.05.0 1.06.0t OSLH t OSHLOutput To Output Skew Time (note1, 2)3.0 to 3.6505002.51.01.0ns SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.C IN Input Capacitance 3.3V IN = 0 to V CC 5pF C OUT Output Capacitance3.3V IN = 0 to V CC 10pF C PDPower Dissipation Capacitance (note 1)3.3f IN = 10MHz V IN = 0 or V CC37pF74LCX1255/12Figure 3: Test CircuitC L = 50 pF or equivalent (includes jig and probe capacitance)R L = R1 = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)Figure 4: Waveform - Propagation Delay (f=1MHz; 50% duty cycle)TESTSWITCH t PLH , t PHL Open t PZL , t PLZ 6V t PZH , t PHZGND74LCX125Figure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)6/1274LCX1257/12DIM.mm.inch MIN.TYPMAX.MIN.TYP.MAX.A 1.35 1.750.0530.069A10.10.250.0040.010A2 1.10 1.650.0430.065B 0.330.510.0130.020C 0.190.250.0070.010D 8.558.750.3370.344E 3.84.00.1500.157e 1.270.050H 5.8 6.20.2280.244h 0.250.500.0100.020L 0.4 1.270.0160.050k 0°8°0°8°ddd0.1000.004SO-14 MECHANICAL DATA0016019D74LCX1258/12DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0089D 4.95 5.10.1930.1970.201E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP14 MECHANICAL DATAcEbA2A E1D1PIN 1 IDENTIFICATIONA1LKe0080337D74LCX125 Tape & Reel SO-14 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T22.40.882Ao 6.4 6.60.2520.260Bo99.20.3540.362Ko 2.1 2.30.0820.090Po 3.9 4.10.1530.161P7.98.10.3110.3199/1274LCX125Tape & Reel TSSOP14 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T22.40.882 Ao 6.7 6.90.2640.272 Bo 5.3 5.50.2090.217 Ko 1.6 1.80.0630.071 Po 3.9 4.10.1530.161 P7.98.10.3110.31910/1274LCX125 Table 10: Revision HistoryDate Revision Description of Changes 15-Sep-20045Ordering Codes Revision - pag. 1.11/1274LCX125Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America12/12。
MAX9140 MAX9141 MAX9142 MAX9144高速比较器说明书
General DescriptionThe MAX9140/MAX9141 are single and the MAX9142/MAX9144 are dual/quad high-speed comparators optimized for systems powered from a 3V or 5V supply. The MAX9141 features latch enable and device shutdown. These devices combine high speed, low power, and rail-to-rail inputs. Propagation delay is 40ns, while supply current is only 150μA per comparator.The input common-mode range of the devices extends beyond both power-supply rails. The outputs pull to within 0.3V of either supply rail without external pullup circuitry, making these devices ideal for interface with both CMOS and TTL logic. All input and output pins can tolerate a continuous short-circuit fault condition to either rail. Internal hysteresis ensures clean output switching, even with slow-moving input signals.The devices are higher-speed, lower-power, and lower-cost upgrades to industry-standard comparators MAX941/MAX942/MAX944.The MAX9140 are offered in tiny 5-pin SC70 and SOT23 packages. The MAX9141 and MAX9142 are available in 8-pin SOT23 and SO packages, while the MAX9144 is available in both 14-pin SO and TSSOP packages.Applications●Line Receivers●Battery-Powered Systems●Threshold Detectors/Discriminators ●3V/5V Systems●Zero-Crossing Detectors●Sampling CircuitsFeatures●Fast, 40ns Propagation Delay (10mV Overdrive) ●Low Power• 150μA Supply Current Per Comparator (3V) ●Optimized for 3V and 5V Applications ●Rail-to-Rail Input Voltage Range ●Low, 500μV Offset Voltage●Internal Hysteresis for Clean Switching ●Outputs Swing 300mV of Power Rails ●CMOS/TTL-Compatible Outputs ●Output Latch (MAX9141 Only)●Shutdown Function (MAX9141 Only) ●Available in SC70 and SOT23 Packages●AEC-Q100 Qualified (MAX9140AAXK/V+T Only)19-2064; Rev 9; 10/19Click here for production status of specific part numbers.MAX9140/MAX9141/MAX9142/MAX914440ns, Low-Power, 3V/5V, Rail-to-RailSingle-Supply ComparatorsPin ConfigurationsPower-Supply RangesSupply Voltage (V CC to GND) ...........................................+6V IN+, IN- to GND ....................................-0.3V to (V CC + 0.3V) LE Input Voltage (MAX9141 only) ........-0.3V to (V CC + 0.3V) SHDN Input Voltage (MAX9141 only) ..-0.3V to (V CC + 0.3V)Current into Input Pins .....................................................±20mA Input/Output Short-Circuit Duration toV CC or GND ..........................................................Continuous Continuous Power Dissipation (T A = +70°C)5-Pin SC70 (derate 3.1mW/°C above +70°C) .............247mW 5-Pin SOT23 (derate 7.1mW/°C above +70°C) ..........571mW8-Pin SOT23 (derate 9.1mW/°C above +70°C) ..........727mW 8-Pin SO (derate 5.9mW/°C above +70°C) ..............470.6mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) ........727mW 14-Pin SO (derate 8.33mW/°C above +70°C) ..........666.7mW Operating Temperature RangeE grade ...........................................................-40°C to +85°C A grade .........................................................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C(V CC = 5V, V CM = 0V, SHDN = LE = V CC (MAX9141 only), C L = 15pF, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)PARAMETERSYMBOL CONDITIONSMIN TYPMAX UNITS Operating Supply Voltage V CC (Note 2) 2.7 5.5V Input Voltage RangeV CMR (Note 3)-0.2V CC + 0.2VInput Offset Voltage V OS (Note 4)T A = +25°C0.5 2.0mV T A = -40°C to +85°C 4.5MAX9140AA_ _6.0Input Hysteresis V HYST (Note 5) 1.5mV Input Bias Current I B (Note 6)T A = -40°C to +85°C 90320nA MAX9140AA_ _350Input Offset CurrentI OS T A = -40°C to +85°C 8120nA MAX9140AA_ _140Common-Mode Rejection Ratio CMRR V CC = 5.5V (Note 7)T A = -40°C to +85°C 80800µV/V MAX9140AA_ _850Power-Supply Rejection RatioPSRR2.7V ≤ V CC ≤ 5.5V T A = -40°C to +85°C 80750µV/V MAX9140AA_ _800Output High VoltageV OH I SOURCE = 4mA T A = -40°C to +85°C V CC - 0.425V CC - 0.3VMAX9140AA_ _V CC - 0.47Output Low Voltage V OL I SINK = 4mAT A = -40°C to +85°C 0.30.425V MAX9140AA_ _0.45Output Leakage CurrentI LEAKSHDN = GND, MAX9141 only (Note 8)0.041µAMAX9142/MAX9144Single-Supply ComparatorsAbsolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(V CC = 5V, V CM = 0V, SHDN = LE = V CC (MAX9141 only), C L = 15pF, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)Note 1: All devices are 100% production tested at T A = +25°C. Specifications over temperature are guaranteed by design.Note 2: Inferred from PSRR test.Note 3: Inferred from CMRR test. Note also that either or both inputs can be driven to the absolute maximum limit (0.3V beyondeither supply rail) without damage or false output inversion.Note 4: V OS is defined as the center of the input-referred hysteresis zone. See Figure 1.Note 5: The input-referred trip points are the extremities of the differential input voltage required to make the comparator outputchange state. The difference between the upper and lower trip points is equal to the width of the input-referred hysteresis zone. See Figure 1.Note 6: The polarity of I B reverses direction as V CM approaches either supply rail.Note 7: Specified over the full common-mode voltage range (V CMR ).Note 8: Specification is for current flowing into or out of the output pin for V OUT driven to any voltage from V CC to GND while the partis in shutdown.Note 9: Specified between any two channels in the MAX9142/MAX9144.Note 10: Specified as the difference between t PD+ and t PD- for any one comparator.Note 11: Applies to the MAX9141 only for both SHDN and LE .Note 12: Applies to the MAX9141 only. Comparator is active with LE driven high and is latched with LE driven low (V OD = 10mV). SeeFigure 2.Note 13: Applicable to the MAX9141 only. Comparator is active with the SHDN driven high and is shutdown with SHDN driven low.Shutdown enable time is the delay when the SHDN is driven high to the time the output is valid. Shutdown disable time is the delay when the SHDN is driven low to the time the comparator shuts down.PARAMETERSYMBOLCONDITIONSMINTYP MAX UNITSSupply Current (Per Comparator)I CCV CM = V CC = 3VMAX9141165275µA MAX9140,T A = -40°C to 85°C 150250MAX9140AA_ _360MAX9142/MAX9144150250V CM = V CC = 5VMAX9141200320MAX9140,T A = -40°C to 85°C 165300MAX9140AA_ _400MAX9142/MAX9144165300MAX9141 only, SHDN = GND; V CC = V CM = 3V1230Propagation Delayt PD+, t PD-V CC = 3V, V OD = 10mV 40ns Differential Propagation Delay dt PDV OD = 10mV (Note 9)2ns Propagation Delay Skew V OD = 10mV (Note 10)2ns Logic Input-Voltage High V IH (Note 11)(V CC /2) +0.4V CC /2V Logic Input-Voltage Low V IL (Note 11)V CC /2(V CC /2) -0.4V Logic Input Current I IL , I IH V LOGIC = 0 to V CC (Note 11)210µA Data-to-Latch Setup Time t S (Note 12)16ns Latch-to-Data Hold Time t H (Note 12)16ns Latch Pulse Width t LPW (Note 12)45ns Latch Propagation Delay t LPD (Note 12)60ns Shutdown Enable Time (Note 13)1µs Shutdown Disable Time(Note 13)5µs MAX9142/MAX9144Single-Supply ComparatorsElectrical Characteristics (continued)(V CC = 3.0V, V CM = 0V, C L = 15pF, V OD = 10mV, T A = +25°C, unless otherwise noted.)320322326324328330-400-2020406080100OUTPUT LOW VOLTAGE vs. TEMPERATURETEMPERATURE (°C)V O L (m V )5.005.055.105.155.20-400-2020406080100OUTPUT HIGH VOLTAGE vs. TEMPERATURETEMPERATURE (°C)V O H (V )35404550-400-2020406080100OUTPUT SHORT-CIRCUIT (SINK) CURRENTvs. TEMPERATURETEMPERATURE (°C)O U T P U T S H O R T -C I R C U I T S I N K C U R R E N T (m A)15253545-40-2020406080100OUTPUT SHORT-CIRCUIT (SOURCE) CURRENT vs. TEMPERATURETEMPERATURE (°C)O U T P U T S H O R T -C I R C U I T S O U R C E C U R R E N T (m A )0100502001502503003456MAX9140 SUPPLY CURRENT vs. SUPPLY VOLTAGEV CC (V)I C C (A )40208060120100140-5025-255075100INPUT BIAS CURRENT vs. TEMPERATURETEMPERATURE (°C)I N P U T C U R R E N T (n A )MAX9142/MAX9144Single-Supply ComparatorsTypical Operating Characteristics(V CC = 3.0V, V CM = 0V, C L = 15pF, V OD = 10mV, T A = +25°C, unless otherwise noted.)-500-200-300-400-1000100200300400500-50-25255075100INPUT OFFSET VOLTAGE vs. TEMPERATURETEMPERATURE (°C)V O S (µV )-1.0-0.4-0.6-0.8-0.200.20.40.60.81.0-500-25255075100TRIP POINT vs. TEMPERATURETEMPERATURE (°C)V O S (m V )-110326547-40-2020406080100INPUT VOLTAGE RANGE vs. TEMPERATURETEMPERATURE (°C)I N P U T V O L T A G E R A N G E (V )202535304045040206080100PROPAGATION DELAY vs. INPUT OVERDRIVEINPUT OVERDRIVE (mV)P R O P A G A T I O N D E L A Y (n S )253040354550-50-25255075100PROPAGATION DELAY vs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (n s )2030254035504555154560307590105PROPAGATION DELAY vs. CAPACITIVE LOADCAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )MAX9142/MAX9144Single-Supply ComparatorsTypical Operating Characteristics (continued)(V CC = 3.0V, V CM = 0V, C L = 15pF, V OD = 10mV, T A = +25°C, unless otherwise noted.)PINNAME FUNCTIONMAX9140MAX9141MAX9142MAX9144——11OUTA Comparator A Output ——22INA-Comparator A Inverting Input ——33INA+Comparator A Noninverting Input 5184V CC Positive Supply——55INB+Comparator B Noninverting Input ——66INB-Comparator B Inverting Input ——77OUTB Comparator B Output ———8OUTC Comparator C Output ———9INC-Comparator C Inverting Input ———10INC+Comparator C Noninverting Input 24411GND Ground———12IND+Comparator D Noninverting Input ———13IND-Comparator D Inverting Input ———14OUTD Comparator D Output 32——IN+Noninverting Input 43——IN-Inverting Input—6——SHDN Shutdown: MAX9141 is active when SHDN is driven high; MAX9141 is in shutdown when SHDN is driven low.—5——LE The output is latched when LE is low. The latch is transparent when LE is high.17——OUT Comparator Output—8——N.C.No Connection. Not internally connected.OUTPUT 2V/div INPUT 50mV/divPROPAGATION DELAY (t PD -)10ns/div V OD = 10mV V CC = 5.5VOUTPUT 2V/div INPUT 50mV/divPROPAGATION DELAY (t PD +)10ns/div V OD = 10mVV CC = 5.5VOUTPUT 2V/divINPUT 50mV/divSINUSOID RESPONSE AT 4MHz50ns/divV CC = 5.5VMAX9142/MAX9144Single-Supply ComparatorsPin DescriptionTypical Operating Characteristics (continued)Detailed DescriptionThe MAX9140/MAX9141/MAX9142/MAX9144 single-supply comparators feature internal hysteresis, high speed, and low power. Their outputs are pulled to within 300mV of either supply rail without external pullup or pulldown circuitry. Rail-to-rail input voltage range and low-voltage single-supply operation make these devices ideal for portable equipment. The devices interface directly to CMOS and TTL logic.Most high-speed comparators oscillate in the linear region because of noise or undesired parasitic feedback. This tends to occur when the voltage on one input is at or equal to the voltage on the other input. To counter the parasitic effects and noise, the devices have an internal hysteresis of 1.5mV.The hysteresis in a comparator creates two trip points: one for the rising input voltage and one for the falling input voltage (Figure 1). The difference between the trip points is the hysteresis. The average of the trip points is the offset voltage. When the comparator’s input voltages are equal, the hysteresis effectively causes one comparator input voltage to move quickly past the other, thus taking theinput out of the region where oscillation occurs. Standard comparators require hysteresis to be added with external resistors. The devices’ fixed internal hysteresis eliminates these resistors. To increase hysteresis and noise margin even more, add positive feedback with two resistors as a voltage divider from the output to the noninverting input. Figure 1 illustrates the case where IN- is fixed and IN+ is varied. If the inputs were reversed, the figure would look the same, except the output would be inverted.The MAX9141 includes an internal latch that allows storage of comparison results. The LE pin has a high input impedance. If LE is high, the latch is transparent (i.e., the comparator operates as though the latch is not present). The comparator’s output state is latched when LE is pulled low (Figure 2).Shutdown Mode (MAX9141 Only)The MAX9141 shuts down when the SHDN pin is low. When shut down, the supply current drops to less than 12μA, and the three-state output becomes high impedance. The SHDN pin has a high-input impedance. Connect SHDN to V CC for normal operation. Exit shutdown with LE high (transparent state); otherwise, the output will be indeterminate.Input Stage CircuitryThe devices include internal protection circuitry that prevents damage to the precision input stage from large differential input voltages. This protection circuitry consists of two back-toback diodes between IN+ and IN- as well as two series 4.1kΩ resistors (Figure 3). The diodes limit the differential voltage applied to the internal circuitry of the comparators to be no more than 2V F, where V F is the forward voltage drop of the diode (about 0.7V at +25°C). For a large differential input voltage (exceeding 2V F), this protection circuitry increases the input bias current at IN+ (source) and IN- (sink).F(IN+ - IN-) - 2VInput Current2 4.1k=×ΩInput current with large differential input voltages should not be confused with input bias current (I B). As long as the differential input voltage is less than 2V F, this input current is equal to I B. The output is in the correct logic state if one or both inputs are within the common-mode range. Figure 1. Input and Output Waveform, Noninverting Input VariedMAX9142/MAX9144Single-Supply ComparatorsOutput Stage CircuitryThe MAX9140/MAX9141/MAX9142/MAX9144 contain a current-driven output stage as shown in Figure 4. During an output transition, I SOURCE or I SINK is pushed or pulled to the output pin. The output source or sink current is high during the transition, creating a rapid slew rate. Once the output voltage reaches V OH or V OL , the source or sink current decreases to a small value, capable of maintaining the V OH or V OL static condition. This significant decrease in current conserves power after an output transition has occurred.One consequence of a current-driven output stage is a linear dependence between the slew rate and the load capacitance. A heavy capacitive load will slow down a voltage output transition. This can be useful in noisesensitive applications where fast edges may cause interference.Applications InformationCircuit Layout and BypassingThe high-gain bandwidth of the MAX9140/MAX9141/MAX9142/MAX9144 requires design precautions to real-ize the full high-speed capabilities of these comparators. The recommended precautions are:1) Use a PCB with a good, unbroken, low-inductance ground plane.2) Place a decoupling capacitor (a 0.1μF ceramic capacitor is a good choice) as close to V CC as possible.3) Pay close attention to the decoupling capacitor’s bandwidth, keeping leads short.4) On the inputs and outputs, keep lead lengths short to avoid unwanted parasitic feedback around the comparators.5) Solder the device directly to the PCB instead of using a socket.Figure 2. MAX9141 Timing Diagram with Latch OperatorFigure 3. Input Stage CircuitryMAX9142/MAX9144Single-Supply ComparatorsFigure 4. Output Stage Circuitry Figure 5. 3.3V Digitally Controlled Threshold DetectorFigure 6. Line Receiver ApplicationMAX9142/MAX9144Single-Supply ComparatorsChip InformationPROCESS: BipolarNote: All E-grade devices are specified over the -40°C to +85°C operating temperature range. All A-grade devices are specified over the -40°C to +125°C operating temperature range.+Denotes a lead(Pb)-free/RoHS-compliant package.-Denotes a package containing lead(Pb).T = Tape and reel.Ordering InformationPART*PIN-PACKAGETOP MARK MAX9140AAUK+T 5 SOT23+AFEJ MAX9140AAXK+T 5 SC70+ASW MAX9140AAXK/V+T5 SC70+AUG MAX9140EXK-T 5 SC70ACC MAX9140EUK-T 5 SOT23ADQP MAX9141EKA-T 8 SOT23AAFD MAX9141ESA 8 SO —MAX9142EKA+8 SOT23+AAFE MAX9142EKA+T 8 SOT23+AAFE MAX9142ESA+8 SO —MAX9142ESA+T 8 SO —MAX9142EKA-T 8 SOT23AAFE MAX9142ESA 8 SO —MAX9144EUD 14 TSSOP —MAX9144ESD14 SO—MAX9142/MAX9144Single-Supply Comparators Package InformationFor the latest package outline information and land patterns (footprints), go to /packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.PACKAGE TYPE PACKAGE CODE DOCUMENT ND PATTERN NO.8 SOT23K8-521-007890-01765 SOT23U5-121-005790-01745 SC70X5+121-007690-018814 TSSOP U14-121-006690-01138 SO S8-221-004190-009614 SO S14-121-004190-0112REVISION NUMBERREVISION DATE DESCRIPTIONPAGES CHANGED06/01Initial release—11/07Updated Absolute Maximum Ratings with ±20mA current into input pin.2212/07Added two new automotive grade products.1, 231/10Added automotive qualified part146/14Added Junction Temperature to Absolute Maximum Ratings259/15Removed MAX9140AAXK/V from Ordering Information and edited the Absolute Maximum Ratings1, 2610/15Updated TOC7 and TOC8 in the Typical Operating Characteristics section 6711/17Added AEC statement to Features section and updated Ordering Information table1, 981/19Removed embedded package outline drawings 10–13910/19Updated Ordering Information9Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.MAX9140/MAX9141/MAX9142/MAX914440ns, Low-Power, 3V/5V, Rail-to-RailSingle-Supply Comparators© 2019 Maxim Integrated Products, Inc. │ 11Revision HistoryFor pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https:///en/storefront/storefront.html.。
CE77资料
DS06-20112-2EFUJITSU SEMICONDUCTORDATA SHEETCopyright©2002-2007 FUJITSU LIMITED All rights reservedSemicustomCMOSEmbedded arrayCE77 Series■DESCRIPTIONThe CE77 series 0.25 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time.CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.■FEATURES•Technology : 0.25 µm silicon-gate CMOS, 3- to 4-layer wiring •Supply voltage : +2.5 V ± 0.2 V (normal) to +1.5 V ± 0.1 V •Junction temperature range : −40 °C to +125 °C•Gate delay time : t pd = 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load) •Gate power consumption : 0.02 µW/MHz (1.5 V, F/O = 1, No load) •High-load driving capability : I OL = 2 mA/4 mA/8 mA/12 mA mixable •Output buffer cells with noise reduction circuits•Inputs with on-chip input pull-up/pull-down resistors (25 k Ω typical) and bidirectional buffer cells •Buffer cells dedicated to crystal oscillator•Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL +, and others including those under development)•IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development) •Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.) •Configurable internal bus circuits•Advanced hardware/software co-design environment •Support for static timing sign-offDramatically reducing the time for generating test vectors for timing verification and the simulation time •Hierarchical design environment for supporting large-scale circuits•Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,supporting development with minimized timing trouble after trial manufacture(Continued)CE77 Series2(Continued)•Support for memory (RAM/ROM) SCAN•Support for memory (RAM) BIST•Support for boundary SCAN•Support for path delay test•A variety of package options(SQFP, HQFP, PBGA, LQFP, FBGA under development)■MACRO LIBRARY (Including macros being prepared)1. Logic cells (about 700 types)2.IP macros3.Special I/O interface macros•Adder•AND-OR•AND-OR Inverter•Decoder•Clock Buffer•Non-SCAN Flip Flop•Latch•Inverter•NAND•Buffer•AND•OR-AND Inverter•NOR•OR•SCAN Flip Flop•Selector•BUS Driver•ENOR•EOR•Boundary Scan Register•OthersCPU SPARClite, ARM7Interface macro USB, IrDA, etc.Multimedia processing macros JPEG, etc.Mixed signal macros ADC, DAC, Analog switch, etc. Compiled macros RAM, ROM, FIFO, Delay Line, PLL Analog PLL•P-CML•USBCE77 Series3■CHIP STRUCTUREThe chip layout of the CE77 series consists of two major areas : chip peripheral area and basic cell area.The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells.•Chip configurationCE77 Series4■COMPILED CELLSCompiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE77 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) .1.Clock synchronous single-port RAM (1 address, 1 RW)(High density type) / (Partial write type)(Ultra high density type)(Low power consumption type)(High speed type)2.Clock synchronous dual-port RAM (2 addresses, 1 RW/1 R)3.Clock synchronous register file (3 addresses, 1W/2R)4.Clock synchronous register file (4 addresses, 2W/2R)Column type Memory capacity Word range Bit range Unit 416 to 72 K16 to 1 K 1 to 72bit1664 to 72 K64 to 4 K 1 to 18bitColumn type Memory capacity Word range Bit range Unit 464 to 72 K32 to 1 K 2 to 72bit42064 to 512 K1032 to 4 K 2 to 128bit164160 to 512 K2080 to 16 K 2 to 32bitColumn type Memory capacity Word range Bit range Unit 4128 to 72 K32 to 1 K 4 to 72bit8256 to 72 K64 to 2 K 4 to 36bitColumn type Memory capacity Word range Bit range Unit 8128 to 144 K32 to 2 K 4 to 72bitColumn type Memory capacity Word range Bit range Unit 416 to 72 K16 to 1 K 1 to 72bit1664 to 72 K64 to 4 K 1 to 18bitColumn type Memory capacity Word range Bit range Unit 14608 4 to 64 1 to 72bitColumn type Memory capacity Word range Bit range Unit 14608 4 to 64 1 to 72bitCE77 Series5.Clock synchronous ROM (1 address, 1R)Column type Memory capacity Word range Bit range Unit 8128 to 512 K32 to 4 K 4 to 128bit16128 to 512 K64 to 8 K 2 to 64bit6.Clock synchronous delay line memory (2 addresses, 1W/1R)Column type Memory capacity Word range Bit range Unit 8512 to 32 K32 to 1 K16 to 32bit16512 to 32 K64 to 2 K8 to 16bit32512 to 32 K128 to 4 K 4 to 8bit7.Clock synchronous FIFO memory (2 addresses, 1W/1R)Column type Memory capacity Word range Bit range Unit 8512 to 32 K32 to 1 K16 to 32bit16512 to 32 K64 to 2 K8 to 16bit32512 to 32 K128 to 4 K 4 to 8bit5CE77 Series6■ABSOLUTE MAXIMUM RATINGS*1 : V SS= 0 V*2 : Maximum output current which can be supplied constantly.*3 : Maximum supply current which can be supplied constantly.*4 : Internal gate part in case of single power supply or dual power supply.*5 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply.WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.Parameter Symbol ApplicationRatingUnitMin MaxPower supply voltage*1V DDV DD= 1.4 V to 2.7 V− 0.5+3.0*4VV DD= 2.7 V to 3.6 V+4.0*5Input voltage*1V I⎯− 0.5V DD+ 0.5 ( ≤ 3.0 V) *4VV DD+ 0.5 ( ≤ 4.0 V) *5 Output voltage*1V O⎯− 0.5V DD+ 0.5 ( ≤ 3.0 V) *4VV DD+ 0.5 ( ≤ 4.0 V) *5 Storage temperature Tst⎯−55+125°C Junction temperature Tj⎯−40+125°COutput current*2L typeI OPowerless type(I OL= 2 mA)⎯±13mA M typeNormal type(I OL= 4 mA)⎯±13H typePower type(I OL= 8 mA)⎯±13V typeHigh power type(I OL= 12 mA)⎯±26Power-supply pin current*3I D Per V DD, GND pin⎯60mACE77 Series7■RECOMMENDED OPERATING CONDITIONS1.Single power supply• Conditions: V DD = 2.5 V ±0.2 V , V SS = 0 V• Conditions: V DD = 1.8 V ±0.15 V , V SS = 0 V• Conditions: V DD = 1.5 V ±0.1 V , V SS = 0 VParameterSymbol ValueUnit Min Typ Max Power supply voltage V DD 2.3 2.5 2.7V “H” level input voltage CMOS normal V IH 1.7⎯V DD + 0.3V CMOS schmitt V DD × 0.8“L” level input voltage CMOS normal V IL −0.3⎯+0.7V CMOS schmittV DD × 0.2Junction temperatureT j−40⎯+125°CParameterSymbol ValueUnit Min Typ Max Power supply voltage V DDI 1.65 1.8 1.95V “H” level input voltage CMOS normal V IH V DD × 0.65⎯V DD + 0.3V CMOS schmitt V DD × 0.8“L” level input voltage CMOS normal V IL −0.3⎯V DD × 0.35V CMOS schmittV DD × 0.2Junction temperatureT j−40⎯+125°CParameterSymbol ValueUnit Min Typ Max Power supply voltage V DDI 1.4 1.5 1.6V “H” level input voltage CMOS normal V IH V DD × 0.7⎯V DD + 0.3V CMOS schmitt V DD × 0.8“L” level input voltage CMOS normal V IL −0.3⎯V DD × 0.3V CMOS schmittV DD × 0.2Junction temperatureT j−40⎯+125°CCE77 Series82.Dual power supply• Conditions: V DDE=3.3 V±0.3 V/V DDI=2.5 V±0.2 V, V DDI=1.8 V±0.15 V, V DDI=1.5 V±0.1 V, V SS=0 V Parameter SymbolValueUnitMin Typ MaxPower supply voltageV DDE 3.0 3.3 3.6VV DDI 1.4⎯ 2.7“H” level input voltage1.5 V CMOS normalV IHV DDI× 0.7⎯V DDI+ 0.3V1.8 V CMOS normal V DDI× 0.652.5 V CMOS normal 1.73.3 V CMOS normal 2.0V DDE+ 0.31.5 V CMOS schmittV DDI× 0.8V DDI+ 0.31.8 V CMOS schmitt2.5 V CMOS schmitt3.3 V CMOS schmitt V DDE× 0.8V DDE+ 0.35 V Tolerant 2.0 5.5“L” level input voltage1.5 V CMOS normalV IL−0.3⎯V DDI× 0.3V1.8 V CMOS normal V DDI× 0.352.5 V CMOS normal+ 0.73.3 V CMOS normal+ 0.81.5 V CMOS schmittV DDI× 0.21.8 V CMOS schmitt2.5 V CMOS schmitt3.3 V CMOS schmitt V DDE× 0.25 V Tolerant+ 0.8Junction temperature T j−40⎯+125°CCE77 Series9• Conditions: V DDE = 2.5 V ±0.2 V /V DDI = 1.8 V ±0.15 V , V DDI = 1.5 V ±0.1 V , V SS = 0 VWARNING:The recommended operating conditions are required in order to ensure the normal operation of thesemiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.Parameter SymbolValueUnit Min Typ Max Power supply voltageV DDE 2.3 2.5 2.7VV DDI1.4⎯1.95“H” level input voltage1.5 V CMOS normal V IH V DDI × 0.7⎯V DDI + 0.3V1.8 V CMOS normalV DDI × 0.652.5 V CMOS normal 1.7V DDE + 0.31.5 V CMOS schmitt V DDI × 0.8V DDI + 0.31.8 V CMOS schmitt 2.5 V CMOS schmitt V DDE × 0.8V DDE + 0.3“L” level input voltage1.5 V CMOS normal V IL−0.3⎯V DDI × 0.3V1.8 V CMOS normalV DDI × 0.352.5 V CMOS normal 0.71.5 V CMOS schmitt V DDI × 0.21.8 V CMOS schmitt 2.5 V CMOS schmittV DDE × 0.2Junction temperatureT j−40⎯+125°CCE77 Series10■DC CHARACTERISTICS•Single power supply : V DD=2.5 V (Standard)*1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are V IH= V DD, V IL= V SS, and T j=+25 °C. The above values may not be guaranteed when the input buffer witha pull-up/pull-down resistor or a crystal oscillator buffer is used.*2 : Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS.(V DD= 2.5 V ± 0.2 V, V SS= 0 V, T j=−40 °C to +125 °C) Parameter Symbol ConditionsValueUnitMin Typ MaxPower supply current*1I DDST2⎯⎯0.1mAT3, T4⎯⎯0.2T5 to T7⎯⎯0.3T8, T9⎯⎯0.4TA⎯⎯0.5TB, TC⎯⎯0.6TD⎯⎯0.8TE⎯⎯ 1.0TF⎯⎯ 1.1TG⎯⎯ 1.3“H” level output voltage V OH I OH=−100 µA V DD− 0.2⎯V DD V “L” level output voltage V OL I OL= 100 µA0⎯0.2V “H” level output voltageV-I characteristics⎯ 2.5 V V DD= 2.5 V±0.2 V*2⎯⎯⎯“L” level output currentV-I characteristics⎯ 2.5 V V DD= 2.5 V±0.2 V*2⎯⎯⎯Input leakage current I L⎯⎯⎯±5µA Pull-up/pull-downresistanceR PPull-up V IL= 0 VPull-down V IH= V DD1025120kΩ•Single power supply : V DD = 1.8 V *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditionsare V IH = V DD , V IL = V SS , and T j = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used.*2 : Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS.(V DD = 1.8 V ± 0.15 V, V SS = 0 V, T j = −40 °C to +125 °C)ParameterSymbolConditionsValueUnitMin Typ Max Power supply current*1I DDST2⎯⎯0.1mA T3, T4⎯⎯0.2T5 to T7⎯⎯0.3T8, T9⎯⎯0.4TA ⎯⎯0.5TB, TC ⎯⎯0.6TD ⎯⎯0.8TE ⎯⎯ 1.0TF ⎯⎯ 1.1TG⎯⎯ 1.3“H” level output voltage V OH I OH = −100 µA V DD − 0.2⎯V DD V “L” level output voltage V OL I OL = 100 µA0⎯0.2V “H” level output voltage V-I characteristics ⎯ 1.8 V V DD = 1.8 V ±0.15 V *2⎯⎯⎯“L” level output current V-I characteristics ⎯ 1.8 V V DD = 1.8 V ±0.15 V*2⎯⎯⎯Input leakage current I L ⎯⎯⎯±5µA Pull-up/pull-down resistanceR PPull-up V IL = 0 V Pull-down V IH = V DD1040120k Ω•Single power supply : V DD = 1.5 V *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditionsare V IH = V DD , V IL = V SS , and T j = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used.*2 : Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS.(V DD = 1.5 V ± 0.1 V, V SS = 0 V, T j = −40 °C to +125 °C)ParameterSymbolConditionsValueUnitMin Typ Max Power supply current*1I DDST2⎯⎯0.1mA T3, T4⎯⎯0.2T5 to T7⎯⎯0.3T8, T9⎯⎯0.4TA ⎯⎯0.5TB, TC ⎯⎯0.6TD ⎯⎯0.8TE ⎯⎯ 1.0TF ⎯⎯ 1.1TG⎯⎯ 1.3“H” level output voltage V OH I OH = −100 µA V DD − 0.2⎯V DD V “L” level output voltage V OL I OL = 100 µA0⎯0.2V “H” level output voltage V-I characteristics ⎯ 1.5 V V DD = 1.5 V ±0.1 V *2⎯⎯⎯“L” level output current V-I characteristics ⎯ 1.5 V V DD = 1.5 V ±0.1 V*2⎯⎯⎯Input leakage current I L ⎯⎯⎯±5µA Pull-up/pull-down resistanceR PPull-up V IL = 0 V Pull-down V IH = V DD1055120k Ω•Dual power supply : V DDE = 3.3 V /V DDI = 2.5 V , 1.8 V , 1.5 V*1:When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are V IH = V DD , V IL = V SS , and T j = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used.*2:Refer to “(1) 3.3 V” in ■ V-I CHARACTERISTICS.*3:Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS.*4:Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“.*5:Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS.(V DDE = 3.3 V ± 0.3 V/V DDI = 2.5 V ±0.2 V, 1.8 V ± 0.15 V, 1.5 V ±0.1 V, V SS = 0 V, T j = −40 °C to +125 °C)ParameterSymbolConditionsValueUnitMin Typ Max Power supply current*1I DDST2⎯⎯0.1mA T3, T4⎯⎯0.2T5 to T7⎯⎯0.3T8, T9⎯⎯0.4TA ⎯⎯0.5TB, TC ⎯⎯0.6TD ⎯⎯0.8TE ⎯⎯ 1.0TF ⎯⎯ 1.1TG⎯⎯ 1.3“H” level output voltageV OH43.3 V output I OH = −100 µA V DDE − 0.2⎯V DDE V V OH3 2.5 V output I OH = −100 µA V DDI − 0.2⎯V DDI V OH2 1.8 V output I OH = −100 µA V DDI − 0.2⎯V DDI V OH1 1.5 V output I OH = −100 µA V DDI − 0.2⎯V DDI “L” level output voltageV OL43.3 V output I OL = 100 µA 0⎯0.2V V OL3 2.5 V output I OL = 100 µA 0⎯0.2V OL2 1.8 V output I OL = 100 µA 0⎯0.2V OL1 1.5 V output I OL = 100 µA 0⎯0.2“H” level output V-I characteristics⎯3.3 V V DDE = 3.3 V ±0.3 V *2⎯⎯⎯⎯ 2.5 V V DDI = 2.5 V ±0.2 V *3⎯⎯⎯ 1.8 V V DDE = 1.8 V ±0.15 V *4⎯⎯⎯ 1.5 V V DDI = 1.5 V ±0.1 V *5⎯⎯“L” level output V-I characteristics ⎯3.3 V V DDE = 3.3 V ±0.3 V *2⎯⎯⎯⎯ 2.5 V V DDI = 2.5 V ±0.2 V *3⎯⎯⎯ 1.8 V V DDE = 1.8 V ±0.15 V *4⎯⎯⎯ 1.5 V V DDI = 1.5 V ±0.1 V*5⎯⎯Input leakage currentI L⎯⎯⎯±5µA Pull-up/pull-down resistanceR P3.3 VPull-up V IL = 0Pull-down V IH = V DDE 102570k Ω2.5 VPull-up V IL = 0Pull-down V IH = V DDI 10251201.8 V Pull-up V IL = 0Pull-down V IH = V DDI 10401201.5 VPull-up V IL = 0Pull-down V IH = V DDI 1055120•Dual power supply : V DDE = 2.5 V /V DDI = 2.5 V , 1.8 V , 1.5 V*1:When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are V IH = V DD , V IL = V SS , and T j = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used.*2:Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS.*3:Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“.*4:Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS.(V DDE = 2.5 V ± 0.2 V/V DDI = 1.8 V ±0.15 V, 1.5 V ± 0.1 V, V SS = 0 V, T j = −40 °C to +125 °C)ParameterSymbolConditionsValueUnitMin Typ Max Power supply current*1I DDST2⎯⎯0.1mA T3, T4⎯⎯0.2T5 to T7⎯⎯0.3T8, T9⎯⎯0.4TA ⎯⎯0.5TB, TC ⎯⎯0.6TD ⎯⎯0.8TE ⎯⎯ 1.0TF ⎯⎯ 1.1TG⎯⎯ 1.3“H” level output voltageV OH32.5 V output I OH = −100 µA V DDE − 0.2⎯V DDE V V OH2 1.8 V output I OH = −100 µA V DDI − 0.2⎯V DDI V OH1 1.5 V output I OH = −100 µA V DDI − 0.2⎯V DDI “L” level output voltageV OL32.5 V output I OL = 100 µA 0⎯0.2V V OL2 1.8 V output I OL = 100 µA 0⎯0.2V OL11.5 V output I OL = 100 µA 0⎯0.2“H” level output V-I characteristics⎯ 2.5 V V DDE = 2.5 V ±0.2 V *2⎯⎯⎯⎯ 1.8 V V DDI = 1.8 V ±0.15 V *3⎯⎯⎯ 1.5 V V DDI = 1.5 V ±0.1 V *4⎯⎯“L” level output V-I characteristics ⎯ 2.5 V V DDE = 2.5 V ±0.2 V *2⎯⎯⎯⎯ 1.8 V V DDI = 1.8 V ±0.15 V *3⎯⎯⎯ 1.5 V V DDI = 1.5 V ±0.1 V*4⎯⎯Input leakage currentI L⎯⎯⎯±5µA Pull-up/pull-down resistanceR P2.5 VPull-up V IL = 0Pull-down V IH = V DDE 1025120k Ω1.8 V Pull-up V IL = 0Pull-down V IH = V DDI 10401201.5 VPull-up V IL = 0Pull-down V IH = V DDI 1055120■V-I CHARACTERISTICS (1) 3.3 V(2) 2.5 V(3) 1.8 V(4) 1.5 V■AC CHARACTERISTICS*1 : Delay time = propagation delay time, enable time, disable time *2 : “typ” is calculated from the cell specification.*3 : Measurement conditionNote : tpd Max is calculated according to the maximum junction temperature (T j ) .■ INPUT/OUTPUT CAPACITANCE■DESIGN METHODLinking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan infor-mation. In addition, CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information is also available. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time.(V DD = 1.8 V ± 0.15 V, V SS = 0 V, T j = −40 °C to +125 °C)ParameterSymbol ValueUnit Min Typ Max Delay timet pd *1typ*2 × tmin*3typ*2 × ttyp*3typ*2 × tmax*3nsMeasurement condition tmin ttyp tmax V DD = 2.5V ± 0.2 V, V SS = 0 V, T j = −40 °C to +125 °C 0.60 1.00 1.64V DD = 1.8V ± 0.15 V, V SS = 0 V, T j = −40 °C to +125 °C 0.84 1.57 2.84V DD = 1.5V ± 0.1 V, V SS = 0 V, T j = −40 °C to +125 °C1.142.224.09(f = 1 MHz, V DD = V I = 0 V, Tj = +25 °C)ParameterSymbol Value Unit Input pin C IN Max 16pF Output pinC OUT Max 16pF Input/output capacitanceC I /OMax 16pF■THE NUMBER OF GATES USED AND PACKAGES1.Counting the number of the gates usedEvaluation of the basic cell count used has revealed some problems including the circuit complexities, difference of the utilization depending on the circuit design scheme (whether it is designed with the logic synthesis) or being unable to achieve the minimum layout with the logically synthesized circuit.To cope with those problems, Fujitsu developed the AREA as a criteria where the circuit size and the layout feasibility is determined. The AREA is a basic cell conceived from the viewpoint of congestion of the wiring; it has been calculated from the actual basic cell count and pin count in units of BC.Estimate method for the frame include the conventional one by the basic cell count and the one by the AREA for more detailed estimate.Hard macro basic cell count and AREA count for unit cell, I/O buffer cell or compiled cell are listed in the respective cell characteristic table.2.PackagesThe table below lists the package types available and the reference number of gates used.Consult Fujitsu for the combination of each package and the availability.CE77 (V-FRAME)Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu.CE77 (T-FRAME)Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu.21(Continued) 2223FUJITSU LIMITEDAll Rights Reserved.The contents of this document are subject to change without notice.Customers are advised toc onsult with FUJITSU salesrepresentatives before ordering.The information, such as descriptions of function and applicationc irc uit examples, in this doc ument are presented solely for thepurpose of reference to show examples of operations and uses ofFujitsu semic onduc tor devic e; Fujitsu does not warrant properoperation of the devic e with respec t to use based on suc hinformation. When you develop equipment inc orporating thedevi e based on su h information, you must assume anyresponsibility arising out of suc h use of the information. Fujitsuassumes no liability for any damages whatsoever arising out ofthe use of the information.Any information in this doc ument, inc luding desc riptions offunction and schematic diagrams, shall not be construed as licenseof the use or exerc ise of any intellec tual property right, suc h aspatent right or copyright, or any other right of Fujitsu or any thirdparty or does Fujitsu warrant non-infringement of any third-party’sintellectual property right or other right by using such information.Fujitsu assumes no liability for any infringement of the intellectualproperty rights or other rights of third parties which would resultfrom the use of information contained herein.The products described in this document are designed, developedand manufac tured as c ontemplated for general use, inc ludingwithout limitation, ordinary industrial use, general offic e use,personal use, and household use, but are not designed, developedand manufactured as contemplated (1) for use accompanying fatalrisks or dangers that, unless extremely high safety is secured, couldhave a serious effect to the public, and could lead directly to death,personal injury, severe physical damage or other loss (i.e., nuclearreaction control in nuclear facility, aircraft flight control, air trafficcontrol, mass transport control, medical life support system, missilelaunc h c ontrol in weapon system), or (2) for use requiringextremely high reliability (i.e., submersible repeater and artificialsatellite).Please note that Fujitsu will not be liable against you and/or anythird party for any claims or damages arising in connection withabove-mentioned uses of the products.Any semiconductor devices have an inherent chance of failure. Youmust protect against injury, damage or loss from such failures byinc orporating safety design measures into your fac ility andequipment such as redundancy, fire protection, and prevention ofover-current levels and other abnormal operating conditions.If any produc ts desc ribed in this doc ument represent goods ortec hnologies subjec t to c ertain restric tions on export under theForeign Exc hange and Foreign Trade Law of Japan, the priorauthorization by Japanese government will be required for exportof those products from Japan.The company names and brand names herein are the trademarks orregistered trademarks of their respective owners.Edited Business Promotion Dept.F0701。
High-speed, current driven latch
专利名称:High-speed, current driven latch发明人:Karl Edwards申请号:US10761753申请日:20040120公开号:US07176736B2公开日:20070213专利内容由知识产权出版社提供专利附图:摘要:A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change theoutput of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.申请人:Karl Edwards地址:San Jose CA US国籍:US代理机构:Fish & Neave IP Group, Ropes & Gray LLP代理人:Jeffrey C. Aldridge更多信息请下载全文后查看。
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I.
INTRODUCTION
In analog-to-digital converters CADCs) the comparator plays a crucial role on the overall performance. An accurate and fast comparator is a key element in high-resolution and high speed data converter. Such ADCs are widely used in many applications such as data storage systems, fast serial links and high speed measurement systems. There are several most popular structures of high speed comparators like multistage open loop comparator, the regenerative latch comparator and the preamplifier latch comparator. Among all these comparators, the multistage open loop comparator can obtain high speed and good resolution easily. A common architecture used in analog circuits is the dynamic latch. It is widely used to satisfy the need for high speed and low power consumption. It has proven to have an excellent speed while maintaining an acceptable accuracy. The circuits presented in this paper are taken from [2] and [3] are dynamic latch comparator using preamplifier and dynamic latch with inverter buffer. In preamplifier latched topology an amplifier is added before a latched comparator which significantly decreases the effects of the offset voltage errors caused by device mismatch. Transmission gates are used between preamplifier and latch to control the signal path and to provide high gain to the output signal of the amplifier using charge injection phenomenon. The major disadvantages of dynamic latch are the kickback noise [5] produced by high transmission currents which induces spikes at the differential input voltage signal and the offset error caused due to the device mismatch. In buffered latch comparator inverter buffers are added to the output of the dynamic latch comparator to isolate the comparator output from large capacitive loads.
II.
METHODOLOGY
A.
Preamp the block diagram of comparator. Preamplifier latch
circuit consists of a preamplifier followed by a double regenerative dynamic latch, this preamplifier uses fully differential circuit which decreases the effects of offset voltage error due to device mismatch. The basic principle of preamplifier is that the preamplifiers amplify the input signal and is fed to the input of dynamic latch comparator using transmission gates. The preamplifier comparator has low propagation delay as compared to the latch comparator. Fig. 2 shows the preamplifier based comparator. The preamplifier based comparator [7] consists of three stages: the input preamplifier stage, a latch stage, and an output buffer stage. The preamplifier is basically a self-biased differential amplifier with active loads.
I
MI�
LATCHSTAG[
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Figure 2. Preamplifier based comparator
The Preamplifier stage amplifies the input signal to improve the comparator sensitivity and isolates the input of the comparator from switching noise coming from the positive feedback stage. It also can reduce input referred latch offset voltage. The sizes of MI and M2 are set by considering the diff-amp transconductance and the input capacitance. The transconductance sets the gain of the stage, while the size of MI and M2 determines the input capacitance of the comparator. The positive feedback latch stage is used to determine which of the input signals is larger and extremely amplifies their difference. The output buffer, the final component of our comparator, converts the output of the latch stage into a full scale digital level output (logic 0 or logic 1). The output buffer should accept a differential input signal and not have slew-rate limitations. The circuit of the output buffer is basically a self biased differential amplifier followed by an inverter. The inverter is added as a separate additional gain stage and isolates any load capacitance from differential amplifier [10]. In
HIGH-SPEED AND LOW-POWER DYNAMIC LATCH COMPARATOR
D. lackuline Moni and P. lisha Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamil Nadu, India
Mail id: jishamanimandir@
Abstract-This paper presents the comparison between the CMOS dynamic latch comparators. High speed and low power comparators are essential building blocks of high speed analog to digital converters (ADCs). The comparator circuit take for study are dynamic latch comparator using preamplifier and dynamic latch with inverter buffer. Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch, this preamplifier uses fully differential circuit which decreases the effects of offset voltage error due to device mismatch. Buffered dynamic latch circuit includes a basic dynamic latch comparator followed by an inverter buffer stage. The inverter buffers are added to isolate the comparator output and large node capacitance also used to minimize the offset errors. The circuit using SPICE tool with O.18um technology and the supply voltage used 1.8V.