如何读单片机的时序图

/itangcleCPE/EE 421MicrocomputersWEEK #10Interpreting the Timing Diagram如何读懂时序图The 68000 Read Cycle2 Timing Diagram of a Simple Flip-F lopIdealized form of the timing diagramActual behavior of a D flip-f lopData hold timeData setup timeMax time for output tobecome valid after clockAlan Clements 3 General form of the timing diagramAn alternative form of the timing diagram4The Clock•A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations一个微处理器需要时钟,提供一系列的计时脉冲来控制它的内部操作•A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7一个6800芯片的储存器最小能过接收8个从S0到S7的时钟脉冲.6A memory access begins in clockstate S0 and ends in state S7Alan Clements Alan Clements 7The most important parameterof the clock is the duration of a cycle,t C YC .Alan Clements 8Address Timing地址时序•We are interested in when the 68000 generates a new address for use in the current memory access我们感兴趣的是当6800芯片能够生成一个新的地址供当前的内存访问•The next slide shows the relationship between the new address and the state of the 68000 ’s clock下面展示的是新的地址跟6800芯片时钟的关系1:S0在没有初始化的时候，地址总线总是包涵新的地址。

2： S1这个状态说明一个新的地址可以供内存访问Alan ClementsAddress Timing地址时序•Let’s look at the sequence of events that govern the timing of the address bus让我们看看事件发生的顺序,管理时间的地址总线•The “old” address is removed in state S0旧的地址已经从S0中移除•The address bus is floated for a short time, and the CPU puts out a new address in state S1地址要先存在一小段时间后，CPU才能把心的地址状态写入S1中12Alan ClementsAlan Clements Alan Clements 13The old address is removedin clock state S0 and theaddress bus floatedAlan Clements我们感兴趣的是地址生效的那个时间点。

这个时间是在S0失效后，t CLA V 秒后。

t C LA VThe designer is interested in the point atwhich the address first becomes valid. Thispoint is t C LA V seconds after the falling edgeof S0.Address and Address Strobe地址跟地址选通•We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted我们感兴趣的事在地址总线能够访问时，地址选通是否有效。

•When AS* is active-low it indicates that the address is valid当AS*低电平有效时地址才是有效的。

Alan Clements上图说明：1：当地址有效的时候把AS 低电平信号.2：当地址要改变前，要把AS变成高电平•We now look at the timing of the clock, the address, and the address strobe从上面的时序图可以看出到，时钟脉冲，地址信号，片选脉冲；3者的关系。

16Alan Clements17Alan ClementsAlan Clements当AS变成低电平的时候，时钟脉冲在S2处AS* goes low in clockstate S2The Data Strobes 数据选通•The 68000 has two data strobes LDS* and UDS*. These select the lower byte or the upper byte of a word during a memory access6800芯片有两个数据选通信号LDS（低）和UDS（高）.内存通过选择LDS和UDS来访问数据。

•To keep things simple, we will use a single data strobe, DS* 为了让事情看起来简单，我们只要选通DS就可以了。

（DS的高8位是UDS低8位是LDS）•The timing of DS* in a read cycle is the same as the address strobe, AS*DS的读数据跟AS读地址的时序是一样的。

Alan Clements19Alan ClementsAlan ClementsThe Data Bus 数据总线•During a read cycle the memory provides the CPU with data当读数据期间，内存给CPU提供数据•The next slide shows the data bus and the timing of the data signal .上图显示了数据总线跟数据的关系•Note that valid data does not appear on the data bus until near the end of the read cycle 注意到可访问的数据没有出现在数据总线，直到读完数据。

20The data strobe, is assertedat the same time as AS*in a read cycleAlan Clements Alan Clements21Analyzing the Timing Diagram分析时序图•We are going to redraw the timing diagram to remove clutter让我们从头到脚分析这个时序图让头脑不那么乱•We aren’t interested in the signal paths themselves, only in the relationship between the signals 我们不能单单从一条信号线来分析了，我们得从整体上来分析。

我们感兴趣的是时钟脉冲,AS/DS(地址选通/数据选通)和数据在读周期Alan Clements在地址开始有效的时候，内存就可以访问数据了。

Alan ClementsAlan ClementsCalculating the Access Time计算访问时间• We need to calculate the memory’s access time 我们必须计算内存的访问时间• By knowing the access time, we can use the appropriate memory component 通过了解访问时间，我们可以适当使用内存• Equally, if we select a given memory component, we can calculate whether its access time is adequate for a particular system 同样,如果我们选择一个特定内存组件,我们可以计算出它的访问时间是否足够用来在一个特定的系统Alan Clements 2728Alan Clements在t DICL 后，数据必须有效。

Alan Clements我们知道在地址和数据可以访问的时候之间的时间是t acc 秒Alan Clements地址数据在t CLA V 后能被访问Alan Clements在地址有效，从S0到S6结束，数据就别俘获了。

Alan ClementsAlan Clements 3334Timing Example•68000 clock 8 MHz t CYC = 125 ns •68000 CPU t CLA V = 70 ns•68000 CPU t DICL = 15 ns•What is the minimum t acc?•3 t CYC = t CLA V + t acc + t DICL•375 = 70 + t acc + 15•t acc = 290 nsAlan Clements35。