EDA课程设计——基于DDS的正弦信号发生器设计
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顶层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END ENTITY DDS;
ARCHITECTURE BEHA VE OF DDS IS
COMPONENT SUM99 IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
CLK:IN STD_LOGIC;
OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT SUM99;
COMPONENT REG1 IS
PORT(D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT REG1;
COMPONENT ROM IS
PORT(CLK:IN STD_LOGIC;
ADDR:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
OUTP:OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END COMPONENT ROM;
COMPONENT REG2 IS
PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT REG2;
SIGNAL S1:STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S2:STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL S3:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
U0:SUM99 PORT MAP(K=>K,EN=>EN,RESET=>RESET,CLK=>CLK,OUT1=>S1); U1:REG1 PORT MAP(D=>S1,CLK=>CLK,Q=>S1);
U2:ROM PORT MAP(ADDR=>S2,CLK=>CLK,OUTP=>S3);
U3:REG2 PORT MAP(D=>S3,CLK=>CLK,Q=>Q);
END ARCHITECTURE BEHA VE;
正弦查找表
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM IS
PORT (ADDR:IN STD_LOGIC_VECTOR(6 DOWNTO 0); CLK:IN STD_LOGIC;
OUTP:OUT SIGNED(7 DOWNTO 0));
END ENTITY ROM;
ARCHITECTURE ART OF ROM IS
BEGIN
PROCESS(CLK)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
CASE ADDR IS
WHEN "0000000"=>OUTP<="00000000";
WHEN "0000001"=>OUTP<="00000010";
WHEN "0000010"=>OUTP<="00000011";
WHEN "0000011"=>OUTP<="00000101";
WHEN "0000100"=>OUTP<="00000110";
WHEN "0000110"=>OUTP<="00001001"; WHEN "0000111"=>OUTP<="00001011"; WHEN "0001000"=>OUTP<=”00001101"; WHEN "0001001"=>OUTP<="00001110"; WHEN "0001010"=>OUTP<="00010000"; WHEN "0001011"=>OUTP<="00010001"; WHEN "0001100"=>OUTP<="00010011"; WHEN "0001101"=>OUTP<="00010100"; WHEN "0001110"=>OUTP<="00010110"; WHEN "0001111"=>OUTP<="00010111"; WHEN "0010000"=>OUTP<="00011001"; WHEN "0010001"=>OUTP<="00011011";
WHEN "0010010"=>OUTP<="00011100"; WHEN "0010011"=>OUTP<="00011110"; WHEN "0010100"=>OUTP<="00011111"; WHEN "0010101"=>OUTP<="00100001"; WHEN "0010110"=>OUTP<="00100010"; WHEN "0010111"=>OUTP<="00100100"; WHEN "0011000"=>OUTP<="00100101"; WHEN "0011001"=>OUTP<="00100111";