设计一四位计数器
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
学院：信息技术学院班级：
专业：电子信息科学与技术姓名：
日期：学号：
1、熟悉行为级语法；
2、熟悉有限状态机
设计一四位计数器，进行仿真，并检测输出结果；
提示：在时钟上升沿，如果复位信号有效，则复位为0,如果复位信号无效，则计数器需要加一。
完成一个序列信号电路检测器，检测信号为10010，当检测到此序列时输出端口输出高电平，其余时间输出低电平。
提示：先画出状态转换图或写出状态转换表，根据状态表或者状态图完成代码的设计；
编写测试模块对该功能模块进行仿真。要求实验报告包括完整的状态转化图或者转化表。
序列信号电路检测器：
module mian (z, x, clock, clear);
output z;
reg z;
input clock, clear;
input x;
parameter s0 = 3'd0,
s1 = 3'd1,
s2 = 3'd2,
s3 = 3'd3,
s5 = 3'd5,
s4 = 3'd4;
reg [2:0] state;
reg [2:0] next_state;
always @(posedge clock) if(clear)
state <= s0;
else
state <= next_state;
always @(state)
begin
case(state)
s0: show = 0;
s1: show = 0;
s2: show = 0;
s3: show = 0;
s4: show = 0;
s5: show = 1; endcase
end
always @(x or state) begin
case(state)
s0: if(x == 0)
next_state = s0;
else
next_state = s1;
s1: if(x == 0)
next_state = s2;
else
next_state = s1;
s2: if(x == 0)
next_state = s3;
else
next_state = s1;
s3: if(x == 0)
next_state = s0;
else
next_state = s4;
s4: if(x == 0)
next_state = s5;
else
next_state = s1;
s5: if(x == 0)
next_state = s0;
else
next_state = s1;
endcase
end
endmodule
module stimulus_mv;
wire z;
reg x;
reg clock, clear; mianMVP(z, x, clock, clear);
initial
begin clock = 0;
forever #5 clock = ~clock;
end
initial
begin
clear = 1;
repeat(2)@(negedge clock);
clear = 0;
end
initial
begin
#30 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 0;
end
endmodule
1.输出：
四位计数器
3.1功能块代码
module counter(out, clock, clear);
output out;
input clock, clear;
reg [3:0] out;
always @(posedge clock or negedge clear) begin
if(clear)
out <= 4'd0;
else
out <= out + 1;
end
endmodule
3.2测试模块代码
module counter_stimulus;
reg clock, clear;
wire [3:0] out;
initial
$monitor($time, "count = %b , clear = %b", out[3:0], clear); counter MVP(out, clock, clear);
always
begin
clear = 1'b1;
#15 clear = 1'b0;
#200 clear = 1'b1;
#50 clear = 1'b1;
end
initial
begin
clock = 1'b0;
forever #5 clock = ~clock;
end
initial
begin
#400 $Finish;
end
endmodule