杭电计组实验报告9

Inst_Fetch1 inst_fetch(
.rst(rst),
.clk(clk),
.Inst_codes(codes)
);
wire[5:0] OP;
wire[5:0] func;
wire[2:0] ALU_OP;
wire rd_rt_s;
wire imm_s;
wire rt_imm_s;
wire alu_mem_s;
);
wire [31:0]ALU_A;
wire [31:0]ALU_B;
assign ALU_A = R_Data_A;
assign ALU_B = (rt_imm_s)?imm_data:R_Data_B;
ALU alu(
.ALU_OP(ALU_OP),
.A(ALU_A),
.B(ALU_B),
.F(ALU_F),
wire Write_Reg;
wire Mem_Write;
wire [15:0]Fra Baidu bibliotekimm;
wire [31:0] imm_data ;
assign imm_data = (imm_s)?{{16{imm[15]}},imm}:{{16{1'b0}},imm};
assign OP = codes[31:26];
Top uut (
.inclk(inclk),
.mem_clk(mem_clk),
.rst(rst),
.LED(LED),
.SW(SW)
);
reg [2:0] i;
initial begin
// Initialize Inputs
inclk = 0;
mem_clk = 0;
rst = 0;
SW = 0;
NET "LED[5]" LOC = "N11";
NET "LED[4]" LOC = "M11";
NET "LED[3]" LOC = "V15";
NET "LED[2]" LOC = "U15";
NET "LED[1]" LOC = "V16";
NET "LED[0]" LOC = "U16";//LED
.rt_imm_s(rt_imm_s),
.alu_mem_s(alu_mem_s),
.Write_Reg(Write_Reg),
.Mem_Write(Mem_Write)
);
wire[4:0] rs;
wire[4:0] rt;
wire[4:0] rd;
assign rs = codes[25:21];
NET "rst" LOC = "D9";
五、思考与探索
2，给译码与控制单元增加一个控制信号，该信号在OP==6’b001111产生。在该信号的控制下，imm=imm<<16，即imm左移16位，地位补0，并将移位后的imm送入地址为rt的寄存器。由此便实现了该指令。
3，其实编写实验八的过程也就是将前面所有的实验进行一次应用和巩固的过程。当然了，在这个实验中同样涉及到了IP核的应用。
RegisterHeap register(
.R_Addr_A(rs),
.R_Addr_B(rt),
.W_Addr(W_Addr),
.Write_Reg(Write_Reg),
.Reset(rst),
.Clk(clk_n),
.W_Data(W_Data),
.R_Data_A(R_Data_A),
.R_Data_B(R_Data_B)
.ZF(ZF),
.OF(OF)
);
Data_Mem data_mem (
.clka(mem_clk), // input clka
.wea(Mem_Write), // input [0 : 0] wea
.addra(ALU_F), // input [5 : 0] addra
.dina(R_Data_B), // input [31 : 0] dina
NET "inclk" LOC = "C9";
NET "mem_clk" LOC = "V10";//100mHZ
NET "SW[3]" LOC = "M8";//右边4个开关
NET "SW[2]" LOC = "V9";
NET "SW[1]" LOC = "T9";
NET "SW[0]" LOC = "T10";
顶层模块代码：
module My_I_CPU(
input clk,
input mem_clk,
input rst,
output [31:0] ALU_F,
output [31:0] M_R_Data,
output ZF,
output OF
);
wire clk_n = ~clk;
wire[31:0] codes;
计组实验九
老师：包健
一、源代码
测试模块代码：
module Test_Top;
// Inputs
reg inclk;
reg mem_clk;
reg rst;
reg [3:0] SW;
// Outputs
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
i=0;
// Wait 100 ns for global reset to finish
#100;
rst = 1;
#100;
rst =0 ;
#100;
forever
begin
#100;
mem_clk=~mem_clk;
i=i+1;
if(i==3'b000)
inclk=~inclk;
end
end
endmodule
assign rt = codes[20:16];
assign rd = codes[15:11];
wire[4:0] W_Addr;
assign W_Addr=(rd_rt_s)?rt:rd;
wire [31:0]W_Data;
wire [31:0]R_Data_A;
wire [31:0]R_Data_B;
assign func = codes[5:0];
assign imm = codes[15:0];
OP_Decoder op_decoder(
.OP(OP),//input
.func(func),//input
.ALU_OP(ALU_OP),
.rd_rt_s(rd_rt_s),
.imm_s(imm_s),
.douta(M_R_Data) // output [31 : 0] douta
);
assign W_Data = (alu_mem_s)?M_R_Data:ALU_F;
endmodule
二、仿真波形
三、电路图
四、引脚配置
NET "LED[7]" LOC = "T11";
NET "LED[6]" LOC = "R11";