中山大学软件学院专业课计算机组成原理课件第4章.ppt
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memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches
Fetch cycle – micro-operations
Control bus Data bus Address
PC MAR Address Bus
Control Unit
The control unit (CU) is that portion of the processor that actually causes things to happen
The control unit issues control signals external to the processor to cause data exchange with memory and I/O modules
Flowchart for Instruction Cycle
Functional Requirements
The definition of control unit functional requirements is the basis for the design and implementation of the control unit
Review
• Characteristics of Memory System • Types of Memory • The Memory Hierarchy • Cache Memory • Virtual Memory
Main Content
• Micro-Operations • Control of the Processor • Hardwired Implementation • Microprogrammed Control
For execute cycle ➢ One sequence of micro-operations for each opcode
Need to tie sequences of micro-operations together, so, assume new 2-bit Instruction Cycle Code (ICC) register designates which part of cycle processor is in ➢00: Fetch ➢01: Indirect ➢10: Execute ➢11: Interrupt
Micro-Operations
Constituent Elements of Program Execution
Operation analysis
There are 4 processor cycle for the complementation of a instruction
The Fetch cycle The Indirect cycle The Execute cycle The Interrupt cycle
Memory Address Register (MAR) ➢ Connected to address bus ➢ Specifies address for read or write op
Memory Buffer Register (MBR) ➢ Connected to data bus ➢ Holds data to write or last data read
Instruction Cycle
Each phase of the instruction can be decomposed into a sequence of elementary micro-operations ➢ E.g. fetch, indirect, and interrupt cycles
The control unit issues control signals internal to the processor to move data between registers, to cause the ALU to perform a specified function, and to regulate other internal operations
The following three-step process leads to a characterization of the control unit:
➢ Define basic elements of processor ➢ Describe micro-operations that processor performs ➢ Determine the functions that the control unit must perform to cause the micro-operations to be performed
Micro-Operations
Programs are executed as a sequence of instructions
Each instruction consists of a series of steps that make up the instruction cycle -- fetch, decode, etc.
1R
(Control unit issues READ command)
CPU
Memory MBR
PC
MAR
MBR IR ( PC ) + 1 PC
CU +1 ALU
IR
MBR
Memory I/O
Rules for Clock Cycle Grouping
Proper sequence must be followed ➢ MAR <- (PC) must precede MBR <- (memory)
Indirect Cycle
(IR(Address)) MAR Address bus
1R
CPU
M ( MAR ) MBR
MAR
MBR IR(Address)
CU
IR
MBR
Control bus Data bus Address bus
Memory
Interrupt Cycle
At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred
Conflicts must be avoided ➢ Must not read & write same register at same time ➢ MBR <- (memory) & IR <- (MBR) must not be in same cycle
Also: PC <- (PC) +1 involves addition ➢ Use ALU ➢ May need additional micro-operations
Addressing modes
Registers
I/O module interface
Memory interface
module
Interrupt processing structure
CPU
PC
MAR
CU +1 ALU
IR
MBR
Memory I/O
Fetch - 4 Registers
Program Counter (PC) ➢ Holds address of next instruction to be fetched
Instruction Register (IR) ➢ Holds last instruction fetched
Fetch Sequence
Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from
Basic Elements of Processor
ALU – is the functional essence of CPU Registers – are used to store data or status
Each of these steps are, in turn, made up of a smaller series of steps called micro-operations
micro-operations are the functional, or atomic, operations of a processor
(IR(Address)) MAR
1
R (control bus)
Memory MBR
(MBR)+1 MBR
(MBR) → memory if (MBR) == 0 then (PC)+1→PC
Notes: ➢ The steps in red can be done simultaneously.
Only fetch and execute cycles always occurring
The things needed to specify the function of a processor
Control bus Data bus Address
Operations (opcode)
Execute Cycle
The fetch, indirect, and interrupt cycles are simple and predictable – each involves a small, fixed sequence of micro-operations
The execute cycle, different for each instruction Can be discussed in three types
The nature of interrupt cycle varies greatly from one machine to another
A simple sequence of events as follow ➢ MBR <-(PC) ➢ MAR <- save-address ➢ PC <- routine-address ➢ memory <- (MBR)
(IR(Address)) MAR
1
W (control bus)
ACC MBR
MBR Memory
3. Branch instruction
ISZ X – The content of location X is incremented by 1. If the result is 0, the next instruction is skipped.
➢ Instruction without memory access ➢ Instruction with memory access ➢ Branch instruction
1. Instruction without memory access
(1) CLA clean A 0 ACC
(2) COM complement ACC ACC
(3) STP halt
ቤተ መጻሕፍቲ ባይዱ0G
2. Instruction with memory access
(1) Add instruction ADD R1, X
(IR(Address)) MAR
1
R (control bus)
Memory MBR
(R1) + (MBR) R1
(2) Store data instruction STA X
Fetch cycle – micro-operations
Control bus Data bus Address
PC MAR Address Bus
Control Unit
The control unit (CU) is that portion of the processor that actually causes things to happen
The control unit issues control signals external to the processor to cause data exchange with memory and I/O modules
Flowchart for Instruction Cycle
Functional Requirements
The definition of control unit functional requirements is the basis for the design and implementation of the control unit
Review
• Characteristics of Memory System • Types of Memory • The Memory Hierarchy • Cache Memory • Virtual Memory
Main Content
• Micro-Operations • Control of the Processor • Hardwired Implementation • Microprogrammed Control
For execute cycle ➢ One sequence of micro-operations for each opcode
Need to tie sequences of micro-operations together, so, assume new 2-bit Instruction Cycle Code (ICC) register designates which part of cycle processor is in ➢00: Fetch ➢01: Indirect ➢10: Execute ➢11: Interrupt
Micro-Operations
Constituent Elements of Program Execution
Operation analysis
There are 4 processor cycle for the complementation of a instruction
The Fetch cycle The Indirect cycle The Execute cycle The Interrupt cycle
Memory Address Register (MAR) ➢ Connected to address bus ➢ Specifies address for read or write op
Memory Buffer Register (MBR) ➢ Connected to data bus ➢ Holds data to write or last data read
Instruction Cycle
Each phase of the instruction can be decomposed into a sequence of elementary micro-operations ➢ E.g. fetch, indirect, and interrupt cycles
The control unit issues control signals internal to the processor to move data between registers, to cause the ALU to perform a specified function, and to regulate other internal operations
The following three-step process leads to a characterization of the control unit:
➢ Define basic elements of processor ➢ Describe micro-operations that processor performs ➢ Determine the functions that the control unit must perform to cause the micro-operations to be performed
Micro-Operations
Programs are executed as a sequence of instructions
Each instruction consists of a series of steps that make up the instruction cycle -- fetch, decode, etc.
1R
(Control unit issues READ command)
CPU
Memory MBR
PC
MAR
MBR IR ( PC ) + 1 PC
CU +1 ALU
IR
MBR
Memory I/O
Rules for Clock Cycle Grouping
Proper sequence must be followed ➢ MAR <- (PC) must precede MBR <- (memory)
Indirect Cycle
(IR(Address)) MAR Address bus
1R
CPU
M ( MAR ) MBR
MAR
MBR IR(Address)
CU
IR
MBR
Control bus Data bus Address bus
Memory
Interrupt Cycle
At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred
Conflicts must be avoided ➢ Must not read & write same register at same time ➢ MBR <- (memory) & IR <- (MBR) must not be in same cycle
Also: PC <- (PC) +1 involves addition ➢ Use ALU ➢ May need additional micro-operations
Addressing modes
Registers
I/O module interface
Memory interface
module
Interrupt processing structure
CPU
PC
MAR
CU +1 ALU
IR
MBR
Memory I/O
Fetch - 4 Registers
Program Counter (PC) ➢ Holds address of next instruction to be fetched
Instruction Register (IR) ➢ Holds last instruction fetched
Fetch Sequence
Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from
Basic Elements of Processor
ALU – is the functional essence of CPU Registers – are used to store data or status
Each of these steps are, in turn, made up of a smaller series of steps called micro-operations
micro-operations are the functional, or atomic, operations of a processor
(IR(Address)) MAR
1
R (control bus)
Memory MBR
(MBR)+1 MBR
(MBR) → memory if (MBR) == 0 then (PC)+1→PC
Notes: ➢ The steps in red can be done simultaneously.
Only fetch and execute cycles always occurring
The things needed to specify the function of a processor
Control bus Data bus Address
Operations (opcode)
Execute Cycle
The fetch, indirect, and interrupt cycles are simple and predictable – each involves a small, fixed sequence of micro-operations
The execute cycle, different for each instruction Can be discussed in three types
The nature of interrupt cycle varies greatly from one machine to another
A simple sequence of events as follow ➢ MBR <-(PC) ➢ MAR <- save-address ➢ PC <- routine-address ➢ memory <- (MBR)
(IR(Address)) MAR
1
W (control bus)
ACC MBR
MBR Memory
3. Branch instruction
ISZ X – The content of location X is incremented by 1. If the result is 0, the next instruction is skipped.
➢ Instruction without memory access ➢ Instruction with memory access ➢ Branch instruction
1. Instruction without memory access
(1) CLA clean A 0 ACC
(2) COM complement ACC ACC
(3) STP halt
ቤተ መጻሕፍቲ ባይዱ0G
2. Instruction with memory access
(1) Add instruction ADD R1, X
(IR(Address)) MAR
1
R (control bus)
Memory MBR
(R1) + (MBR) R1
(2) Store data instruction STA X