FC封装基板简介

测试条件
288℃/10sec 10 Cycles -55℃～125℃ 2000 Cycles (Max. Temp.260℃)/10Cycles
判定依据
Micro-section E-test E-test
结果
Pass Pass Pass
Solder Dip 10 Cycles
Jiang Nan High Density Interconnection
3.8～4.2
ABF, Epoxy 3.2～3.4
Thickness (μm)
110±5
35±5 or 55±5
Impendance Control (Ω)
50±3.5
50±3.5
Overall Thickness (mm)
1.50
0.50
Jiang Nan High Density Interconnection
成本因子
-- Shorter processes setting -- High productivity and time saving -- Lower material cost
Jiang Nan High Density Interconnection
HDI Substrate
FCBGA Packaging Process
Thickness (μm) Min. Line /Space (μm) Height (μm) Min. Diameter (μm) Type Dielectric Constant
Substrate
Core
Build-up
--
20±4
--
35 /35
--
75～80
--
65
BT & Polyimide
-- More I/O
＝＞ More Heat
-- More gate
＝＞ More Heat
-- Increase gate density ＝＞ More Heat
-- Heat sink can directly attach to the die on a full array FCBGA
组装技术限制
应用
HDI Substrate
2+2+2 FC封装基板
Bump Pad (um) Bump Pitch (Area Array - um) Line Width/Space (um) Line Tolerance (+/-um) Solder Mask Window (um) SM Window Size Tolerance (+/-um) Solder Mask Registration (um) Copper pillar (um) Micro Via Land (um) Through Hole (Mechanical um) Through Hole Land (um)
150 176 25/25 4 90 10 20 65 100 150 250
Jiang Nan High Density Interconnection
应用
HDI Substrate
4+2+4 And 6+4+6 FC封装基板
Bump Pad (um) Bump Pitch (Area Array - um) Line Width/Space (um) Line Tolerance (+/-um) Solder Mask Window (um) SM Window Size Tolerance (+/-um) Solder Mask Registration (um) Copper pillar (um) Micro Via Land (um) Buried Hole (Mechanical um) Buried Hole Land (um)
Core材料
Solder Mask材料
ENIG, OSP 0.1um
0.015+0.005/-0.005 mm 0.025+/-0.005 mm 0.0175+/-0.005 mm 0.02mm (min)
ABF，Proprietary High Tg Resin 0.035~0.050 +/- 0.005 mm PI, BT, High Tg Epoxy Taiyo PSR4000 Taiyo High Tg Resin ABF
PCB与基板发展历程
HDI Substrate
Jiang Nan High Density Interconnection
T需ec求h与no技lo术gy驱D动rivers
CSP- Chip Scale Package/Chip Size Package
IC package area/ Si Chip (Die) area < 1.2 Micro BGA, uBGA
HDI Substrate
Jiang Nan High Density Interconnection
T需ec求h与no技lo术gy驱D动rive来自百度文库s
HDI Substrate
Flip Chip BGA Vs. Wire Bonding BGA
电性能
-- Shorter interconnection path -- Negligible interconnect inductance 热性能
HDI Substrate
【Note】 积层: 每面的L1-4层.
Jiang Nan High Density Interconnection
Pisa Tower 封装基板
技术能力
Substrate body size X 尺寸
15.0 to 45.0 +/- 0.1 mm
Substrate body size Y 尺寸
130 150 25/25
4 100 10 20 50 100 200 500
Jiang Nan High Density Interconnection
应用
4+10+4 MCM-L 基板
HDI Substrate
Feature Line Copper Pillar
Dielectric
Parameter
15.0 to 45.0 +/- 0.1 mm
Solder ball pad 节距
1.27mm, 1.00mm, 0.80mm
Ball pad 尺寸
0.50+/0.015mm (min)
Ball pad 阻焊开口
0.35+/-0.010mm (min)
Bump 节距
0.150mm (min)
Bump 尺寸
10% 0.200+/-0.025mm (min)
0.10mm (min)
Jiang Nan High Density Interconnection
Pisa Tower 封装基板
材料规格
HDI Substrate
导体表面处理 Max. 金厚 积层铜厚
Core外层铜厚 Core内层铜厚 机械孔孔壁铜厚 积层绝缘层材料 积层绝缘层厚度
HDI Substrate
“Pisa Tower” 封装基板 简介
2011-04
Jiang Nan High Density Interconnection
需求与技术驱动
产品发展趋向
HDI Substrate
Jiang Nan High Density Interconnection
需求与技术驱动
Jiang Nan High Density Interconnection
Pisa Tower 封装基板
HDI Substrate
样品信息: 铜柱数量:160 0000 积层结构: 4+10+4
可靠性测试结果
线宽/间距:0.035mm/0.035mm 积层绝缘层厚度:0.04mm
测试项目
Thermal Stress Test (Solder Dip) Temperature Cycling Test (Air to Air) Air Reflow
0.130 mm (min)
SM defined bump 开口
Bump annular ring for SM defined bump opening
积层线路宽度
0.1+/-0.01mm 0.015mm(min) 0.025mm (min)
积层线路间距
0.025mm (min)
局部线路宽度 局部线路间距
铜柱直径 铜柱捕捉盘直径 Core外层上的线路宽度 Core外层上的线路间距 Core内层上的线路宽度 Core内层上的线路间距
阻抗控制 Core上机械孔直径 Core上机械孔环宽
HDI Substrate
0.02mm(min) 0.02mm(min) 0.065mm (min) 0.115mm (min) 0.075mm (min) 0.075mm (min) 0.05mm (min) 0.05mm (min)
Jiang Nan High Density Interconnection
Pisa Tower 封装基板
捕捉盘
目标盘
铜柱 绝缘层
HDI Substrate
铜柱作为两层间的互连
Jiang Nan High Density Interconnection
Pisa Tower 封装基板
典型积层4+4+4 封装基板
HDI Substrate
Thank You！
Jiang Nan High Density Interconnection
-- Wire bond pitch has become bottle neck for further die shrink
外形因子 -- Allow smaller package than WB BGA with given die size -- Thinner package is possible