硅片分选机

光伏硅片检测知识普及HE-WI-05 Jan. 2014Process Intelligence (1)M e y e r B u r g e r / 12-10-052Data TrackingBack couplingMB CellMeasurementMB Modul TesterProcess Intelligence (2)Process know-how over the complete wafer, cell and Module production. Material tracking system for all PV processes (HSC -SEMI -Code) Data collection for all processesBack coupling of the results to optimize the productionM e y e r B u r g e r / 12-10-053A new standard forM e y e r B u r g e r / 12-10-054Hennecke WIS-05Roughness Module (1)Why should roughness be measured?The roughness is one important physical quantity for high efficientsolar wafers/cells.Saw mark module is replaced by the advanced Roughness Module Advantages:Additionally to saw mark groove and waviness the roughness values Ra, Rq and Rz can be measured.Up to three measuring tracks on both sides of the wafer are inspected by laser line projections.The lateral resolution along the laser line increases by a factor of4.narrow saw marks can be detectedSlurry cut wafers, very shining diamond wire cut wafers as well as etched wafers can be evaluated regarding saw mark defects.Measurement according to DIN, ISO and JIS standard.Technology powered by5Technology poweredby6Roughness Module (2)Easy upgrade of existing Wafer Inspection Systems (HE-WI 04) Familiar Hennecke user interface Throughput 3600 W/hTechnology poweredbyThe module HE-PED-02 is already integrated in the HE-WI 05.It can also be integrated in the HE-WIS-04.7PED Module (1)PED Module (2)Advantages:Only the Hennecke PED (HE-PED-02) enables the uniqueinspection of all chamfer types (pseudo square and squaregeometry)!Camera resolution of 12 µm instead of 21 µm of the HE-PED-01Not detectable defects of the standard edge defect detection system become visible.Detection of edge defects, which previously only could be detected by eye examination of a wafer stack.Includes a software tool for the Wafer Tracking System (WTS) toread our SEMI standardized new HSC-Code (Hennecke-Systems-Compressed Code)Optimize your wafering processTechnology powered by8Technology poweredby9PED Module (3)PED: Examination of the wafer edges perpendicularly.WaferEdge DefectStandard Edge Defect Module:Technology poweredby10PED Module (4)ChippingsTypical break outs / chippings on a glue side edgeBreak out / chipping on a chamfer (here: pseudo square wafer)Technology powered by11PED Module (5)Easy upgrade of existing lines due to the modular designPerfect integration in the Hennecke Wafer Inspection tool, including recipes & sortingResolution 21µm x 12 µm for the leading/trailing edge examination Resolution 15 µm for the lateral edge examination 3600 W/h inlinePED moduleLength: 1250 mmTechnology poweredby12PL Module (1)Issues:All wafers, also the bad ones from the edges of the ingot are processed Wafers containing many dislocation clusters are processed The resulting cells will fail during efficiency testThis means a loss of money for the processing costs of bad wafersSolution:Discard bad wafers before processingSeparate «standard» from «premium» quality wafersTechnology powered by13PL Module (2)Quality issue 1:Wafers from edge of ingot have low lifetime as a result of contamination by metallic impuritiesµ-PCD lifetime mapping of as-cut wafer from corner brickµ-PCD lifetime mapping of ingotRed: Low lifetime, bad quality Blue: High lifetime, good qualityTechnology powered by14PL Module (3)Quality issue 2:Dislocation clusters reduce the cell efficiency Crystal boundaries reduce the cell efficiencyDislocation ClusterCrystal boundariesTechnology powered by15PL Module (4)Save money by rejecting and not further processing bad wafers Earn money by processing wafers with forecasted high efficiencygood waferdislocation clusterscorner brick waferTechnology poweredby16PL Module (5)Photoluminescence of as-cut wafers:•Visualisation of low-lifetime regions •Predict cell efficiency •High resolution •Fast•Non touching technologyCameraFilterLaserWafer17Efficiency forecast model:Key metrics analyzed by softwareRed : Dislocation Clusters Violet: Crystal Boundaries Blue: Impuritiespremiumstandardbad wafersachievable cell efficiencyMeasure wafer and predict the later cell efficiencyPL Module (6)A p r i l2013,H e n n e c k e18Efficiency forecast model:Key metrics analyzed by softwareRed : Dislocation Clusters Violet: Crystal Boundaries Blue: Impuritiespremiumstandardbad wafersachievable cell efficiencyREJECT Normal Process For high efficiency cells PL Module (6)Technology poweredby19PL Module (7)Good Operating Procedure for cell producers:Measure and classify wafers using Hennecke Photoluminescence System Discard bad wafers and claim at wafer manufacturer Use standard wafers for producing standard quality cells Use premium wafers for premium quality cell lineTechnology poweredby20PL Module (8)Return of investment calculationCase Study: 5 % of bad wafers are discarded to increase the medium absolute efficiency of cells by 0,07%. 100MW wafer factory.Increase of 2,33 Million $ per year by using PL-improved production.This means: Return of investment within one month!Technology poweredby 21PL Module (9)Technology poweredby The double indexer HE-DI-02 is replaced by the new HE-DI-02b in the HE-WI 05.22Upgrade Double Indexer (1)Technology powered by Advantages:With those two magazines up to six carriers at one turn instead of only two carriers can be placed on the DI.less operator expenditures for the customeroperator action break of more than 2 min instead of about 40 s One operator can handle up to three lines in parallel.Less production down time due to fixed carrier positions in magazines.Slightly increased throughput (> 3%).Easy upgrade of a normal DI 23Upgrade Double Indexer (2)XTechnology poweredby The sorter HE-WS-02 is replaced by the new HE-DI-03 in the HE-WI 05.24Upgrade Sorter (1)Brick Slice Code (1)Why should Brick Slice Code be used?Monitoring the material chain along thewhole process chain.Process data of bricks and wafers arecollected automatically.Ability to improve various processsteps.Production can run on bestefficiencyHSC-Code is SEMI standardized(Semi PV32)Easy upgrade of existing linesTechnology powered by26Brick Slice Code (2)Two separate Codes are marked bylaser on 1 or 2 sides of the brickBrick-ID: worldwide unique codeSlice-ID: exact position within thebrick of every single waferAfter sawing, the code is readableon every waferAbility of tracking …missing“ waferNo scribing at active cell surfaceNo efficiency influenceNo influence of breakage rateSuitable for mono and polyTechnology powered by27Technology poweredby 28BSC -tracking starts after brick coding with feedback to crystallisation DMC -tracking starts after wafer cleaningBrick Slice Code (3)Technology poweredby 29Brick Slice Code (4)Technology poweredby 30 Mark depth/width:30 x 120 µmNo measurable effect on the breakage rate in production If 2 sides of the brick aremarked, no need to have control of the wafer orientationBrick Slice Code (5)Technology poweredby 31Reading at the entrance of Hennecke’s wafer inspectionBrick Slice Code (6)Technology poweredby 32Brick Slice Code (7)Cell reading with transmitted light reader Extra-thin backlight for easy integration答疑时间Technology powered by33。