EDA作业的参考答案

3.3参考答案（以下答案不是唯一，可以有不同的描述）library ieee;
use ieee.std_logic_1164.all;
entity MUXA is
port(a1,a2,a3 :in std_logic;
s0,s1 :in std_logic;
outy :out std_logic
);
end entity MUXA;
architecture mu of MUXA is
signal tmp :std_logic;
begin
process(a2,a3,s0) begin
case s0 is
when '0'=> tmp<=a2;
when '1'=> tmp<=a3;
when others =>null;
end case;
end process;
process(a1,tmp,s1) begin
case s1 is
when '0'=> outy<=a1;
when '1'=> outy<=tmp;
when others =>null;
end case;
end process;
end architecture mu;
3.7参考答案
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_SUBER IS
PORT ( X, Y : IN STD_LOGIC;
DIFF : OUT STD_LOGIC;
S_OUT : OUT STD_LOGIC );
END H_SUBER;
ARCHITECTURE ONE OF H_SUBER IS
SIGNAL XY, DS : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
XY <= X & Y; DIFF <= DS(1); S_OUT <= DS(0);
PROCESS (XY)
BEGIN
CASE (XY) IS
WHEN "00" => DS <= "00";
WHEN "01" => DS <= "11";
WHEN "10" => DS <= "10";
WHEN "11" => DS <= "00";
END CASE;
END PROCESS;
END ONE;
-- 一位二进制全减器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY F_SUBER IS
PORT ( X, Y : IN STD_LOGIC;
SUB_IN : IN STD_LOGIC;
DIFFR : OUT STD_LOGIC;
SUB_OUT : OUT STD_LOGIC);
END F_SUBER;
ARCHITECTURE BEHAV OF F_SUBER IS
COMPONENT H_SUBER IS
PORT ( X, Y : IN STD_LOGIC;
DIFF : OUT STD_LOGIC;
S_OUT : OUT STD_LOGIC );
END COMPONENT;
SIGNAL A, B, C : STD_LOGIC; -- 元件之间的连线，DIFF->X, S_OUT->或门, S_OUT->或门BEGIN
U1 : H_SUBER PORT MAP (X => X, Y => Y, DIFF => A, S_OUT => B);
U2 : H_SUBER PORT MAP (X => A, Y => SUB_IN, DIFF => DIFFR, S_OUT => C);
SUB_OUT <= B OR C;
END BEHAV;
-- 8位全减器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EX3_5 IS
PORT ( X, Y : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SUB_IN : IN STD_LOGIC;
DIFFER : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
SUB_OUT : OUT STD_LOGIC);
END EX3_5;
ARCHITECTURE ONE OF EX3_5 IS
COMPONENT F_SUBER IS
PORT ( X, Y : IN STD_LOGIC;
SUB_IN : IN STD_LOGIC;
DIFFR : OUT STD_LOGIC;
SUB_OUT : OUT STD_LOGIC);
END COMPONENT;
SIGNAL TMP : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
U1 : F_SUBER PORT MAP (X => X(0), Y => Y(0), SUB_IN => SUB_IN, DIFFR => DIFFER(0), SUB_OUT => TMP(0));
U2 : F_SUBER PORT MAP (X => X(1), Y => Y(1), SUB_IN => TMP(0), DIFFR => DIFFER(1), SUB_OUT => TMP(1));
U3 : F_SUBER PORT MAP (X => X(2), Y => Y(2), SUB_IN => TMP(1), DIFFR => DIFFER(2), SUB_OUT => TMP(2));
U4 : F_SUBER PORT MAP (X => X(3), Y => Y(3), SUB_IN => TMP(2), DIFFR => DIFFER(3), SUB_OUT => TMP(3));
U5 : F_SUBER PORT MAP (X => X(4), Y => Y(4), SUB_IN => TMP(3), DIFFR => DIFFER(4), SUB_OUT => TMP(4));
U6 : F_SUBER PORT MAP (X => X(5), Y => Y(5), SUB_IN => TMP(4), DIFFR => DIFFER(5), SUB_OUT => TMP(5));
U7 : F_SUBER PORT MAP (X => X(6), Y => Y(6), SUB_IN => TMP(5), DIFFR => DIFFER(6), SUB_OUT => TMP(6));
U8 : F_SUBER PORT MAP (X => X(7), Y => Y(7), SUB_IN => TMP(6), DIFFR => DIFFER(7), SUB_OUT => SUB_OUT);
END ONE;。